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Commit | Line | Data |
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c7a34993 MM |
1 | /* |
2 | * The PCI Utilities -- Show Extended Capabilities | |
3 | * | |
2849db67 | 4 | * Copyright (c) 1997--2022 Martin Mares <mj@ucw.cz> |
c7a34993 MM |
5 | * |
6 | * Can be freely distributed and used under the terms of the GNU GPL. | |
7 | */ | |
8 | ||
9 | #include <stdio.h> | |
10 | #include <string.h> | |
11 | ||
12 | #include "lspci.h" | |
13 | ||
67da1792 MM |
14 | static void |
15 | cap_tph(struct device *d, int where) | |
16 | { | |
17 | u32 tph_cap; | |
18 | printf("Transaction Processing Hints\n"); | |
19 | if (verbose < 2) | |
20 | return; | |
21 | ||
22 | if (!config_fetch(d, where + PCI_TPH_CAPABILITIES, 4)) | |
23 | return; | |
24 | ||
25 | tph_cap = get_conf_long(d, where + PCI_TPH_CAPABILITIES); | |
26 | ||
27 | if (tph_cap & PCI_TPH_INTVEC_SUP) | |
28 | printf("\t\tInterrupt vector mode supported\n"); | |
29 | if (tph_cap & PCI_TPH_DEV_SUP) | |
30 | printf("\t\tDevice specific mode supported\n"); | |
31 | if (tph_cap & PCI_TPH_EXT_REQ_SUP) | |
32 | printf("\t\tExtended requester support\n"); | |
33 | ||
34 | switch (tph_cap & PCI_TPH_ST_LOC_MASK) { | |
35 | case PCI_TPH_ST_NONE: | |
36 | printf("\t\tNo steering table available\n"); | |
37 | break; | |
38 | case PCI_TPH_ST_CAP: | |
39 | printf("\t\tSteering table in TPH capability structure\n"); | |
40 | break; | |
41 | case PCI_TPH_ST_MSIX: | |
42 | printf("\t\tSteering table in MSI-X table\n"); | |
43 | break; | |
44 | default: | |
45 | printf("\t\tReserved steering table location\n"); | |
46 | break; | |
47 | } | |
48 | } | |
49 | ||
50 | static u32 | |
51 | cap_ltr_scale(u8 scale) | |
52 | { | |
53 | return 1 << (scale * 5); | |
54 | } | |
55 | ||
56 | static void | |
57 | cap_ltr(struct device *d, int where) | |
58 | { | |
59 | u32 scale; | |
60 | u16 snoop, nosnoop; | |
61 | printf("Latency Tolerance Reporting\n"); | |
62 | if (verbose < 2) | |
63 | return; | |
64 | ||
65 | if (!config_fetch(d, where + PCI_LTR_MAX_SNOOP, 4)) | |
66 | return; | |
67 | ||
68 | snoop = get_conf_word(d, where + PCI_LTR_MAX_SNOOP); | |
69 | scale = cap_ltr_scale((snoop >> PCI_LTR_SCALE_SHIFT) & PCI_LTR_SCALE_MASK); | |
c3d1d465 | 70 | printf("\t\tMax snoop latency: %" PCI_U64_FMT_U "ns\n", |
6811edb8 | 71 | ((u64)snoop & PCI_LTR_VALUE_MASK) * scale); |
67da1792 MM |
72 | |
73 | nosnoop = get_conf_word(d, where + PCI_LTR_MAX_NOSNOOP); | |
74 | scale = cap_ltr_scale((nosnoop >> PCI_LTR_SCALE_SHIFT) & PCI_LTR_SCALE_MASK); | |
c3d1d465 | 75 | printf("\t\tMax no snoop latency: %" PCI_U64_FMT_U "ns\n", |
6811edb8 | 76 | ((u64)nosnoop & PCI_LTR_VALUE_MASK) * scale); |
67da1792 MM |
77 | } |
78 | ||
21ff9851 | 79 | static void |
9225e71d | 80 | cap_sec(struct device *d, int where) |
21ff9851 B |
81 | { |
82 | u32 ctrl3, lane_err_stat; | |
83 | u8 lane; | |
84 | printf("Secondary PCI Express\n"); | |
9225e71d | 85 | if (verbose < 2) |
21ff9851 B |
86 | return; |
87 | ||
88 | if (!config_fetch(d, where + PCI_SEC_LNKCTL3, 12)) | |
89 | return; | |
90 | ||
91 | ctrl3 = get_conf_word(d, where + PCI_SEC_LNKCTL3); | |
018f413c | 92 | printf("\t\tLnkCtl3: LnkEquIntrruptEn%c PerformEqu%c\n", |
21ff9851 B |
93 | FLAG(ctrl3, PCI_SEC_LNKCTL3_LNK_EQU_REQ_INTR_EN), |
94 | FLAG(ctrl3, PCI_SEC_LNKCTL3_PERFORM_LINK_EQU)); | |
95 | ||
96 | lane_err_stat = get_conf_word(d, where + PCI_SEC_LANE_ERR); | |
97 | printf("\t\tLaneErrStat: "); | |
98 | if (lane_err_stat) | |
99 | { | |
9f7dc65c | 100 | printf("LaneErr at lane:"); |
21ff9851 B |
101 | for (lane = 0; lane_err_stat; lane_err_stat >>= 1, lane += 1) |
102 | if (BITS(lane_err_stat, 0, 1)) | |
103 | printf(" %u", lane); | |
104 | } | |
105 | else | |
106 | printf("0"); | |
107 | printf("\n"); | |
108 | } | |
109 | ||
c7a34993 MM |
110 | static void |
111 | cap_dsn(struct device *d, int where) | |
112 | { | |
113 | u32 t1, t2; | |
114 | if (!config_fetch(d, where + 4, 8)) | |
115 | return; | |
116 | t1 = get_conf_long(d, where + 4); | |
117 | t2 = get_conf_long(d, where + 8); | |
118 | printf("Device Serial Number %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", | |
6f9f8fd7 MW |
119 | t2 >> 24, (t2 >> 16) & 0xff, (t2 >> 8) & 0xff, t2 & 0xff, |
120 | t1 >> 24, (t1 >> 16) & 0xff, (t1 >> 8) & 0xff, t1 & 0xff); | |
c7a34993 MM |
121 | } |
122 | ||
123 | static void | |
a1492b88 | 124 | cap_aer(struct device *d, int where, int type) |
c7a34993 | 125 | { |
a6625432 | 126 | u32 l, l0, l1, l2, l3; |
a1492b88 | 127 | u16 w; |
c7a34993 MM |
128 | |
129 | printf("Advanced Error Reporting\n"); | |
9a2e4b35 YZ |
130 | if (verbose < 2) |
131 | return; | |
132 | ||
a6625432 | 133 | if (!config_fetch(d, where + PCI_ERR_UNCOR_STATUS, 40)) |
c7a34993 MM |
134 | return; |
135 | ||
136 | l = get_conf_long(d, where + PCI_ERR_UNCOR_STATUS); | |
137 | printf("\t\tUESta:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c " | |
138 | "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n", | |
139 | FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP), | |
140 | FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT), | |
141 | FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP), | |
142 | FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL)); | |
143 | l = get_conf_long(d, where + PCI_ERR_UNCOR_MASK); | |
144 | printf("\t\tUEMsk:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c " | |
145 | "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n", | |
146 | FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP), | |
147 | FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT), | |
148 | FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP), | |
149 | FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL)); | |
150 | l = get_conf_long(d, where + PCI_ERR_UNCOR_SEVER); | |
151 | printf("\t\tUESvrt:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c " | |
152 | "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n", | |
153 | FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP), | |
154 | FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT), | |
155 | FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP), | |
156 | FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL)); | |
157 | l = get_conf_long(d, where + PCI_ERR_COR_STATUS); | |
aca48104 | 158 | printf("\t\tCESta:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c AdvNonFatalErr%c\n", |
c7a34993 MM |
159 | FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP), |
160 | FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE)); | |
161 | l = get_conf_long(d, where + PCI_ERR_COR_MASK); | |
aca48104 | 162 | printf("\t\tCEMsk:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c AdvNonFatalErr%c\n", |
c7a34993 MM |
163 | FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP), |
164 | FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE)); | |
165 | l = get_conf_long(d, where + PCI_ERR_CAP); | |
9a54979e | 166 | printf("\t\tAERCap:\tFirst Error Pointer: %02x, ECRCGenCap%c ECRCGenEn%c ECRCChkCap%c ECRCChkEn%c\n" |
b33a4a2b | 167 | "\t\t\tMultHdrRecCap%c MultHdrRecEn%c TLPPfxPres%c HdrLogCap%c\n", |
c7a34993 | 168 | PCI_ERR_CAP_FEP(l), FLAG(l, PCI_ERR_CAP_ECRC_GENC), FLAG(l, PCI_ERR_CAP_ECRC_GENE), |
b33a4a2b BH |
169 | FLAG(l, PCI_ERR_CAP_ECRC_CHKC), FLAG(l, PCI_ERR_CAP_ECRC_CHKE), |
170 | FLAG(l, PCI_ERR_CAP_MULT_HDRC), FLAG(l, PCI_ERR_CAP_MULT_HDRE), | |
171 | FLAG(l, PCI_ERR_CAP_TLP_PFX), FLAG(l, PCI_ERR_CAP_HDR_LOG)); | |
a6625432 BH |
172 | |
173 | l0 = get_conf_long(d, where + PCI_ERR_HEADER_LOG); | |
174 | l1 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 4); | |
175 | l2 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 8); | |
176 | l3 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 12); | |
177 | printf("\t\tHeaderLog: %08x %08x %08x %08x\n", l0, l1, l2, l3); | |
a1492b88 BH |
178 | |
179 | if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ROOT_EC) | |
180 | { | |
181 | if (!config_fetch(d, where + PCI_ERR_ROOT_COMMAND, 12)) | |
182 | return; | |
183 | ||
184 | l = get_conf_long(d, where + PCI_ERR_ROOT_COMMAND); | |
185 | printf("\t\tRootCmd: CERptEn%c NFERptEn%c FERptEn%c\n", | |
186 | FLAG(l, PCI_ERR_ROOT_CMD_COR_EN), | |
187 | FLAG(l, PCI_ERR_ROOT_CMD_NONFATAL_EN), | |
188 | FLAG(l, PCI_ERR_ROOT_CMD_FATAL_EN)); | |
189 | ||
190 | l = get_conf_long(d, where + PCI_ERR_ROOT_STATUS); | |
191 | printf("\t\tRootSta: CERcvd%c MultCERcvd%c UERcvd%c MultUERcvd%c\n" | |
192 | "\t\t\t FirstFatal%c NonFatalMsg%c FatalMsg%c IntMsg %d\n", | |
193 | FLAG(l, PCI_ERR_ROOT_COR_RCV), | |
194 | FLAG(l, PCI_ERR_ROOT_MULTI_COR_RCV), | |
195 | FLAG(l, PCI_ERR_ROOT_UNCOR_RCV), | |
196 | FLAG(l, PCI_ERR_ROOT_MULTI_UNCOR_RCV), | |
197 | FLAG(l, PCI_ERR_ROOT_FIRST_FATAL), | |
198 | FLAG(l, PCI_ERR_ROOT_NONFATAL_RCV), | |
199 | FLAG(l, PCI_ERR_ROOT_FATAL_RCV), | |
200 | PCI_ERR_MSG_NUM(l)); | |
201 | ||
202 | w = get_conf_word(d, where + PCI_ERR_ROOT_COR_SRC); | |
203 | printf("\t\tErrorSrc: ERR_COR: %04x ", w); | |
204 | ||
205 | w = get_conf_word(d, where + PCI_ERR_ROOT_SRC); | |
206 | printf("ERR_FATAL/NONFATAL: %04x\n", w); | |
207 | } | |
c7a34993 MM |
208 | } |
209 | ||
de91b6f2 KB |
210 | static void cap_dpc(struct device *d, int where) |
211 | { | |
212 | u16 l; | |
213 | ||
214 | printf("Downstream Port Containment\n"); | |
215 | if (verbose < 2) | |
216 | return; | |
217 | ||
218 | if (!config_fetch(d, where + PCI_DPC_CAP, 8)) | |
219 | return; | |
220 | ||
221 | l = get_conf_word(d, where + PCI_DPC_CAP); | |
222 | printf("\t\tDpcCap:\tINT Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n", | |
223 | PCI_DPC_CAP_INT_MSG(l), FLAG(l, PCI_DPC_CAP_RP_EXT), FLAG(l, PCI_DPC_CAP_TLP_BLOCK), | |
224 | FLAG(l, PCI_DPC_CAP_SW_TRIGGER), PCI_DPC_CAP_RP_LOG(l), FLAG(l, PCI_DPC_CAP_DL_ACT_ERR)); | |
225 | ||
226 | l = get_conf_word(d, where + PCI_DPC_CTL); | |
227 | printf("\t\tDpcCtl:\tTrigger:%x Cmpl%c INT%c ErrCor%c PoisonedTLP%c SwTrigger%c DL_ActiveErr%c\n", | |
228 | PCI_DPC_CTL_TRIGGER(l), FLAG(l, PCI_DPC_CTL_CMPL), FLAG(l, PCI_DPC_CTL_INT), | |
229 | FLAG(l, PCI_DPC_CTL_ERR_COR), FLAG(l, PCI_DPC_CTL_TLP), FLAG(l, PCI_DPC_CTL_SW_TRIGGER), | |
230 | FLAG(l, PCI_DPC_CTL_DL_ACTIVE)); | |
231 | ||
232 | l = get_conf_word(d, where + PCI_DPC_STATUS); | |
233 | printf("\t\tDpcSta:\tTrigger%c Reason:%02x INT%c RPBusy%c TriggerExt:%02x RP PIO ErrPtr:%02x\n", | |
234 | FLAG(l, PCI_DPC_STS_TRIGGER), PCI_DPC_STS_REASON(l), FLAG(l, PCI_DPC_STS_INT), | |
235 | FLAG(l, PCI_DPC_STS_RP_BUSY), PCI_DPC_STS_TRIGGER_EXT(l), PCI_DPC_STS_PIO_FEP(l)); | |
236 | ||
237 | l = get_conf_word(d, where + PCI_DPC_SOURCE); | |
238 | printf("\t\tSource:\t%04x\n", l); | |
239 | } | |
240 | ||
c7a34993 MM |
241 | static void |
242 | cap_acs(struct device *d, int where) | |
243 | { | |
244 | u16 w; | |
245 | ||
246 | printf("Access Control Services\n"); | |
9a2e4b35 YZ |
247 | if (verbose < 2) |
248 | return; | |
249 | ||
c7a34993 MM |
250 | if (!config_fetch(d, where + PCI_ACS_CAP, 4)) |
251 | return; | |
252 | ||
253 | w = get_conf_word(d, where + PCI_ACS_CAP); | |
254 | printf("\t\tACSCap:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c " | |
255 | "DirectTrans%c\n", | |
256 | FLAG(w, PCI_ACS_CAP_VALID), FLAG(w, PCI_ACS_CAP_BLOCK), FLAG(w, PCI_ACS_CAP_REQ_RED), | |
257 | FLAG(w, PCI_ACS_CAP_CMPLT_RED), FLAG(w, PCI_ACS_CAP_FORWARD), FLAG(w, PCI_ACS_CAP_EGRESS), | |
258 | FLAG(w, PCI_ACS_CAP_TRANS)); | |
259 | w = get_conf_word(d, where + PCI_ACS_CTRL); | |
260 | printf("\t\tACSCtl:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c " | |
261 | "DirectTrans%c\n", | |
262 | FLAG(w, PCI_ACS_CTRL_VALID), FLAG(w, PCI_ACS_CTRL_BLOCK), FLAG(w, PCI_ACS_CTRL_REQ_RED), | |
263 | FLAG(w, PCI_ACS_CTRL_CMPLT_RED), FLAG(w, PCI_ACS_CTRL_FORWARD), FLAG(w, PCI_ACS_CTRL_EGRESS), | |
264 | FLAG(w, PCI_ACS_CTRL_TRANS)); | |
265 | } | |
266 | ||
267 | static void | |
268 | cap_ari(struct device *d, int where) | |
269 | { | |
270 | u16 w; | |
271 | ||
272 | printf("Alternative Routing-ID Interpretation (ARI)\n"); | |
9a2e4b35 YZ |
273 | if (verbose < 2) |
274 | return; | |
275 | ||
c7a34993 MM |
276 | if (!config_fetch(d, where + PCI_ARI_CAP, 4)) |
277 | return; | |
278 | ||
279 | w = get_conf_word(d, where + PCI_ARI_CAP); | |
280 | printf("\t\tARICap:\tMFVC%c ACS%c, Next Function: %d\n", | |
281 | FLAG(w, PCI_ARI_CAP_MFVC), FLAG(w, PCI_ARI_CAP_ACS), | |
282 | PCI_ARI_CAP_NFN(w)); | |
283 | w = get_conf_word(d, where + PCI_ARI_CTRL); | |
284 | printf("\t\tARICtl:\tMFVC%c ACS%c, Function Group: %d\n", | |
285 | FLAG(w, PCI_ARI_CTRL_MFVC), FLAG(w, PCI_ARI_CTRL_ACS), | |
286 | PCI_ARI_CTRL_FG(w)); | |
287 | } | |
288 | ||
289 | static void | |
290 | cap_ats(struct device *d, int where) | |
291 | { | |
292 | u16 w; | |
293 | ||
294 | printf("Address Translation Service (ATS)\n"); | |
9a2e4b35 YZ |
295 | if (verbose < 2) |
296 | return; | |
297 | ||
c7a34993 MM |
298 | if (!config_fetch(d, where + PCI_ATS_CAP, 4)) |
299 | return; | |
300 | ||
301 | w = get_conf_word(d, where + PCI_ATS_CAP); | |
302 | printf("\t\tATSCap:\tInvalidate Queue Depth: %02x\n", PCI_ATS_CAP_IQD(w)); | |
303 | w = get_conf_word(d, where + PCI_ATS_CTRL); | |
304 | printf("\t\tATSCtl:\tEnable%c, Smallest Translation Unit: %02x\n", | |
305 | FLAG(w, PCI_ATS_CTRL_ENABLE), PCI_ATS_CTRL_STU(w)); | |
306 | } | |
307 | ||
a858df0d DW |
308 | static void |
309 | cap_pri(struct device *d, int where) | |
310 | { | |
311 | u16 w; | |
312 | u32 l; | |
313 | ||
314 | printf("Page Request Interface (PRI)\n"); | |
315 | if (verbose < 2) | |
316 | return; | |
317 | ||
318 | if (!config_fetch(d, where + PCI_PRI_CTRL, 0xc)) | |
319 | return; | |
320 | ||
321 | w = get_conf_word(d, where + PCI_PRI_CTRL); | |
bfd8658f | 322 | printf("\t\tPRICtl: Enable%c Reset%c\n", |
a858df0d DW |
323 | FLAG(w, PCI_PRI_CTRL_ENABLE), FLAG(w, PCI_PRI_CTRL_RESET)); |
324 | w = get_conf_word(d, where + PCI_PRI_STATUS); | |
bfd8658f | 325 | printf("\t\tPRISta: RF%c UPRGI%c Stopped%c\n", |
a858df0d DW |
326 | FLAG(w, PCI_PRI_STATUS_RF), FLAG(w, PCI_PRI_STATUS_UPRGI), |
327 | FLAG(w, PCI_PRI_STATUS_STOPPED)); | |
328 | l = get_conf_long(d, where + PCI_PRI_MAX_REQ); | |
329 | printf("\t\tPage Request Capacity: %08x, ", l); | |
330 | l = get_conf_long(d, where + PCI_PRI_ALLOC_REQ); | |
331 | printf("Page Request Allocation: %08x\n", l); | |
332 | } | |
333 | ||
334 | static void | |
335 | cap_pasid(struct device *d, int where) | |
336 | { | |
337 | u16 w; | |
338 | ||
339 | printf("Process Address Space ID (PASID)\n"); | |
340 | if (verbose < 2) | |
341 | return; | |
342 | ||
343 | if (!config_fetch(d, where + PCI_PASID_CAP, 4)) | |
344 | return; | |
345 | ||
346 | w = get_conf_word(d, where + PCI_PASID_CAP); | |
bfd8658f | 347 | printf("\t\tPASIDCap: Exec%c Priv%c, Max PASID Width: %02x\n", |
a858df0d DW |
348 | FLAG(w, PCI_PASID_CAP_EXEC), FLAG(w, PCI_PASID_CAP_PRIV), |
349 | PCI_PASID_CAP_WIDTH(w)); | |
350 | w = get_conf_word(d, where + PCI_PASID_CTRL); | |
bfd8658f | 351 | printf("\t\tPASIDCtl: Enable%c Exec%c Priv%c\n", |
a858df0d DW |
352 | FLAG(w, PCI_PASID_CTRL_ENABLE), FLAG(w, PCI_PASID_CTRL_EXEC), |
353 | FLAG(w, PCI_PASID_CTRL_PRIV)); | |
354 | } | |
355 | ||
c7a34993 MM |
356 | static void |
357 | cap_sriov(struct device *d, int where) | |
358 | { | |
359 | u16 b; | |
360 | u16 w; | |
361 | u32 l; | |
67e78b32 | 362 | int i; |
c7a34993 MM |
363 | |
364 | printf("Single Root I/O Virtualization (SR-IOV)\n"); | |
9a2e4b35 YZ |
365 | if (verbose < 2) |
366 | return; | |
367 | ||
c7a34993 MM |
368 | if (!config_fetch(d, where + PCI_IOV_CAP, 0x3c)) |
369 | return; | |
370 | ||
371 | l = get_conf_long(d, where + PCI_IOV_CAP); | |
053d08d2 DL |
372 | printf("\t\tIOVCap:\tMigration%c 10BitTagReq%c Interrupt Message Number: %03x\n", |
373 | FLAG(l, PCI_IOV_CAP_VFM), FLAG(l, PCI_IOV_CAP_VF_10BIT_TAG_REQ), PCI_IOV_CAP_IMN(l)); | |
c7a34993 | 374 | w = get_conf_word(d, where + PCI_IOV_CTRL); |
053d08d2 | 375 | printf("\t\tIOVCtl:\tEnable%c Migration%c Interrupt%c MSE%c ARIHierarchy%c 10BitTagReq%c\n", |
c7a34993 MM |
376 | FLAG(w, PCI_IOV_CTRL_VFE), FLAG(w, PCI_IOV_CTRL_VFME), |
377 | FLAG(w, PCI_IOV_CTRL_VFMIE), FLAG(w, PCI_IOV_CTRL_MSE), | |
053d08d2 | 378 | FLAG(w, PCI_IOV_CTRL_ARI), FLAG(w, PCI_IOV_CTRL_VF_10BIT_TAG_REQ_EN)); |
c7a34993 MM |
379 | w = get_conf_word(d, where + PCI_IOV_STATUS); |
380 | printf("\t\tIOVSta:\tMigration%c\n", FLAG(w, PCI_IOV_STATUS_MS)); | |
381 | w = get_conf_word(d, where + PCI_IOV_INITIALVF); | |
382 | printf("\t\tInitial VFs: %d, ", w); | |
383 | w = get_conf_word(d, where + PCI_IOV_TOTALVF); | |
384 | printf("Total VFs: %d, ", w); | |
385 | w = get_conf_word(d, where + PCI_IOV_NUMVF); | |
386 | printf("Number of VFs: %d, ", w); | |
387 | b = get_conf_byte(d, where + PCI_IOV_FDL); | |
388 | printf("Function Dependency Link: %02x\n", b); | |
389 | w = get_conf_word(d, where + PCI_IOV_OFFSET); | |
390 | printf("\t\tVF offset: %d, ", w); | |
391 | w = get_conf_word(d, where + PCI_IOV_STRIDE); | |
392 | printf("stride: %d, ", w); | |
393 | w = get_conf_word(d, where + PCI_IOV_DID); | |
394 | printf("Device ID: %04x\n", w); | |
395 | l = get_conf_long(d, where + PCI_IOV_SUPPS); | |
396 | printf("\t\tSupported Page Size: %08x, ", l); | |
397 | l = get_conf_long(d, where + PCI_IOV_SYSPS); | |
398 | printf("System Page Size: %08x\n", l); | |
b9e11c65 MM |
399 | |
400 | for (i=0; i < PCI_IOV_NUM_BAR; i++) | |
401 | { | |
187bf2f5 | 402 | u32 addr; |
b9e11c65 MM |
403 | int type; |
404 | u32 h; | |
405 | l = get_conf_long(d, where + PCI_IOV_BAR_BASE + 4*i); | |
406 | if (l == 0xffffffff) | |
407 | l = 0; | |
408 | if (!l) | |
409 | continue; | |
410 | printf("\t\tRegion %d: Memory at ", i); | |
411 | addr = l & PCI_ADDR_MEM_MASK; | |
412 | type = l & PCI_BASE_ADDRESS_MEM_TYPE_MASK; | |
413 | if (type == PCI_BASE_ADDRESS_MEM_TYPE_64) | |
414 | { | |
415 | i++; | |
416 | h = get_conf_long(d, where + PCI_IOV_BAR_BASE + (i*4)); | |
187bf2f5 | 417 | printf("%08x", h); |
b9e11c65 | 418 | } |
187bf2f5 MM |
419 | printf("%08x (%s-bit, %sprefetchable)\n", |
420 | addr, | |
b9e11c65 MM |
421 | (type == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32" : "64", |
422 | (l & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-"); | |
67e78b32 | 423 | } |
b9e11c65 | 424 | |
edca3520 | 425 | l = get_conf_long(d, where + PCI_IOV_MSAO); |
c7a34993 MM |
426 | printf("\t\tVF Migration: offset: %08x, BIR: %x\n", PCI_IOV_MSA_OFFSET(l), |
427 | PCI_IOV_MSA_BIR(l)); | |
428 | } | |
429 | ||
c0d9545c BH |
430 | static void |
431 | cap_multicast(struct device *d, int where, int type) | |
432 | { | |
433 | u16 w; | |
434 | u32 l; | |
435 | u64 bar, rcv, block; | |
436 | ||
437 | printf("Multicast\n"); | |
438 | if (verbose < 2) | |
439 | return; | |
440 | ||
441 | if (!config_fetch(d, where + PCI_MCAST_CAP, 0x30)) | |
442 | return; | |
443 | ||
444 | w = get_conf_word(d, where + PCI_MCAST_CAP); | |
445 | printf("\t\tMcastCap: MaxGroups %d", PCI_MCAST_CAP_MAX_GROUP(w) + 1); | |
446 | if (type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_ROOT_INT_EP) | |
447 | printf(", WindowSz %d (%d bytes)", | |
448 | PCI_MCAST_CAP_WIN_SIZE(w), 1 << PCI_MCAST_CAP_WIN_SIZE(w)); | |
449 | if (type == PCI_EXP_TYPE_ROOT_PORT || | |
450 | type == PCI_EXP_TYPE_UPSTREAM || type == PCI_EXP_TYPE_DOWNSTREAM) | |
451 | printf(", ECRCRegen%c\n", FLAG(w, PCI_MCAST_CAP_ECRC)); | |
452 | w = get_conf_word(d, where + PCI_MCAST_CTRL); | |
453 | printf("\t\tMcastCtl: NumGroups %d, Enable%c\n", | |
454 | PCI_MCAST_CTRL_NUM_GROUP(w) + 1, FLAG(w, PCI_MCAST_CTRL_ENABLE)); | |
455 | bar = get_conf_long(d, where + PCI_MCAST_BAR); | |
456 | l = get_conf_long(d, where + PCI_MCAST_BAR + 4); | |
457 | bar |= (u64) l << 32; | |
458 | printf("\t\tMcastBAR: IndexPos %d, BaseAddr %016" PCI_U64_FMT_X "\n", | |
459 | PCI_MCAST_BAR_INDEX_POS(bar), bar & PCI_MCAST_BAR_MASK); | |
460 | rcv = get_conf_long(d, where + PCI_MCAST_RCV); | |
461 | l = get_conf_long(d, where + PCI_MCAST_RCV + 4); | |
462 | rcv |= (u64) l << 32; | |
463 | printf("\t\tMcastReceiveVec: %016" PCI_U64_FMT_X "\n", rcv); | |
464 | block = get_conf_long(d, where + PCI_MCAST_BLOCK); | |
465 | l = get_conf_long(d, where + PCI_MCAST_BLOCK + 4); | |
466 | block |= (u64) l << 32; | |
467 | printf("\t\tMcastBlockAllVec: %016" PCI_U64_FMT_X "\n", block); | |
468 | block = get_conf_long(d, where + PCI_MCAST_BLOCK_UNTRANS); | |
469 | l = get_conf_long(d, where + PCI_MCAST_BLOCK_UNTRANS + 4); | |
470 | block |= (u64) l << 32; | |
471 | printf("\t\tMcastBlockUntransVec: %016" PCI_U64_FMT_X "\n", block); | |
472 | ||
473 | if (type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_ROOT_INT_EP) | |
474 | return; | |
475 | bar = get_conf_long(d, where + PCI_MCAST_OVL_BAR); | |
476 | l = get_conf_long(d, where + PCI_MCAST_OVL_BAR + 4); | |
477 | bar |= (u64) l << 32; | |
478 | printf("\t\tMcastOverlayBAR: OverlaySize %d ", PCI_MCAST_OVL_SIZE(bar)); | |
479 | if (PCI_MCAST_OVL_SIZE(bar) >= 6) | |
480 | printf("(%d bytes)", 1 << PCI_MCAST_OVL_SIZE(bar)); | |
481 | else | |
482 | printf("(disabled)"); | |
483 | printf(", BaseAddr %016" PCI_U64_FMT_X "\n", bar & PCI_MCAST_OVL_MASK); | |
484 | } | |
485 | ||
33088c24 MM |
486 | static void |
487 | cap_vc(struct device *d, int where) | |
488 | { | |
489 | u32 cr1, cr2; | |
490 | u16 ctrl, status; | |
491 | int evc_cnt; | |
492 | int arb_table_pos; | |
493 | int i, j; | |
3d8b5258 | 494 | static const char ref_clocks[][6] = { "100ns" }; |
3edae14a MM |
495 | static const char arb_selects[8][7] = { "Fixed", "WRR32", "WRR64", "WRR128", "??4", "??5", "??6", "??7" }; |
496 | static const char vc_arb_selects[8][8] = { "Fixed", "WRR32", "WRR64", "WRR128", "TWRR128", "WRR256", "??6", "??7" }; | |
3d8b5258 | 497 | char buf[8]; |
33088c24 MM |
498 | |
499 | printf("Virtual Channel\n"); | |
500 | if (verbose < 2) | |
501 | return; | |
502 | ||
503 | if (!config_fetch(d, where + 4, 0x1c - 4)) | |
504 | return; | |
505 | ||
506 | cr1 = get_conf_long(d, where + PCI_VC_PORT_REG1); | |
507 | cr2 = get_conf_long(d, where + PCI_VC_PORT_REG2); | |
508 | ctrl = get_conf_word(d, where + PCI_VC_PORT_CTRL); | |
509 | status = get_conf_word(d, where + PCI_VC_PORT_STATUS); | |
510 | ||
3d8b5258 | 511 | evc_cnt = BITS(cr1, 0, 3); |
d676f20d | 512 | printf("\t\tCaps:\tLPEVC=%d RefClk=%s PATEntryBits=%d\n", |
3d8b5258 MM |
513 | BITS(cr1, 4, 3), |
514 | TABLE(ref_clocks, BITS(cr1, 8, 2), buf), | |
d676f20d | 515 | 1 << BITS(cr1, 10, 2)); |
33088c24 | 516 | |
d676f20d | 517 | printf("\t\tArb:"); |
33088c24 MM |
518 | for (i=0; i<8; i++) |
519 | if (arb_selects[i][0] != '?' || cr2 & (1 << i)) | |
d676f20d | 520 | printf("%c%s%c", (i ? ' ' : '\t'), arb_selects[i], FLAG(cr2, 1 << i)); |
3d8b5258 | 521 | arb_table_pos = BITS(cr2, 24, 8); |
33088c24 | 522 | |
d676f20d | 523 | printf("\n\t\tCtrl:\tArbSelect=%s\n", TABLE(arb_selects, BITS(ctrl, 1, 3), buf)); |
33088c24 MM |
524 | printf("\t\tStatus:\tInProgress%c\n", FLAG(status, 1)); |
525 | ||
526 | if (arb_table_pos) | |
d676f20d MM |
527 | { |
528 | arb_table_pos = where + 16*arb_table_pos; | |
529 | printf("\t\tPort Arbitration Table [%x] <?>\n", arb_table_pos); | |
530 | } | |
33088c24 MM |
531 | |
532 | for (i=0; i<=evc_cnt; i++) | |
533 | { | |
534 | int pos = where + PCI_VC_RES_CAP + 12*i; | |
535 | u32 rcap, rctrl; | |
536 | u16 rstatus; | |
537 | int pat_pos; | |
538 | ||
5a9a932c | 539 | printf("\t\tVC%d:\t", i); |
33088c24 MM |
540 | if (!config_fetch(d, pos, 12)) |
541 | { | |
5a9a932c | 542 | printf("<unreadable>\n"); |
33088c24 MM |
543 | continue; |
544 | } | |
545 | rcap = get_conf_long(d, pos); | |
546 | rctrl = get_conf_long(d, pos+4); | |
7970509b | 547 | rstatus = get_conf_word(d, pos+10); |
33088c24 | 548 | |
3d8b5258 | 549 | pat_pos = BITS(rcap, 24, 8); |
5a9a932c | 550 | printf("Caps:\tPATOffset=%02x MaxTimeSlots=%d RejSnoopTrans%c\n", |
33088c24 | 551 | pat_pos, |
3711e86f | 552 | BITS(rcap, 16, 7) + 1, |
33088c24 MM |
553 | FLAG(rcap, 1 << 15)); |
554 | ||
555 | printf("\t\t\tArb:"); | |
556 | for (j=0; j<8; j++) | |
557 | if (vc_arb_selects[j][0] != '?' || rcap & (1 << j)) | |
558 | printf("%c%s%c", (j ? ' ' : '\t'), vc_arb_selects[j], FLAG(rcap, 1 << j)); | |
559 | ||
560 | printf("\n\t\t\tCtrl:\tEnable%c ID=%d ArbSelect=%s TC/VC=%02x\n", | |
561 | FLAG(rctrl, 1 << 31), | |
3d8b5258 MM |
562 | BITS(rctrl, 24, 3), |
563 | TABLE(vc_arb_selects, BITS(rctrl, 17, 3), buf), | |
564 | BITS(rctrl, 0, 8)); | |
33088c24 MM |
565 | |
566 | printf("\t\t\tStatus:\tNegoPending%c InProgress%c\n", | |
567 | FLAG(rstatus, 2), | |
568 | FLAG(rstatus, 1)); | |
569 | ||
570 | if (pat_pos) | |
571 | printf("\t\t\tPort Arbitration Table <?>\n"); | |
572 | } | |
573 | } | |
574 | ||
5a9a932c MM |
575 | static void |
576 | cap_rclink(struct device *d, int where) | |
577 | { | |
578 | u32 esd; | |
579 | int num_links; | |
580 | int i; | |
581 | static const char elt_types[][9] = { "Config", "Egress", "Internal" }; | |
582 | char buf[8]; | |
583 | ||
584 | printf("Root Complex Link\n"); | |
585 | if (verbose < 2) | |
586 | return; | |
587 | ||
588 | if (!config_fetch(d, where + 4, PCI_RCLINK_LINK1 - 4)) | |
589 | return; | |
590 | ||
591 | esd = get_conf_long(d, where + PCI_RCLINK_ESD); | |
592 | num_links = BITS(esd, 8, 8); | |
593 | printf("\t\tDesc:\tPortNumber=%02x ComponentID=%02x EltType=%s\n", | |
594 | BITS(esd, 24, 8), | |
595 | BITS(esd, 16, 8), | |
596 | TABLE(elt_types, BITS(esd, 0, 8), buf)); | |
597 | ||
598 | for (i=0; i<num_links; i++) | |
599 | { | |
600 | int pos = where + PCI_RCLINK_LINK1 + i*PCI_RCLINK_LINK_SIZE; | |
601 | u32 desc; | |
602 | u32 addr_lo, addr_hi; | |
603 | ||
604 | printf("\t\tLink%d:\t", i); | |
605 | if (!config_fetch(d, pos, PCI_RCLINK_LINK_SIZE)) | |
606 | { | |
607 | printf("<unreadable>\n"); | |
608 | return; | |
609 | } | |
610 | desc = get_conf_long(d, pos + PCI_RCLINK_LINK_DESC); | |
611 | addr_lo = get_conf_long(d, pos + PCI_RCLINK_LINK_ADDR); | |
612 | addr_hi = get_conf_long(d, pos + PCI_RCLINK_LINK_ADDR + 4); | |
613 | ||
614 | printf("Desc:\tTargetPort=%02x TargetComponent=%02x AssocRCRB%c LinkType=%s LinkValid%c\n", | |
615 | BITS(desc, 24, 8), | |
616 | BITS(desc, 16, 8), | |
617 | FLAG(desc, 4), | |
618 | ((desc & 2) ? "Config" : "MemMapped"), | |
619 | FLAG(desc, 1)); | |
620 | ||
621 | if (desc & 2) | |
622 | { | |
623 | int n = addr_lo & 7; | |
624 | if (!n) | |
625 | n = 8; | |
626 | printf("\t\t\tAddr:\t%02x:%02x.%d CfgSpace=%08x%08x\n", | |
627 | BITS(addr_lo, 20, n), | |
628 | BITS(addr_lo, 15, 5), | |
629 | BITS(addr_lo, 12, 3), | |
630 | addr_hi, addr_lo); | |
631 | } | |
632 | else | |
633 | printf("\t\t\tAddr:\t%08x%08x\n", addr_hi, addr_lo); | |
634 | } | |
635 | } | |
636 | ||
e12bd01e SK |
637 | static void |
638 | cap_rcec(struct device *d, int where) | |
639 | { | |
640 | printf("Root Complex Event Collector Endpoint Association\n"); | |
641 | if (verbose < 2) | |
642 | return; | |
643 | ||
644 | if (!config_fetch(d, where, 12)) | |
645 | return; | |
646 | ||
647 | u32 hdr = get_conf_long(d, where); | |
648 | byte cap_ver = PCI_RCEC_EP_CAP_VER(hdr); | |
649 | u32 bmap = get_conf_long(d, where + PCI_RCEC_RCIEP_BMAP); | |
650 | printf("\t\tRCiEPBitmap: "); | |
651 | if (bmap) | |
652 | { | |
653 | int prevmatched=0; | |
654 | int adjcount=0; | |
655 | int prevdev=0; | |
656 | printf("RCiEP at Device(s):"); | |
657 | for (int dev=0; dev < 32; dev++) | |
658 | { | |
659 | if (BITS(bmap, dev, 1)) | |
660 | { | |
661 | if (!adjcount) | |
662 | printf("%s %u", (prevmatched) ? "," : "", dev); | |
663 | adjcount++; | |
664 | prevdev=dev; | |
665 | prevmatched=1; | |
666 | } | |
667 | else | |
668 | { | |
669 | if (adjcount > 1) | |
670 | printf("-%u", prevdev); | |
671 | adjcount=0; | |
672 | } | |
673 | } | |
674 | } | |
675 | else | |
676 | printf("%s", (verbose > 2) ? "00000000 [none]" : "[none]"); | |
677 | printf("\n"); | |
678 | ||
679 | if (cap_ver < PCI_RCEC_BUSN_REG_VER) | |
680 | return; | |
681 | ||
682 | u32 busn = get_conf_long(d, where + PCI_RCEC_BUSN_REG); | |
683 | u8 lastbusn = BITS(busn, 16, 8); | |
684 | u8 nextbusn = BITS(busn, 8, 8); | |
685 | ||
686 | if ((lastbusn == 0x00) && (nextbusn == 0xff)) | |
687 | printf("\t\tAssociatedBusNumbers: %s\n", (verbose > 2) ? "ff-00 [none]" : "[none]"); | |
688 | else | |
689 | printf("\t\tAssociatedBusNumbers: %02x-%02x\n", nextbusn, lastbusn ); | |
690 | } | |
691 | ||
52097446 BW |
692 | static void |
693 | cxl_range(u64 base, u64 size, int n) | |
694 | { | |
695 | u32 interleave[] = { 0, 256, 4096, 512, 1024, 2048, 8192, 16384 }; | |
696 | const char *type[] = { "Volatile", "Non-volatile", "CDAT" }; | |
697 | const char *class[] = { "DRAM", "Storage", "CDAT" }; | |
698 | u16 w; | |
699 | ||
700 | w = (u16) size; | |
701 | ||
702 | size &= ~0x0fffffffULL; | |
703 | ||
704 | printf("\t\tRange%d: %016"PCI_U64_FMT_X"-%016"PCI_U64_FMT_X"\n", n, base, base + size - 1); | |
705 | printf("\t\t\tValid%c Active%c Type=%s Class=%s interleave=%d timeout=%ds\n", | |
706 | FLAG(w, PCI_CXL_RANGE_VALID), FLAG(w, PCI_CXL_RANGE_ACTIVE), | |
707 | type[PCI_CXL_RANGE_TYPE(w)], class[PCI_CXL_RANGE_CLASS(w)], | |
708 | interleave[PCI_CXL_RANGE_INTERLEAVE(w)], | |
709 | 1 << (PCI_CXL_RANGE_TIMEOUT(w) * 2)); | |
710 | } | |
711 | ||
bd853ef8 | 712 | static void |
2849db67 | 713 | dvsec_cxl_device(struct device *d, int rev, int where, int len) |
bd853ef8 | 714 | { |
2849db67 | 715 | u32 cache_size, cache_unit_size; |
52097446 | 716 | u64 range_base, range_size; |
ccf5ff41 | 717 | u16 w; |
bd853ef8 | 718 | |
2849db67 MM |
719 | if (len < PCI_CXL_DEV_LEN) |
720 | return; | |
721 | ||
0d4491cb BW |
722 | /* Legacy 1.1 revs aren't handled */ |
723 | if (rev < 1) | |
bd853ef8 SK |
724 | return; |
725 | ||
4c2b4b1b | 726 | w = get_conf_word(d, where + PCI_CXL_DEV_CAP); |
bd853ef8 | 727 | printf("\t\tCXLCap:\tCache%c IO%c Mem%c Mem HW Init%c HDMCount %d Viral%c\n", |
4c2b4b1b BW |
728 | FLAG(w, PCI_CXL_DEV_CAP_CACHE), FLAG(w, PCI_CXL_DEV_CAP_IO), FLAG(w, PCI_CXL_DEV_CAP_MEM), |
729 | FLAG(w, PCI_CXL_DEV_CAP_MEM_HWINIT), PCI_CXL_DEV_CAP_HDM_CNT(w), FLAG(w, PCI_CXL_DEV_CAP_VIRAL)); | |
bd853ef8 | 730 | |
4c2b4b1b | 731 | w = get_conf_word(d, where + PCI_CXL_DEV_CTRL); |
bd853ef8 | 732 | printf("\t\tCXLCtl:\tCache%c IO%c Mem%c Cache SF Cov %d Cache SF Gran %d Cache Clean%c Viral%c\n", |
4c2b4b1b BW |
733 | FLAG(w, PCI_CXL_DEV_CTRL_CACHE), FLAG(w, PCI_CXL_DEV_CTRL_IO), FLAG(w, PCI_CXL_DEV_CTRL_MEM), |
734 | PCI_CXL_DEV_CTRL_CACHE_SF_COV(w), PCI_CXL_DEV_CTRL_CACHE_SF_GRAN(w), FLAG(w, PCI_CXL_DEV_CTRL_CACHE_CLN), | |
735 | FLAG(w, PCI_CXL_DEV_CTRL_VIRAL)); | |
bd853ef8 | 736 | |
4c2b4b1b BW |
737 | w = get_conf_word(d, where + PCI_CXL_DEV_STATUS); |
738 | printf("\t\tCXLSta:\tViral%c\n", FLAG(w, PCI_CXL_DEV_STATUS_VIRAL)); | |
52097446 BW |
739 | |
740 | w = get_conf_word(d, where + PCI_CXL_DEV_STATUS2); | |
741 | printf("\t\tCXLSta2:\tResetComplete%c ResetError%c PMComplete%c\n", | |
742 | FLAG(w, PCI_CXL_DEV_STATUS_RC), FLAG(w,PCI_CXL_DEV_STATUS_RE), FLAG(w, PCI_CXL_DEV_STATUS_PMC)); | |
743 | ||
744 | w = get_conf_word(d, where + PCI_CXL_DEV_CAP2); | |
745 | cache_unit_size = BITS(w, 0, 4); | |
746 | cache_size = BITS(w, 8, 8); | |
747 | switch (cache_unit_size) | |
748 | { | |
749 | case PCI_CXL_DEV_CAP2_CACHE_1M: | |
750 | printf("\t\tCache Size: %08x\n", cache_size * (1<<20)); | |
751 | break; | |
752 | case PCI_CXL_DEV_CAP2_CACHE_64K: | |
753 | printf("\t\tCache Size: %08x\n", cache_size * (64<<10)); | |
754 | break; | |
755 | case PCI_CXL_DEV_CAP2_CACHE_UNK: | |
756 | printf("\t\tCache Size Not Reported\n"); | |
757 | break; | |
758 | default: | |
759 | printf("\t\tCache Size: %d of unknown unit size (%d)\n", cache_size, cache_unit_size); | |
760 | break; | |
761 | } | |
762 | ||
2849db67 MM |
763 | range_size = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE1_SIZE_HI) << 32; |
764 | range_size |= get_conf_long(d, where + PCI_CXL_DEV_RANGE1_SIZE_LO); | |
765 | range_base = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE1_BASE_HI) << 32; | |
766 | range_base |= get_conf_long(d, where + PCI_CXL_DEV_RANGE1_BASE_LO); | |
52097446 BW |
767 | cxl_range(range_base, range_size, 1); |
768 | ||
2849db67 MM |
769 | range_size = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE2_SIZE_HI) << 32; |
770 | range_size |= get_conf_long(d, where + PCI_CXL_DEV_RANGE2_SIZE_LO); | |
771 | range_base = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE2_BASE_HI) << 32; | |
772 | range_base |= get_conf_long(d, where + PCI_CXL_DEV_RANGE2_BASE_LO); | |
52097446 | 773 | cxl_range(range_base, range_size, 2); |
bd853ef8 SK |
774 | } |
775 | ||
c8b83c6c | 776 | static void |
2849db67 | 777 | dvsec_cxl_port(struct device *d, int where, int len) |
c8b83c6c BW |
778 | { |
779 | u16 w, m1, m2; | |
780 | u8 b1, b2; | |
781 | ||
2849db67 MM |
782 | if (len < PCI_CXL_PORT_EXT_LEN) |
783 | return; | |
784 | ||
c8b83c6c BW |
785 | w = get_conf_word(d, where + PCI_CXL_PORT_EXT_STATUS); |
786 | printf("\t\tCXLPortSta:\tPMComplete%c\n", FLAG(w, PCI_CXL_PORT_EXT_STATUS)); | |
787 | ||
788 | w = get_conf_word(d, where + PCI_CXL_PORT_CTRL); | |
789 | printf("\t\tCXLPortCtl:\tUnmaskSBR%c UnmaskLinkDisable%c AltMem%c AltBME%c ViralEnable%c\n", | |
790 | FLAG(w, PCI_CXL_PORT_UNMASK_SBR), FLAG(w, PCI_CXL_PORT_UNMASK_LINK), | |
791 | FLAG(w, PCI_CXL_PORT_ALT_MEMORY), FLAG(w, PCI_CXL_PORT_ALT_BME), | |
792 | FLAG(w, PCI_CXL_PORT_VIRAL_EN)); | |
793 | ||
794 | b1 = get_conf_byte(d, where + PCI_CXL_PORT_ALT_BUS_BASE); | |
795 | b2 = get_conf_byte(d, where + PCI_CXL_PORT_ALT_BUS_LIMIT); | |
796 | printf("\t\tAlternateBus:\t%02x-%02x\n", b1, b2); | |
797 | m1 = get_conf_word(d, where + PCI_CXL_PORT_ALT_MEM_BASE); | |
798 | m2 = get_conf_word(d, where + PCI_CXL_PORT_ALT_MEM_LIMIT); | |
799 | printf("\t\tAlternateBus:\t%04x-%04x\n", m1, m2); | |
800 | } | |
801 | ||
2849db67 MM |
802 | static void |
803 | dvsec_cxl_register_locator(struct device *d, int where, int len) | |
0dfa1050 | 804 | { |
2849db67 MM |
805 | static const char * const id_names[] = { |
806 | "empty", | |
807 | "component registers", | |
808 | "BAR virtualization", | |
809 | "CXL device registers", | |
810 | "CPMU registers", | |
811 | }; | |
812 | ||
813 | for (int i=0; ; i++) | |
814 | { | |
55704534 JH |
815 | int pos = where + PCI_CXL_RL_BLOCK1_LO + 8*i; |
816 | if (pos + 7 >= where + len) | |
2849db67 | 817 | break; |
0dfa1050 | 818 | |
2849db67 MM |
819 | u32 lo = get_conf_long(d, pos); |
820 | u32 hi = get_conf_long(d, pos + 4); | |
0dfa1050 | 821 | |
2849db67 MM |
822 | unsigned int bir = BITS(lo, 0, 3); |
823 | unsigned int block_id = BITS(lo, 8, 8); | |
824 | u64 base = (BITS(lo, 16, 16) << 16) | ((u64) hi << 32); | |
0dfa1050 | 825 | |
2849db67 MM |
826 | if (!block_id) |
827 | continue; | |
0dfa1050 | 828 | |
2849db67 MM |
829 | const char *id_name; |
830 | if (block_id < sizeof(id_names) / sizeof(*id_names)) | |
831 | id_name = id_names[block_id]; | |
832 | else if (block_id == 0xff) | |
833 | id_name = "vendor-specific"; | |
834 | else | |
835 | id_name = "<?>"; | |
0dfa1050 | 836 | |
55704534 | 837 | printf("\t\tBlock%d: BIR: bar%d, ID: %s, offset: %016" PCI_U64_FMT_X "\n", i + 1, bir, id_name, base); |
2849db67 | 838 | } |
0dfa1050 BW |
839 | } |
840 | ||
d462e89c JH |
841 | static void |
842 | dvsec_cxl_gpf_device(struct device *d, int where) | |
843 | { | |
844 | u32 l; | |
845 | u16 w, duration; | |
846 | u8 time_base, time_scale; | |
847 | ||
848 | w = get_conf_word(d, where + PCI_CXL_GPF_DEV_PHASE2_DUR); | |
849 | time_base = BITS(w, 0, 4); | |
850 | time_scale = BITS(w, 8, 4); | |
851 | ||
852 | switch (time_scale) | |
853 | { | |
854 | case PCI_CXL_GPF_DEV_100US: | |
855 | case PCI_CXL_GPF_DEV_100MS: | |
856 | duration = time_base * 100; | |
857 | break; | |
858 | case PCI_CXL_GPF_DEV_10US: | |
859 | case PCI_CXL_GPF_DEV_10MS: | |
860 | case PCI_CXL_GPF_DEV_10S: | |
861 | duration = time_base * 10; | |
862 | break; | |
863 | case PCI_CXL_GPF_DEV_1US: | |
864 | case PCI_CXL_GPF_DEV_1MS: | |
865 | case PCI_CXL_GPF_DEV_1S: | |
866 | duration = time_base; | |
867 | break; | |
868 | default: | |
869 | /* Reserved */ | |
870 | printf("\t\tReserved time scale encoding %x\n", time_scale); | |
871 | duration = time_base; | |
872 | } | |
873 | ||
874 | printf("\t\tGPF Phase 2 Duration: %u%s\n", duration, | |
875 | (time_scale < PCI_CXL_GPF_DEV_1MS) ? "us": | |
876 | (time_scale < PCI_CXL_GPF_DEV_1S) ? "ms" : | |
877 | (time_scale == PCI_CXL_GPF_DEV_1S) ? "s" : "<?>"); | |
878 | ||
879 | l = get_conf_long(d, where + PCI_CXL_GPF_DEV_PHASE2_POW); | |
880 | printf("\t\tGPF Phase 2 Power: %umW\n", (unsigned int)l); | |
881 | } | |
882 | ||
5c75f737 JH |
883 | static void |
884 | dvsec_cxl_gpf_port(struct device *d, int where) | |
885 | { | |
886 | u16 w, timeout; | |
887 | u8 time_base, time_scale; | |
888 | ||
889 | w = get_conf_word(d, where + PCI_CXL_GPF_PORT_PHASE1_CTRL); | |
890 | time_base = BITS(w, 0, 4); | |
891 | time_scale = BITS(w, 8, 4); | |
892 | ||
893 | switch (time_scale) | |
894 | { | |
895 | case PCI_CXL_GPF_PORT_100US: | |
896 | case PCI_CXL_GPF_PORT_100MS: | |
897 | timeout = time_base * 100; | |
898 | break; | |
899 | case PCI_CXL_GPF_PORT_10US: | |
900 | case PCI_CXL_GPF_PORT_10MS: | |
901 | case PCI_CXL_GPF_PORT_10S: | |
902 | timeout = time_base * 10; | |
903 | break; | |
904 | case PCI_CXL_GPF_PORT_1US: | |
905 | case PCI_CXL_GPF_PORT_1MS: | |
906 | case PCI_CXL_GPF_PORT_1S: | |
907 | timeout = time_base; | |
908 | break; | |
909 | default: | |
910 | /* Reserved */ | |
911 | printf("\t\tReserved time scale encoding %x\n", time_scale); | |
912 | timeout = time_base; | |
913 | } | |
914 | ||
915 | printf("\t\tGPF Phase 1 Timeout: %d%s\n", timeout, | |
916 | (time_scale < PCI_CXL_GPF_PORT_1MS) ? "us": | |
917 | (time_scale < PCI_CXL_GPF_PORT_1S) ? "ms" : | |
918 | (time_scale == PCI_CXL_GPF_PORT_1S) ? "s" : "<?>"); | |
919 | ||
920 | w = get_conf_word(d, where + PCI_CXL_GPF_PORT_PHASE2_CTRL); | |
921 | time_base = BITS(w, 0, 4); | |
922 | time_scale = BITS(w, 8, 4); | |
923 | ||
924 | switch (time_scale) | |
925 | { | |
926 | case PCI_CXL_GPF_PORT_100US: | |
927 | case PCI_CXL_GPF_PORT_100MS: | |
928 | timeout = time_base * 100; | |
929 | break; | |
930 | case PCI_CXL_GPF_PORT_10US: | |
931 | case PCI_CXL_GPF_PORT_10MS: | |
932 | case PCI_CXL_GPF_PORT_10S: | |
933 | timeout = time_base * 10; | |
934 | break; | |
935 | case PCI_CXL_GPF_PORT_1US: | |
936 | case PCI_CXL_GPF_PORT_1MS: | |
937 | case PCI_CXL_GPF_PORT_1S: | |
938 | timeout = time_base; | |
939 | break; | |
940 | default: | |
941 | /* Reserved */ | |
942 | printf("\t\tReserved time scale encoding %x\n", time_scale); | |
943 | timeout = time_base; | |
944 | } | |
945 | ||
946 | printf("\t\tGPF Phase 2 Timeout: %d%s\n", timeout, | |
947 | (time_scale < PCI_CXL_GPF_PORT_1MS) ? "us": | |
948 | (time_scale < PCI_CXL_GPF_PORT_1S) ? "ms" : | |
949 | (time_scale == PCI_CXL_GPF_PORT_1S) ? "s" : "<?>"); | |
950 | } | |
951 | ||
9e567a4e JH |
952 | static void |
953 | dvsec_cxl_flex_bus(struct device *d, int where, int rev) | |
954 | { | |
955 | u16 w; | |
956 | u32 l, data; | |
957 | ||
958 | if (rev < 1) | |
959 | { | |
960 | printf("\t\tRevision %d not supported\n", rev); | |
961 | return; | |
962 | } | |
963 | ||
964 | w = get_conf_word(d, where + PCI_CXL_FB_PORT_CAP); | |
965 | printf("\t\tFBCap:\tCache%c IO%c Mem%c 68BFlit%c MltLogDev%c", | |
966 | FLAG(w, PCI_CXL_FB_CAP_CACHE), FLAG(w, PCI_CXL_FB_CAP_IO), | |
967 | FLAG(w, PCI_CXL_FB_CAP_MEM), FLAG(w, PCI_CXL_FB_CAP_68B_FLIT), | |
968 | FLAG(w, PCI_CXL_FB_CAP_MULT_LOG_DEV)); | |
969 | ||
970 | if (rev > 1) | |
971 | printf(" 256BFlit%c PBRFlit%c", | |
972 | FLAG(w, PCI_CXL_FB_CAP_256B_FLIT), FLAG(w, PCI_CXL_FB_CAP_PBR_FLIT)); | |
973 | ||
974 | w = get_conf_word(d, where + PCI_CXL_FB_PORT_CTRL); | |
975 | printf("\n\t\tFBCtl:\tCache%c IO%c Mem%c SynHdrByp%c DrftBuf%c 68BFlit%c MltLogDev%c RCD%c Retimer1%c Retimer2%c", | |
976 | FLAG(w, PCI_CXL_FB_CTRL_CACHE), FLAG(w, PCI_CXL_FB_CTRL_IO), | |
977 | FLAG(w, PCI_CXL_FB_CTRL_MEM), FLAG(w, PCI_CXL_FB_CTRL_SYNC_HDR_BYP), | |
978 | FLAG(w, PCI_CXL_FB_CTRL_DRFT_BUF), FLAG(w, PCI_CXL_FB_CTRL_68B_FLIT), | |
979 | FLAG(w, PCI_CXL_FB_CTRL_MULT_LOG_DEV), FLAG(w, PCI_CXL_FB_CTRL_RCD), | |
980 | FLAG(w, PCI_CXL_FB_CTRL_RETIMER1), FLAG(w, PCI_CXL_FB_CTRL_RETIMER2)); | |
981 | ||
982 | if (rev > 1) | |
983 | printf(" 256BFlit%c PBRFlit%c", | |
984 | FLAG(w, PCI_CXL_FB_CTRL_256B_FLIT), FLAG(w, PCI_CXL_FB_CTRL_PBR_FLIT)); | |
985 | ||
986 | w = get_conf_word(d, where + PCI_CXL_FB_PORT_STATUS); | |
987 | printf("\n\t\tFBSta:\tCache%c IO%c Mem%c SynHdrByp%c DrftBuf%c 68BFlit%c MltLogDev%c", | |
988 | FLAG(w, PCI_CXL_FB_STAT_CACHE), FLAG(w, PCI_CXL_FB_STAT_IO), | |
989 | FLAG(w, PCI_CXL_FB_STAT_MEM), FLAG(w, PCI_CXL_FB_STAT_SYNC_HDR_BYP), | |
990 | FLAG(w, PCI_CXL_FB_STAT_DRFT_BUF), FLAG(w, PCI_CXL_FB_STAT_68B_FLIT), | |
991 | FLAG(w, PCI_CXL_FB_STAT_MULT_LOG_DEV)); | |
992 | ||
993 | if (rev > 1) | |
994 | printf(" 256BFlit%c PBRFlit%c", | |
995 | FLAG(w, PCI_CXL_FB_STAT_256B_FLIT), FLAG(w, PCI_CXL_FB_STAT_PBR_FLIT)); | |
996 | ||
997 | l = get_conf_long(d, where + PCI_CXL_FB_MOD_TS_DATA); | |
998 | data = BITS(l, 0, 24); | |
999 | printf("\n\t\tFBModTS:\tReceived FB Data: %06x\n", (unsigned int)data); | |
1000 | ||
1001 | if (rev > 1) | |
1002 | { | |
1003 | u8 nop; | |
1004 | ||
1005 | l = get_conf_long(d, where + PCI_CXL_FB_PORT_CAP2); | |
1006 | printf("\t\tFBCap2:\tNOPHint%c\n", FLAG(l, PCI_CXL_FB_CAP2_NOP_HINT)); | |
1007 | ||
1008 | l = get_conf_long(d, where + PCI_CXL_FB_PORT_CTRL2); | |
1009 | printf("\t\tFBCtl2:\tNOPHint%c\n", FLAG(l, PCI_CXL_FB_CTRL2_NOP_HINT)); | |
1010 | ||
1011 | l = get_conf_long(d, where + PCI_CXL_FB_PORT_STATUS2); | |
1012 | nop = BITS(l, 0, 2); | |
1013 | printf("\t\tFBSta2:\tNOPHintInfo: %x\n", nop); | |
1014 | } | |
1015 | } | |
1016 | ||
45824262 JH |
1017 | static void |
1018 | dvsec_cxl_mld(struct device *d, int where) | |
1019 | { | |
1020 | u16 w; | |
1021 | ||
1022 | w = get_conf_word(d, where + PCI_CXL_MLD_NUM_LD); | |
1023 | ||
1024 | /* Encodings greater than 16 are reserved */ | |
1025 | if (w && w <= PCI_CXL_MLD_MAX_LD) | |
1026 | printf("\t\tNumLogDevs: %d\n", w); | |
1027 | } | |
1028 | ||
ec4cd47b JH |
1029 | static void |
1030 | dvsec_cxl_function_map(struct device *d, int where) | |
1031 | { | |
1032 | ||
1033 | printf("\t\tFuncMap 0: %08x\n", | |
1034 | (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_0))); | |
1035 | ||
1036 | printf("\t\tFuncMap 1: %08x\n", | |
1037 | (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_1))); | |
1038 | ||
1039 | printf("\t\tFuncMap 2: %08x\n", | |
1040 | (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_2))); | |
1041 | ||
1042 | printf("\t\tFuncMap 3: %08x\n", | |
1043 | (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_3))); | |
1044 | ||
1045 | printf("\t\tFuncMap 4: %08x\n", | |
1046 | (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_4))); | |
1047 | ||
1048 | printf("\t\tFuncMap 5: %08x\n", | |
1049 | (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_5))); | |
1050 | ||
1051 | printf("\t\tFuncMap 6: %08x\n", | |
1052 | (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_6))); | |
1053 | ||
1054 | printf("\t\tFuncMap 7: %08x\n", | |
1055 | (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_7))); | |
1056 | } | |
1057 | ||
0d4491cb | 1058 | static void |
2849db67 | 1059 | cap_dvsec_cxl(struct device *d, int id, int rev, int where, int len) |
0d4491cb | 1060 | { |
0d4491cb BW |
1061 | printf(": CXL\n"); |
1062 | if (verbose < 2) | |
1063 | return; | |
1064 | ||
2849db67 MM |
1065 | if (!config_fetch(d, where, len)) |
1066 | return; | |
0d4491cb | 1067 | |
2849db67 MM |
1068 | switch (id) |
1069 | { | |
c8b83c6c | 1070 | case 0: |
2849db67 | 1071 | dvsec_cxl_device(d, rev, where, len); |
0dfa1050 | 1072 | break; |
fe0df5d3 | 1073 | case 2: |
ec4cd47b | 1074 | dvsec_cxl_function_map(d, where); |
fe0df5d3 | 1075 | break; |
2849db67 MM |
1076 | case 3: |
1077 | dvsec_cxl_port(d, where, len); | |
1078 | break; | |
fe0df5d3 | 1079 | case 4: |
5c75f737 | 1080 | dvsec_cxl_gpf_port(d, where); |
fe0df5d3 BW |
1081 | break; |
1082 | case 5: | |
d462e89c | 1083 | dvsec_cxl_gpf_device(d, where); |
fe0df5d3 BW |
1084 | break; |
1085 | case 7: | |
9e567a4e | 1086 | dvsec_cxl_flex_bus(d, where, rev); |
fe0df5d3 | 1087 | break; |
2849db67 MM |
1088 | case 8: |
1089 | dvsec_cxl_register_locator(d, where, len); | |
1090 | break; | |
fe0df5d3 | 1091 | case 9: |
45824262 | 1092 | dvsec_cxl_mld(d, where); |
fe0df5d3 | 1093 | break; |
c8b83c6c | 1094 | default: |
2849db67 MM |
1095 | printf("\t\tUnknown ID %04x\n", id); |
1096 | } | |
0d4491cb BW |
1097 | } |
1098 | ||
5f1d1265 SK |
1099 | static void |
1100 | cap_dvsec(struct device *d, int where) | |
1101 | { | |
71aeac63 | 1102 | printf("Designated Vendor-Specific: "); |
5f1d1265 SK |
1103 | if (!config_fetch(d, where + PCI_DVSEC_HEADER1, 8)) |
1104 | { | |
1105 | printf("<unreadable>\n"); | |
1106 | return; | |
1107 | } | |
1108 | ||
71aeac63 MM |
1109 | u32 hdr = get_conf_long(d, where + PCI_DVSEC_HEADER1); |
1110 | u16 vendor = BITS(hdr, 0, 16); | |
1111 | byte rev = BITS(hdr, 16, 4); | |
1112 | u16 len = BITS(hdr, 20, 12); | |
5f1d1265 | 1113 | |
71aeac63 MM |
1114 | u16 id = get_conf_long(d, where + PCI_DVSEC_HEADER2); |
1115 | ||
1116 | printf("Vendor=%04x ID=%04x Rev=%d Len=%d", vendor, id, rev, len); | |
6c138204 | 1117 | if (vendor == PCI_DVSEC_VENDOR_ID_CXL && len >= 16) |
2849db67 | 1118 | cap_dvsec_cxl(d, id, rev, where, len); |
71aeac63 MM |
1119 | else |
1120 | printf(" <?>\n"); | |
5f1d1265 SK |
1121 | } |
1122 | ||
78ca9582 MM |
1123 | static void |
1124 | cap_evendor(struct device *d, int where) | |
1125 | { | |
1126 | u32 hdr; | |
1127 | ||
1128 | printf("Vendor Specific Information: "); | |
1129 | if (!config_fetch(d, where + PCI_EVNDR_HEADER, 4)) | |
1130 | { | |
1131 | printf("<unreadable>\n"); | |
1132 | return; | |
1133 | } | |
1134 | ||
1135 | hdr = get_conf_long(d, where + PCI_EVNDR_HEADER); | |
1136 | printf("ID=%04x Rev=%d Len=%03x <?>\n", | |
1137 | BITS(hdr, 0, 16), | |
1138 | BITS(hdr, 16, 4), | |
1139 | BITS(hdr, 20, 12)); | |
1140 | } | |
1141 | ||
fb17077d | 1142 | static int l1pm_calc_pwron(int scale, int value) |
8efbe075 RJ |
1143 | { |
1144 | switch (scale) | |
1145 | { | |
1146 | case 0: | |
1147 | return 2 * value; | |
1148 | case 1: | |
1149 | return 10 * value; | |
1150 | case 2: | |
1151 | return 100 * value; | |
1152 | } | |
1153 | return -1; | |
1154 | } | |
1155 | ||
214c9a95 DB |
1156 | static void |
1157 | cap_l1pm(struct device *d, int where) | |
1158 | { | |
8efbe075 RJ |
1159 | u32 l1_cap, val, scale; |
1160 | int time; | |
214c9a95 DB |
1161 | |
1162 | printf("L1 PM Substates\n"); | |
1163 | ||
1164 | if (verbose < 2) | |
1165 | return; | |
1166 | ||
8efbe075 | 1167 | if (!config_fetch(d, where + PCI_L1PM_SUBSTAT_CAP, 12)) |
214c9a95 DB |
1168 | { |
1169 | printf("\t\t<unreadable>\n"); | |
1170 | return; | |
1171 | } | |
1172 | ||
8efbe075 | 1173 | l1_cap = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CAP); |
214c9a95 | 1174 | printf("\t\tL1SubCap: "); |
e495466c | 1175 | printf("PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c L1_PM_Substates%c\n", |
8efbe075 RJ |
1176 | FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_PM_L12), |
1177 | FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_PM_L11), | |
1178 | FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_ASPM_L12), | |
1179 | FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_ASPM_L11), | |
1180 | FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_L1PM_SUPP)); | |
1181 | ||
fb17077d | 1182 | if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12) |
214c9a95 | 1183 | { |
fb17077d | 1184 | printf("\t\t\t PortCommonModeRestoreTime=%dus ", BITS(l1_cap, 8, 8)); |
8efbe075 RJ |
1185 | time = l1pm_calc_pwron(BITS(l1_cap, 16, 2), BITS(l1_cap, 19, 5)); |
1186 | if (time != -1) | |
1187 | printf("PortTPowerOnTime=%dus\n", time); | |
1188 | else | |
1189 | printf("PortTPowerOnTime=<error>\n"); | |
1190 | } | |
214c9a95 | 1191 | |
8efbe075 | 1192 | val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL1); |
fb17077d | 1193 | printf("\t\tL1SubCtl1: PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c\n", |
8efbe075 RJ |
1194 | FLAG(val, PCI_L1PM_SUBSTAT_CTL1_PM_L12), |
1195 | FLAG(val, PCI_L1PM_SUBSTAT_CTL1_PM_L11), | |
1196 | FLAG(val, PCI_L1PM_SUBSTAT_CTL1_ASPM_L12), | |
1197 | FLAG(val, PCI_L1PM_SUBSTAT_CTL1_ASPM_L11)); | |
1198 | ||
fb17077d | 1199 | if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12) |
8efbe075 | 1200 | { |
6469d596 VL |
1201 | printf("\t\t\t T_CommonMode=%dus", BITS(val, 8, 8)); |
1202 | ||
1203 | if (l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12) | |
1204 | { | |
1205 | scale = BITS(val, 29, 3); | |
1206 | if (scale > 5) | |
1207 | printf(" LTR1.2_Threshold=<error>"); | |
1208 | else | |
c3d1d465 | 1209 | printf(" LTR1.2_Threshold=%" PCI_U64_FMT_U "ns", BITS(val, 16, 10) * (u64) cap_ltr_scale(scale)); |
6469d596 VL |
1210 | } |
1211 | printf("\n"); | |
8efbe075 RJ |
1212 | } |
1213 | ||
1214 | val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL2); | |
fb17077d MM |
1215 | printf("\t\tL1SubCtl2:"); |
1216 | if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12) | |
8efbe075 RJ |
1217 | { |
1218 | time = l1pm_calc_pwron(BITS(val, 0, 2), BITS(val, 3, 5)); | |
1219 | if (time != -1) | |
fb17077d | 1220 | printf(" T_PwrOn=%dus", time); |
8efbe075 | 1221 | else |
fb17077d | 1222 | printf(" T_PwrOn=<error>"); |
214c9a95 | 1223 | } |
fb17077d | 1224 | printf("\n"); |
214c9a95 DB |
1225 | } |
1226 | ||
415a9c18 YJ |
1227 | static void |
1228 | cap_ptm(struct device *d, int where) | |
1229 | { | |
1230 | u32 buff; | |
1231 | u16 clock; | |
1232 | ||
1233 | printf("Precision Time Measurement\n"); | |
1234 | ||
1235 | if (verbose < 2) | |
1236 | return; | |
1237 | ||
1238 | if (!config_fetch(d, where + 4, 8)) | |
1239 | { | |
1240 | printf("\t\t<unreadable>\n"); | |
1241 | return; | |
1242 | } | |
1243 | ||
1244 | buff = get_conf_long(d, where + 4); | |
1245 | printf("\t\tPTMCap: "); | |
1246 | printf("Requester:%c Responder:%c Root:%c\n", | |
1247 | FLAG(buff, 0x1), | |
1248 | FLAG(buff, 0x2), | |
1249 | FLAG(buff, 0x4)); | |
1250 | ||
1251 | clock = BITS(buff, 8, 8); | |
1252 | printf("\t\tPTMClockGranularity: "); | |
1253 | switch (clock) | |
1254 | { | |
1255 | case 0x00: | |
1256 | printf("Unimplemented\n"); | |
1257 | break; | |
1258 | case 0xff: | |
1259 | printf("Greater than 254ns\n"); | |
1260 | break; | |
1261 | default: | |
1262 | printf("%huns\n", clock); | |
1263 | } | |
1264 | ||
1265 | buff = get_conf_long(d, where + 8); | |
1266 | printf("\t\tPTMControl: "); | |
1267 | printf("Enabled:%c RootSelected:%c\n", | |
1268 | FLAG(buff, 0x1), | |
1269 | FLAG(buff, 0x2)); | |
1270 | ||
1271 | clock = BITS(buff, 8, 8); | |
1272 | printf("\t\tPTMEffectiveGranularity: "); | |
1273 | switch (clock) | |
1274 | { | |
1275 | case 0x00: | |
1276 | printf("Unknown\n"); | |
1277 | break; | |
1278 | case 0xff: | |
1279 | printf("Greater than 254ns\n"); | |
1280 | break; | |
1281 | default: | |
1282 | printf("%huns\n", clock); | |
1283 | } | |
1284 | } | |
1285 | ||
44c6c7fc MM |
1286 | static void |
1287 | print_rebar_range_size(int ld2_size) | |
1288 | { | |
1289 | // This function prints the input as a power-of-2 size value | |
1290 | // It is biased with 1MB = 0, ... | |
1291 | // Maximum resizable BAR value supported is 2^63 bytes = 43 | |
1292 | // for the extended resizable BAR capability definition | |
1293 | // (otherwise it would stop at 2^28) | |
1294 | ||
1295 | if (ld2_size >= 0 && ld2_size < 10) | |
1296 | printf(" %dMB", (1 << ld2_size)); | |
1297 | else if (ld2_size >= 10 && ld2_size < 20) | |
1298 | printf(" %dGB", (1 << (ld2_size-10))); | |
1299 | else if (ld2_size >= 20 && ld2_size < 30) | |
1300 | printf(" %dTB", (1 << (ld2_size-20))); | |
1301 | else if (ld2_size >= 30 && ld2_size < 40) | |
1302 | printf(" %dPB", (1 << (ld2_size-30))); | |
1303 | else if (ld2_size >= 40 && ld2_size < 44) | |
1304 | printf(" %dEB", (1 << (ld2_size-40))); | |
1305 | else | |
1306 | printf(" <unknown>"); | |
1307 | } | |
1308 | ||
1309 | static void | |
1310 | cap_rebar(struct device *d, int where, int virtual) | |
1311 | { | |
1312 | u32 sizes_buffer, control_buffer, ext_sizes, current_size; | |
d10c2aa1 MM |
1313 | u16 bar_index, barcount, i; |
1314 | // If the structure exists, at least one bar is defined | |
44c6c7fc MM |
1315 | u16 num_bars = 1; |
1316 | ||
1317 | printf("%s Resizable BAR\n", (virtual) ? "Virtual" : "Physical"); | |
1318 | ||
d10c2aa1 | 1319 | if (verbose < 2) |
44c6c7fc MM |
1320 | return; |
1321 | ||
1322 | // Go through all defined BAR definitions of the caps, at minimum 1 | |
1323 | // (loop also terminates if num_bars read from caps is > 6) | |
1324 | for (barcount = 0; barcount < num_bars; barcount++) | |
1325 | { | |
1326 | where += 4; | |
1327 | ||
1328 | // Get the next BAR configuration | |
1329 | if (!config_fetch(d, where, 8)) | |
1330 | { | |
1331 | printf("\t\t<unreadable>\n"); | |
1332 | return; | |
1333 | } | |
1334 | ||
1335 | sizes_buffer = get_conf_long(d, where) >> 4; | |
44c6c7fc | 1336 | where += 4; |
44c6c7fc MM |
1337 | control_buffer = get_conf_long(d, where); |
1338 | ||
d10c2aa1 MM |
1339 | bar_index = BITS(control_buffer, 0, 3); |
1340 | current_size = BITS(control_buffer, 8, 6); | |
1341 | ext_sizes = BITS(control_buffer, 16, 16); | |
44c6c7fc MM |
1342 | |
1343 | if (barcount == 0) | |
1344 | { | |
1345 | // Only index 0 controlreg has the num_bar count definition | |
d10c2aa1 MM |
1346 | num_bars = BITS(control_buffer, 5, 3); |
1347 | if (num_bars < 1 || num_bars > 6) | |
1348 | { | |
1349 | printf("\t\t<error in resizable BAR: num_bars=%d is out of specification>\n", num_bars); | |
1350 | break; | |
1351 | } | |
44c6c7fc MM |
1352 | } |
1353 | ||
1354 | // Resizable BAR list entry have an arbitrary index and current size | |
d10c2aa1 | 1355 | printf("\t\tBAR %d: current size:", bar_index); |
44c6c7fc MM |
1356 | print_rebar_range_size(current_size); |
1357 | ||
d10c2aa1 MM |
1358 | if (sizes_buffer || ext_sizes) |
1359 | { | |
1360 | printf(", supported:"); | |
44c6c7fc | 1361 | |
d10c2aa1 MM |
1362 | for (i=0; i<28; i++) |
1363 | if (sizes_buffer & (1U << i)) | |
1364 | print_rebar_range_size(i); | |
44c6c7fc | 1365 | |
d10c2aa1 MM |
1366 | for (i=0; i<16; i++) |
1367 | if (ext_sizes & (1U << i)) | |
1368 | print_rebar_range_size(i + 28); | |
1369 | } | |
44c6c7fc | 1370 | |
44c6c7fc MM |
1371 | printf("\n"); |
1372 | } | |
1373 | } | |
1374 | ||
60be9345 JC |
1375 | static void |
1376 | cap_doe(struct device *d, int where) | |
1377 | { | |
1378 | u32 l; | |
1379 | ||
1380 | printf("Data Object Exchange\n"); | |
1381 | ||
1382 | if (verbose < 2) | |
1383 | return; | |
1384 | ||
1385 | if (!config_fetch(d, where + PCI_DOE_CAP, 0x14)) | |
1386 | { | |
1387 | printf("\t\t<unreadable>\n"); | |
1388 | return; | |
1389 | } | |
1390 | ||
1391 | l = get_conf_long(d, where + PCI_DOE_CAP); | |
1392 | printf("\t\tDOECap: IntSup%c\n", | |
1393 | FLAG(l, PCI_DOE_CAP_INT_SUPP)); | |
1394 | if (l & PCI_DOE_CAP_INT_SUPP) | |
1395 | printf("\t\t\tInterrupt Message Number %03x\n", | |
1396 | PCI_DOE_CAP_INT_MSG(l)); | |
1397 | ||
1398 | l = get_conf_long(d, where + PCI_DOE_CTL); | |
1399 | printf("\t\tDOECtl: IntEn%c\n", | |
1400 | FLAG(l, PCI_DOE_CTL_INT)); | |
1401 | ||
1402 | l = get_conf_long(d, where + PCI_DOE_STS); | |
1403 | printf("\t\tDOESta: Busy%c IntSta%c Error%c ObjectReady%c\n", | |
1404 | FLAG(l, PCI_DOE_STS_BUSY), | |
1405 | FLAG(l, PCI_DOE_STS_INT), | |
1406 | FLAG(l, PCI_DOE_STS_ERROR), | |
1407 | FLAG(l, PCI_DOE_STS_OBJECT_READY)); | |
1408 | } | |
1409 | ||
c7a34993 | 1410 | void |
a1492b88 | 1411 | show_ext_caps(struct device *d, int type) |
c7a34993 MM |
1412 | { |
1413 | int where = 0x100; | |
1414 | char been_there[0x1000]; | |
1415 | memset(been_there, 0, 0x1000); | |
1416 | do | |
1417 | { | |
1418 | u32 header; | |
33088c24 | 1419 | int id, version; |
c7a34993 MM |
1420 | |
1421 | if (!config_fetch(d, where, 4)) | |
1422 | break; | |
1423 | header = get_conf_long(d, where); | |
861063f3 | 1424 | if (!header || header == 0xffffffff) |
c7a34993 MM |
1425 | break; |
1426 | id = header & 0xffff; | |
33088c24 MM |
1427 | version = (header >> 16) & 0xf; |
1428 | printf("\tCapabilities: [%03x", where); | |
1429 | if (verbose > 1) | |
1430 | printf(" v%d", version); | |
1431 | printf("] "); | |
c7a34993 MM |
1432 | if (been_there[where]++) |
1433 | { | |
1434 | printf("<chain looped>\n"); | |
1435 | break; | |
1436 | } | |
1437 | switch (id) | |
1438 | { | |
c508d1c9 BH |
1439 | case PCI_EXT_CAP_ID_NULL: |
1440 | printf("Null\n"); | |
1441 | break; | |
c7a34993 | 1442 | case PCI_EXT_CAP_ID_AER: |
a1492b88 | 1443 | cap_aer(d, where, type); |
c7a34993 | 1444 | break; |
de91b6f2 KB |
1445 | case PCI_EXT_CAP_ID_DPC: |
1446 | cap_dpc(d, where); | |
1447 | break; | |
c7a34993 | 1448 | case PCI_EXT_CAP_ID_VC: |
33088c24 MM |
1449 | case PCI_EXT_CAP_ID_VC2: |
1450 | cap_vc(d, where); | |
c7a34993 MM |
1451 | break; |
1452 | case PCI_EXT_CAP_ID_DSN: | |
1453 | cap_dsn(d, where); | |
1454 | break; | |
1455 | case PCI_EXT_CAP_ID_PB: | |
1456 | printf("Power Budgeting <?>\n"); | |
1457 | break; | |
1458 | case PCI_EXT_CAP_ID_RCLINK: | |
5a9a932c | 1459 | cap_rclink(d, where); |
c7a34993 MM |
1460 | break; |
1461 | case PCI_EXT_CAP_ID_RCILINK: | |
1462 | printf("Root Complex Internal Link <?>\n"); | |
1463 | break; | |
e12bd01e SK |
1464 | case PCI_EXT_CAP_ID_RCEC: |
1465 | cap_rcec(d, where); | |
c7a34993 MM |
1466 | break; |
1467 | case PCI_EXT_CAP_ID_MFVC: | |
1468 | printf("Multi-Function Virtual Channel <?>\n"); | |
1469 | break; | |
eff08b33 BH |
1470 | case PCI_EXT_CAP_ID_RCRB: |
1471 | printf("Root Complex Register Block <?>\n"); | |
c7a34993 MM |
1472 | break; |
1473 | case PCI_EXT_CAP_ID_VNDR: | |
78ca9582 | 1474 | cap_evendor(d, where); |
c7a34993 MM |
1475 | break; |
1476 | case PCI_EXT_CAP_ID_ACS: | |
1477 | cap_acs(d, where); | |
1478 | break; | |
1479 | case PCI_EXT_CAP_ID_ARI: | |
1480 | cap_ari(d, where); | |
1481 | break; | |
1482 | case PCI_EXT_CAP_ID_ATS: | |
1483 | cap_ats(d, where); | |
1484 | break; | |
1485 | case PCI_EXT_CAP_ID_SRIOV: | |
1486 | cap_sriov(d, where); | |
1487 | break; | |
b8f7cd64 BH |
1488 | case PCI_EXT_CAP_ID_MRIOV: |
1489 | printf("Multi-Root I/O Virtualization <?>\n"); | |
1490 | break; | |
c0d9545c BH |
1491 | case PCI_EXT_CAP_ID_MCAST: |
1492 | cap_multicast(d, where, type); | |
1493 | break; | |
a858df0d DW |
1494 | case PCI_EXT_CAP_ID_PRI: |
1495 | cap_pri(d, where); | |
1496 | break; | |
b8f7cd64 | 1497 | case PCI_EXT_CAP_ID_REBAR: |
44c6c7fc | 1498 | cap_rebar(d, where, 0); |
b8f7cd64 BH |
1499 | break; |
1500 | case PCI_EXT_CAP_ID_DPA: | |
1501 | printf("Dynamic Power Allocation <?>\n"); | |
1502 | break; | |
67da1792 MM |
1503 | case PCI_EXT_CAP_ID_TPH: |
1504 | cap_tph(d, where); | |
1505 | break; | |
1506 | case PCI_EXT_CAP_ID_LTR: | |
1507 | cap_ltr(d, where); | |
1508 | break; | |
b8f7cd64 | 1509 | case PCI_EXT_CAP_ID_SECPCI: |
9225e71d | 1510 | cap_sec(d, where); |
b8f7cd64 BH |
1511 | break; |
1512 | case PCI_EXT_CAP_ID_PMUX: | |
1513 | printf("Protocol Multiplexing <?>\n"); | |
1514 | break; | |
a858df0d DW |
1515 | case PCI_EXT_CAP_ID_PASID: |
1516 | cap_pasid(d, where); | |
1517 | break; | |
b8f7cd64 BH |
1518 | case PCI_EXT_CAP_ID_LNR: |
1519 | printf("LN Requester <?>\n"); | |
1520 | break; | |
214c9a95 DB |
1521 | case PCI_EXT_CAP_ID_L1PM: |
1522 | cap_l1pm(d, where); | |
1523 | break; | |
415a9c18 YJ |
1524 | case PCI_EXT_CAP_ID_PTM: |
1525 | cap_ptm(d, where); | |
1526 | break; | |
b8f7cd64 BH |
1527 | case PCI_EXT_CAP_ID_M_PCIE: |
1528 | printf("PCI Express over M_PHY <?>\n"); | |
1529 | break; | |
1530 | case PCI_EXT_CAP_ID_FRS: | |
1531 | printf("FRS Queueing <?>\n"); | |
1532 | break; | |
1533 | case PCI_EXT_CAP_ID_RTR: | |
1534 | printf("Readiness Time Reporting <?>\n"); | |
1535 | break; | |
1536 | case PCI_EXT_CAP_ID_DVSEC: | |
71aeac63 | 1537 | cap_dvsec(d, where); |
b8f7cd64 BH |
1538 | break; |
1539 | case PCI_EXT_CAP_ID_VF_REBAR: | |
44c6c7fc | 1540 | cap_rebar(d, where, 1); |
b8f7cd64 BH |
1541 | break; |
1542 | case PCI_EXT_CAP_ID_DLNK: | |
1543 | printf("Data Link Feature <?>\n"); | |
1544 | break; | |
1545 | case PCI_EXT_CAP_ID_16GT: | |
1546 | printf("Physical Layer 16.0 GT/s <?>\n"); | |
1547 | break; | |
1548 | case PCI_EXT_CAP_ID_LMR: | |
1549 | printf("Lane Margining at the Receiver <?>\n"); | |
1550 | break; | |
1551 | case PCI_EXT_CAP_ID_HIER_ID: | |
1552 | printf("Hierarchy ID <?>\n"); | |
1553 | break; | |
1554 | case PCI_EXT_CAP_ID_NPEM: | |
1555 | printf("Native PCIe Enclosure Management <?>\n"); | |
1556 | break; | |
60be9345 JC |
1557 | case PCI_EXT_CAP_ID_DOE: |
1558 | cap_doe(d, where); | |
1559 | break; | |
c7a34993 | 1560 | default: |
60a45a7e | 1561 | printf("Extended Capability ID %#02x\n", id); |
c7a34993 MM |
1562 | break; |
1563 | } | |
d61c4772 | 1564 | where = (header >> 20) & ~3; |
c7a34993 MM |
1565 | } while (where); |
1566 | } |