/*
* The PCI Utilities -- Show Capabilities
*
- * Copyright (c) 1997--2008 Martin Mares <mj@ucw.cz>
+ * Copyright (c) 1997--2010 Martin Mares <mj@ucw.cz>
*
* Can be freely distributed and used under the terms of the GNU GPL.
*/
FLAG(cap, PCI_PM_CAP_DSI),
FLAG(cap, PCI_PM_CAP_D1),
FLAG(cap, PCI_PM_CAP_D2),
- pm_aux_current[(cap >> 6) & 7],
+ pm_aux_current[(cap & PCI_PM_CAP_AUX_C_MASK) >> 6],
FLAG(cap, PCI_PM_CAP_PME_D0),
FLAG(cap, PCI_PM_CAP_PME_D1),
FLAG(cap, PCI_PM_CAP_PME_D2),
1 << (9 + ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U)),
max_outstanding[(command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U]);
printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c DC=%s DMMRBC=%u DMOST=%u DMCRS=%u RSCEM%c 266MHz%c 533MHz%c\n",
- ((status >> 8) & 0xff),
- ((status >> 3) & 0x1f),
+ (status & PCI_PCIX_STATUS_BUS) >> 8,
+ (status & PCI_PCIX_STATUS_DEVICE) >> 3,
(status & PCI_PCIX_STATUS_FUNCTION),
FLAG(status, PCI_PCIX_STATUS_64BIT),
FLAG(status, PCI_PCIX_STATUS_133MHZ),
FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED),
FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC),
((status & PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"),
- 1 << (9 + ((status >> 21) & 3U)),
- max_outstanding[(status >> 23) & 7U],
- 1 << (3 + ((status >> 26) & 7U)),
+ 1 << (9 + ((status & PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT) >> 21)),
+ max_outstanding[(status & PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS) >> 23],
+ 1 << (3 + ((status & PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE) >> 26)),
FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS),
FLAG(status, PCI_PCIX_STATUS_266MHZ),
FLAG(status, PCI_PCIX_STATUS_533MHZ));
FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC),
FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN),
FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED),
- sec_clock_freq[(secstatus >> 6) & 7]);
+ sec_clock_freq[(secstatus & PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ) >> 6]);
status = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS);
printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c\n",
- ((status >> 8) & 0xff),
- ((status >> 3) & 0x1f),
+ (status & PCI_PCIX_BRIDGE_STATUS_BUS) >> 8,
+ (status & PCI_PCIX_BRIDGE_STATUS_DEVICE) >> 3,
(status & PCI_PCIX_BRIDGE_STATUS_FUNCTION),
FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT),
FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ),
u16 w;
t = get_conf_long(d, where + PCI_EXP_DEVCAP);
- printf("\t\tDevCap:\tMaxPayload %d bytes, PhantFunc %d, Latency L0s %s, L1 %s\n",
+ printf("\t\tDevCap:\tMaxPayload %d bytes, PhantFunc %d",
128 << (t & PCI_EXP_DEVCAP_PAYLOAD),
- (1 << ((t & PCI_EXP_DEVCAP_PHANTOM) >> 3)) - 1,
+ (1 << ((t & PCI_EXP_DEVCAP_PHANTOM) >> 3)) - 1);
+ if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END))
+ printf(", Latency L0s %s, L1 %s",
latency_l0s((t & PCI_EXP_DEVCAP_L0S) >> 6),
latency_l1((t & PCI_EXP_DEVCAP_L1) >> 9));
+ printf("\n");
printf("\t\t\tExtTag%c", FLAG(t, PCI_EXP_DEVCAP_EXT_TAG));
if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) ||
(type == PCI_EXP_TYPE_UPSTREAM) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
printf(" AttnBtn%c AttnInd%c PwrInd%c",
FLAG(t, PCI_EXP_DEVCAP_ATN_BUT),
FLAG(t, PCI_EXP_DEVCAP_ATN_IND), FLAG(t, PCI_EXP_DEVCAP_PWR_IND));
- printf(" RBE%c FLReset%c",
- FLAG(t, PCI_EXP_DEVCAP_RBE),
+ printf(" RBE%c",
+ FLAG(t, PCI_EXP_DEVCAP_RBE));
+ if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END))
+ printf(" FLReset%c",
FLAG(t, PCI_EXP_DEVCAP_FLRESET));
- if (type == PCI_EXP_TYPE_UPSTREAM)
- printf("SlotPowerLimit %fW",
+ if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_UPSTREAM) ||
+ (type == PCI_EXP_TYPE_PCI_BRIDGE))
+ printf(" SlotPowerLimit %.3fW",
power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18,
(t & PCI_EXP_DEVCAP_PWR_SCL) >> 26));
printf("\n");
FLAG(w, PCI_EXP_DEVCTL_PHANTOM),
FLAG(w, PCI_EXP_DEVCTL_AUX_PME),
FLAG(w, PCI_EXP_DEVCTL_NOSNOOP));
- if (type == PCI_EXP_TYPE_PCI_BRIDGE || type == PCI_EXP_TYPE_PCIE_BRIDGE)
+ if (type == PCI_EXP_TYPE_PCI_BRIDGE)
printf(" BrConfRtry%c", FLAG(w, PCI_EXP_DEVCTL_BCRE));
- if (type == PCI_EXP_TYPE_ENDPOINT && (t & PCI_EXP_DEVCAP_FLRESET))
+ if (((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END)) &&
+ (t & PCI_EXP_DEVCAP_FLRESET))
printf(" FLReset%c", FLAG(w, PCI_EXP_DEVCTL_FLRESET));
printf("\n\t\t\tMaxPayload %d bytes, MaxReadReq %d bytes\n",
128 << ((w & PCI_EXP_DEVCTL_PAYLOAD) >> 5),
return "2.5GT/s";
case 2:
return "5GT/s";
+ case 3:
+ return "8GT/s";
+ case 4:
+ return "16GT/s";
default:
return "unknown";
}
{
switch (code)
{
+ case 0:
+ return "not supported";
case 1:
return "L0s";
+ case 2:
+ return "L1";
case 3:
return "L0s L1";
default:
static void cap_express_link(struct device *d, int where, int type)
{
- u32 t;
+ u32 t, aspm;
u16 w;
t = get_conf_long(d, where + PCI_EXP_LNKCAP);
- printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s, Latency L0 %s, L1 %s\n",
+ aspm = (t & PCI_EXP_LNKCAP_ASPM) >> 10;
+ printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s",
t >> 24,
link_speed(t & PCI_EXP_LNKCAP_SPEED), (t & PCI_EXP_LNKCAP_WIDTH) >> 4,
- aspm_support((t & PCI_EXP_LNKCAP_ASPM) >> 10),
- latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12),
- latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
- printf("\t\t\tClockPM%c Surprise%c LLActRep%c BwNot%c\n",
+ aspm_support(aspm));
+ if (aspm)
+ {
+ printf(", Exit Latency ");
+ if (aspm & 1)
+ printf("L0s %s", latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12));
+ if (aspm & 2)
+ printf("%sL1 %s", (aspm & 1) ? ", " : "",
+ latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
+ }
+ printf("\n");
+ printf("\t\t\tClockPM%c Surprise%c LLActRep%c BwNot%c ASPMOptComp%c\n",
FLAG(t, PCI_EXP_LNKCAP_CLOCKPM),
FLAG(t, PCI_EXP_LNKCAP_SURPRISE),
FLAG(t, PCI_EXP_LNKCAP_DLLA),
- FLAG(t, PCI_EXP_LNKCAP_LBNC));
+ FLAG(t, PCI_EXP_LNKCAP_LBNC),
+ FLAG(t, PCI_EXP_LNKCAP_AOC));
w = get_conf_word(d, where + PCI_EXP_LNKCTL);
printf("\t\tLnkCtl:\tASPM %s;", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM));
if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) ||
- (type == PCI_EXP_TYPE_LEG_END))
+ (type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
printf(" RCB %d bytes", w & PCI_EXP_LNKCTL_RCB ? 128 : 64);
- printf(" Disabled%c Retrain%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n",
+ printf(" Disabled%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n",
FLAG(w, PCI_EXP_LNKCTL_DISABLE),
- FLAG(w, PCI_EXP_LNKCTL_RETRAIN),
FLAG(w, PCI_EXP_LNKCTL_CLOCK),
FLAG(w, PCI_EXP_LNKCTL_XSYNCH),
FLAG(w, PCI_EXP_LNKCTL_CLOCKPM),
u16 w;
t = get_conf_long(d, where + PCI_EXP_SLTCAP);
- printf("\t\tSltCap:\tAttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surpise%c\n",
+ printf("\t\tSltCap:\tAttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c\n",
FLAG(t, PCI_EXP_SLTCAP_ATNB),
FLAG(t, PCI_EXP_SLTCAP_PWRC),
FLAG(t, PCI_EXP_SLTCAP_MRL),
FLAG(t, PCI_EXP_SLTCAP_PWRI),
FLAG(t, PCI_EXP_SLTCAP_HPC),
FLAG(t, PCI_EXP_SLTCAP_HPS));
- printf("\t\t\tSlot #%3x, PowerLimit %f; Interlock%c NoCompl%c\n",
- t >> 19,
+ printf("\t\t\tSlot #%d, PowerLimit %.3fW; Interlock%c NoCompl%c\n",
+ (t & PCI_EXP_SLTCAP_PSN) >> 19,
power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7, (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15),
FLAG(t, PCI_EXP_SLTCAP_INTERLOCK),
FLAG(t, PCI_EXP_SLTCAP_NOCMDCOMP));
}
}
+static const char *cap_express_devcap2_obff(int obff)
+{
+ switch (obff)
+ {
+ case 1:
+ return "Via message";
+ case 2:
+ return "Via WAKE#";
+ case 3:
+ return "Via message/WAKE#";
+ default:
+ return "Not Supported";
+ }
+}
+
+static const char *cap_express_devctl2_obff(int obff)
+{
+ switch (obff)
+ {
+ case 0:
+ return "Disabled";
+ case 1:
+ return "Via message A";
+ case 2:
+ return "Via message B";
+ case 3:
+ return "Via WAKE#";
+ default:
+ return "Unknown";
+ }
+}
+
+static int
+device_has_memory_space_bar(struct device *d)
+{
+ struct pci_dev *p = d->dev;
+ int i, found = 0;
+
+ for (i=0; i<6; i++)
+ if (p->base_addr[i] && p->size[i])
+ {
+ if (!(p->base_addr[i] & PCI_BASE_ADDRESS_SPACE_IO))
+ {
+ found = 1;
+ break;
+ }
+ }
+ return found;
+}
+
static void cap_express_dev2(struct device *d, int where, int type)
{
u32 l;
u16 w;
+ int has_mem_bar = device_has_memory_space_bar(d);
l = get_conf_long(d, where + PCI_EXP_DEVCAP2);
- printf("\t\tDevCap2: Completion Timeout: %s, TimeoutDis%c",
+ printf("\t\tDevCap2: Completion Timeout: %s, TimeoutDis%c, LTR%c, OBFF %s",
cap_express_dev2_timeout_range(PCI_EXP_DEV2_TIMEOUT_RANGE(l)),
- FLAG(l, PCI_EXP_DEV2_TIMEOUT_DIS));
+ FLAG(l, PCI_EXP_DEV2_TIMEOUT_DIS),
+ FLAG(l, PCI_EXP_DEVCAP2_LTR),
+ cap_express_devcap2_obff(PCI_EXP_DEVCAP2_OBFF(l)));
if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
printf(" ARIFwd%c\n", FLAG(l, PCI_EXP_DEV2_ARI));
else
printf("\n");
+ if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
+ type == PCI_EXP_TYPE_DOWNSTREAM || has_mem_bar)
+ {
+ printf("\t\t\t AtomicOpsCap:");
+ if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
+ type == PCI_EXP_TYPE_DOWNSTREAM)
+ printf(" Routing%c", FLAG(l, PCI_EXP_DEVCAP2_ATOMICOP_ROUTING));
+ if (type == PCI_EXP_TYPE_ROOT_PORT || has_mem_bar)
+ printf(" 32bit%c 64bit%c 128bitCAS%c",
+ FLAG(l, PCI_EXP_DEVCAP2_32BIT_ATOMICOP_COMP),
+ FLAG(l, PCI_EXP_DEVCAP2_64BIT_ATOMICOP_COMP),
+ FLAG(l, PCI_EXP_DEVCAP2_128BIT_CAS_COMP));
+ printf("\n");
+ }
w = get_conf_word(d, where + PCI_EXP_DEVCTL2);
- printf("\t\tDevCtl2: Completion Timeout: %s, TimeoutDis%c",
+ printf("\t\tDevCtl2: Completion Timeout: %s, TimeoutDis%c, LTR%c, OBFF %s",
cap_express_dev2_timeout_value(PCI_EXP_DEV2_TIMEOUT_VALUE(w)),
- FLAG(w, PCI_EXP_DEV2_TIMEOUT_DIS));
+ FLAG(w, PCI_EXP_DEV2_TIMEOUT_DIS),
+ FLAG(w, PCI_EXP_DEV2_LTR),
+ cap_express_devctl2_obff(PCI_EXP_DEV2_OBFF(w)));
if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
printf(" ARIFwd%c\n", FLAG(w, PCI_EXP_DEV2_ARI));
else
printf("\n");
+ if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
+ type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ENDPOINT ||
+ type == PCI_EXP_TYPE_ROOT_INT_EP || type == PCI_EXP_TYPE_LEG_END)
+ {
+ printf("\t\t\t AtomicOpsCtl:");
+ if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ENDPOINT ||
+ type == PCI_EXP_TYPE_ROOT_INT_EP || type == PCI_EXP_TYPE_LEG_END)
+ printf(" ReqEn%c", FLAG(w, PCI_EXP_DEV2_ATOMICOP_REQUESTER_EN));
+ if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
+ type == PCI_EXP_TYPE_DOWNSTREAM)
+ printf(" EgressBlck%c", FLAG(w, PCI_EXP_DEV2_ATOMICOP_EGRESS_BLOCK));
+ printf("\n");
+ }
}
static const char *cap_express_link2_speed(int type)
return "2.5GT/s";
case 2:
return "5GT/s";
+ case 3:
+ return "8GT/s";
+ case 4:
+ return "16GT/s";
default:
return "Unknown";
}
}
}
-static void cap_express_link2(struct device *d, int where, int type UNUSED)
+static void cap_express_link2(struct device *d, int where, int type)
{
u16 w;
- w = get_conf_word(d, where + PCI_EXP_LNKCTL2);
- printf("\t\tLnkCtl2: Target Link Speed: %s, EnterCompliance%c SpeedDis%c, Selectable De-emphasis: %s\n"
- "\t\t\t Transmit Margin: %s, EnterModifiedCompliance%c ComplianceSOS%c\n"
- "\t\t\t Compliance De-emphasis: %s\n",
+ if (!((type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_LEG_END) &&
+ (d->dev->dev != 0 || d->dev->func != 0))) {
+ w = get_conf_word(d, where + PCI_EXP_LNKCTL2);
+ printf("\t\tLnkCtl2: Target Link Speed: %s, EnterCompliance%c SpeedDis%c",
cap_express_link2_speed(PCI_EXP_LNKCTL2_SPEED(w)),
FLAG(w, PCI_EXP_LNKCTL2_CMPLNC),
- FLAG(w, PCI_EXP_LNKCTL2_SPEED_DIS),
- cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_DEEMPHASIS(w)),
+ FLAG(w, PCI_EXP_LNKCTL2_SPEED_DIS));
+ if (type == PCI_EXP_TYPE_DOWNSTREAM)
+ printf(", Selectable De-emphasis: %s",
+ cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_DEEMPHASIS(w)));
+ printf("\n"
+ "\t\t\t Transmit Margin: %s, EnterModifiedCompliance%c ComplianceSOS%c\n"
+ "\t\t\t Compliance De-emphasis: %s\n",
cap_express_link2_transmargin(PCI_EXP_LNKCTL2_MARGIN(w)),
FLAG(w, PCI_EXP_LNKCTL2_MOD_CMPLNC),
FLAG(w, PCI_EXP_LNKCTL2_CMPLNC_SOS),
cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_COM_DEEMPHASIS(w)));
+ }
w = get_conf_word(d, where + PCI_EXP_LNKSTA2);
- printf("\t\tLnkSta2: Current De-emphasis Level: %s\n",
- cap_express_link2_deemphasis(PCI_EXP_LINKSTA2_DEEMPHASIS(w)));
+ printf("\t\tLnkSta2: Current De-emphasis Level: %s, EqualizationComplete%c, EqualizationPhase1%c\n"
+ "\t\t\t EqualizationPhase2%c, EqualizationPhase3%c, LinkEqualizationRequest%c\n",
+ cap_express_link2_deemphasis(PCI_EXP_LINKSTA2_DEEMPHASIS(w)),
+ FLAG(w, PCI_EXP_LINKSTA2_EQU_COMP),
+ FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE1),
+ FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE2),
+ FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE3),
+ FLAG(w, PCI_EXP_LINKSTA2_EQU_REQ));
}
static void cap_express_slot2(struct device *d UNUSED, int where UNUSED)
/* No capabilities that require this field in PCIe rev2.0 spec. */
}
-static void
+static int
cap_express(struct device *d, int where, int cap)
{
int type = (cap & PCI_EXP_FLAGS_TYPE) >> 4;
int size;
int slot = 0;
+ int link = 1;
printf("Express ");
if (verbose >= 2)
printf("Downstream Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
break;
case PCI_EXP_TYPE_PCI_BRIDGE:
- printf("PCI/PCI-X Bridge");
+ printf("PCI-Express to PCI/PCI-X Bridge");
break;
case PCI_EXP_TYPE_PCIE_BRIDGE:
- printf("PCI/PCI-X to PCI-Express Bridge");
+ slot = cap & PCI_EXP_FLAGS_SLOT;
+ printf("PCI/PCI-X to PCI-Express Bridge (Slot%c)",
+ FLAG(cap, PCI_EXP_FLAGS_SLOT));
break;
case PCI_EXP_TYPE_ROOT_INT_EP:
+ link = 0;
printf("Root Complex Integrated Endpoint");
break;
case PCI_EXP_TYPE_ROOT_EC:
+ link = 0;
printf("Root Complex Event Collector");
break;
default:
}
printf(", MSI %02x\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
if (verbose < 2)
- return;
+ return type;
size = 16;
if (slot)
if (type == PCI_EXP_TYPE_ROOT_PORT)
size = 32;
if (!config_fetch(d, where + PCI_EXP_DEVCAP, size))
- return;
+ return type;
cap_express_dev(d, where, type);
- cap_express_link(d, where, type);
+ if (link)
+ cap_express_link(d, where, type);
if (slot)
cap_express_slot(d, where);
if (type == PCI_EXP_TYPE_ROOT_PORT)
cap_express_root(d, where);
if ((cap & PCI_EXP_FLAGS_VERS) < 2)
- return;
+ return type;
size = 16;
if (slot)
size = 24;
if (!config_fetch(d, where + PCI_EXP_DEVCAP2, size))
- return;
+ return type;
cap_express_dev2(d, where, type);
- cap_express_link2(d, where, type);
+ if (link)
+ cap_express_link2(d, where, type);
if (slot)
cap_express_slot2(d, where);
+ return type;
}
static void
printf("\t\tAFStatus: TP%c\n", FLAG(reg, PCI_AF_STATUS_TP));
}
+static void
+cap_sata_hba(struct device *d, int where, int cap)
+{
+ u32 bars;
+ int bar;
+
+ printf("SATA HBA v%d.%d", BITS(cap, 4, 4), BITS(cap, 0, 4));
+ if (verbose < 2 || !config_fetch(d, where + PCI_SATA_HBA_BARS, 4))
+ {
+ printf("\n");
+ return;
+ }
+
+ bars = get_conf_long(d, where + PCI_SATA_HBA_BARS);
+ bar = BITS(bars, 0, 4);
+ if (bar >= 4 && bar <= 9)
+ printf(" BAR%d Offset=%08x\n", bar - 4, BITS(bars, 4, 20));
+ else if (bar == 15)
+ printf(" InCfgSpace\n");
+ else
+ printf(" BAR??%d\n", bar);
+}
+
+static const char *cap_ea_property(int p, int is_secondary)
+{
+ switch (p) {
+ case 0x00:
+ return "memory space, non-prefetchable";
+ case 0x01:
+ return "memory space, prefetchable";
+ case 0x02:
+ return "I/O space";
+ case 0x03:
+ return "VF memory space, prefetchable";
+ case 0x04:
+ return "VF memory space, non-prefetchable";
+ case 0x05:
+ return "allocation behind bridge, non-prefetchable memory";
+ case 0x06:
+ return "allocation behind bridge, prefetchable memory";
+ case 0x07:
+ return "allocation behind bridge, I/O space";
+ case 0xfd:
+ return "memory space resource unavailable for use";
+ case 0xfe:
+ return "I/O space resource unavailable for use";
+ case 0xff:
+ if (is_secondary)
+ return "entry unavailable for use, PrimaryProperties should be used";
+ else
+ return "entry unavailable for use";
+ default:
+ return NULL;
+ }
+}
+
+static void cap_ea(struct device *d, int where, int cap)
+{
+ int entry;
+ int entry_base = where + 4;
+ int num_entries = BITS(cap, 0, 6);
+ u8 htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
+
+ printf("Enhanced Allocation (EA): NumEntries=%u", num_entries);
+ if (htype == PCI_HEADER_TYPE_BRIDGE) {
+ byte fixed_sub, fixed_sec;
+
+ entry_base += 4;
+ if (!config_fetch(d, where + 4, 2)) {
+ printf("\n");
+ return;
+ }
+ fixed_sec = get_conf_byte(d, where + PCI_EA_CAP_TYPE1_SECONDARY);
+ fixed_sub = get_conf_byte(d, where + PCI_EA_CAP_TYPE1_SUBORDINATE);
+ printf(", secondary=%d, subordinate=%d", fixed_sec, fixed_sub);
+ }
+ printf("\n");
+ if (verbose < 2)
+ return;
+
+ for (entry = 0; entry < num_entries; entry++) {
+ int max_offset_high_pos, has_base_high, has_max_offset_high;
+ u32 entry_header;
+ u32 base, max_offset;
+ int es, bei, pp, sp;
+ const char *prop_text;
+
+ if (!config_fetch(d, entry_base, 4))
+ return;
+ entry_header = get_conf_long(d, entry_base);
+ es = BITS(entry_header, 0, 3);
+ bei = BITS(entry_header, 4, 4);
+ pp = BITS(entry_header, 8, 8);
+ sp = BITS(entry_header, 16, 8);
+ if (!config_fetch(d, entry_base + 4, es * 4))
+ return;
+ printf("\t\tEntry %u: Enable%c Writable%c EntrySize=%u\n", entry,
+ FLAG(entry_header, PCI_EA_CAP_ENT_ENABLE),
+ FLAG(entry_header, PCI_EA_CAP_ENT_WRITABLE), es);
+ printf("\t\t\t BAR Equivalent Indicator: ");
+ switch (bei) {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ printf("BAR %u", bei);
+ break;
+ case 6:
+ printf("resource behind function");
+ break;
+ case 7:
+ printf("not indicated");
+ break;
+ case 8:
+ printf("expansion ROM");
+ break;
+ case 9:
+ case 10:
+ case 11:
+ case 12:
+ case 13:
+ case 14:
+ printf("VF-BAR %u", bei - 9);
+ break;
+ default:
+ printf("reserved");
+ break;
+ }
+ printf("\n");
+
+ prop_text = cap_ea_property(pp, 0);
+ printf("\t\t\t PrimaryProperties: ");
+ if (prop_text)
+ printf("%s\n", prop_text);
+ else
+ printf("[%02x]\n", pp);
+
+ prop_text = cap_ea_property(sp, 1);
+ printf("\t\t\t SecondaryProperties: ");
+ if (prop_text)
+ printf("%s\n", prop_text);
+ else
+ printf("[%02x]\n", sp);
+
+ base = get_conf_long(d, entry_base + 4);
+ has_base_high = ((base & 2) != 0);
+ base &= ~3;
+
+ max_offset = get_conf_long(d, entry_base + 8);
+ has_max_offset_high = ((max_offset & 2) != 0);
+ max_offset |= 3;
+ max_offset_high_pos = entry_base + 12;
+
+ printf("\t\t\t Base: ");
+ if (has_base_high) {
+ u32 base_high = get_conf_long(d, entry_base + 12);
+
+ printf("%x", base_high);
+ max_offset_high_pos += 4;
+ }
+ printf("%08x\n", base);
+
+ printf("\t\t\t MaxOffset: ");
+ if (has_max_offset_high) {
+ u32 max_offset_high = get_conf_long(d, max_offset_high_pos);
+
+ printf("%x", max_offset_high);
+ }
+ printf("%08x\n", max_offset);
+
+ entry_base += 4 + 4 * es;
+ }
+}
+
void
-show_caps(struct device *d)
+show_caps(struct device *d, int where)
{
int can_have_ext_caps = 0;
+ int type = -1;
if (get_conf_word(d, PCI_STATUS) & PCI_STATUS_CAP_LIST)
{
- int where = get_conf_byte(d, PCI_CAPABILITY_LIST) & ~3;
byte been_there[256];
+ where = get_conf_byte(d, where) & ~3;
memset(been_there, 0, 256);
while (where)
{
cap_ht(d, where, cap);
break;
case PCI_CAP_ID_VNDR:
- printf("Vendor Specific Information <?>\n");
+ show_vendor_caps(d, where, cap);
break;
case PCI_CAP_ID_DBG:
cap_debug_port(cap);
printf("Secure device <?>\n");
break;
case PCI_CAP_ID_EXP:
- cap_express(d, where, cap);
+ type = cap_express(d, where, cap);
can_have_ext_caps = 1;
break;
case PCI_CAP_ID_MSIX:
cap_msix(d, where, cap);
break;
case PCI_CAP_ID_SATA:
- printf("SATA HBA <?>\n");
+ cap_sata_hba(d, where, cap);
break;
case PCI_CAP_ID_AF:
cap_af(d, where);
break;
+ case PCI_CAP_ID_EA:
+ cap_ea(d, where, cap);
+ break;
default:
printf("#%02x [%04x]\n", id, cap);
}
}
}
if (can_have_ext_caps)
- show_ext_caps(d);
+ show_ext_caps(d, type);
}
projects / thirdparty / pciutils.git / blobdiff