lspci: Make DevCtl, DevSta, and AER decoding more consistent

[thirdparty/pciutils.git] / ls-caps.c

diff --git a/ls-caps.c b/ls-caps.c
index 30f371f062058ee729f6a1fbaa6da65d93069f03..158ac38f864291723c02366e0d01f473dde98c6f 100644 (file)
--- a/ls-caps.c
+++ b/ls-caps.c
@@ -25,7 +25,7 @@ cap_pm(struct device *d, int where, int cap)
         FLAG(cap, PCI_PM_CAP_DSI),
         FLAG(cap, PCI_PM_CAP_D1),
         FLAG(cap, PCI_PM_CAP_D2),
-        pm_aux_current[(cap >> 6) & 7],
+        pm_aux_current[(cap & PCI_PM_CAP_AUX_C_MASK) >> 6],
         FLAG(cap, PCI_PM_CAP_PME_D0),
         FLAG(cap, PCI_PM_CAP_PME_D1),
         FLAG(cap, PCI_PM_CAP_PME_D2),
@@ -136,17 +136,17 @@ cap_pcix_nobridge(struct device *d, int where)
         1 << (9 + ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U)),
         max_outstanding[(command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U]);
   printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c DC=%s DMMRBC=%u DMOST=%u DMCRS=%u RSCEM%c 266MHz%c 533MHz%c\n",
-        ((status >> 8) & 0xff),
-        ((status >> 3) & 0x1f),
+        (status & PCI_PCIX_STATUS_BUS) >> 8,
+        (status & PCI_PCIX_STATUS_DEVICE) >> 3,
         (status & PCI_PCIX_STATUS_FUNCTION),
         FLAG(status, PCI_PCIX_STATUS_64BIT),
         FLAG(status, PCI_PCIX_STATUS_133MHZ),
         FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED),
         FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC),
         ((status & PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"),
-        1 << (9 + ((status >> 21) & 3U)),
-        max_outstanding[(status >> 23) & 7U],
-        1 << (3 + ((status >> 26) & 7U)),
+        1 << (9 + ((status & PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT) >> 21)),
+        max_outstanding[(status & PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS) >> 23],
+        1 << (3 + ((status & PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE) >> 26)),
         FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS),
         FLAG(status, PCI_PCIX_STATUS_266MHZ),
         FLAG(status, PCI_PCIX_STATUS_533MHZ));
@@ -175,11 +175,11 @@ cap_pcix_bridge(struct device *d, int where)
         FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC),
         FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN),
         FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED),
-        sec_clock_freq[(secstatus >> 6) & 7]);
+        sec_clock_freq[(secstatus & PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ) >> 6]);
   status = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS);
   printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c\n",
-        ((status >> 8) & 0xff),
-        ((status >> 3) & 0x1f),
+        (status & PCI_PCIX_BRIDGE_STATUS_BUS) >> 8,
+        (status & PCI_PCIX_BRIDGE_STATUS_DEVICE) >> 3,
         (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION),
         FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT),
         FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ),
@@ -686,7 +686,7 @@ static void cap_express_dev(struct device *d, int where, int type)
   printf("\n");
 
   w = get_conf_word(d, where + PCI_EXP_DEVCTL);
-  printf("\t\tDevCtl:\tReport errors: Correctable%c Non-Fatal%c Fatal%c Unsupported%c\n",
+  printf("\t\tDevCtl:\tCorrErr%c NonFatalErr%c FatalErr%c UnsupReq%c\n",
        FLAG(w, PCI_EXP_DEVCTL_CERE),
        FLAG(w, PCI_EXP_DEVCTL_NFERE),
        FLAG(w, PCI_EXP_DEVCTL_FERE),
@@ -707,7 +707,7 @@ static void cap_express_dev(struct device *d, int where, int type)
        128 << ((w & PCI_EXP_DEVCTL_READRQ) >> 12));
 
   w = get_conf_word(d, where + PCI_EXP_DEVSTA);
-  printf("\t\tDevSta:\tCorrErr%c UncorrErr%c FatalErr%c UnsuppReq%c AuxPwr%c TransPend%c\n",
+  printf("\t\tDevSta:\tCorrErr%c NonFatalErr%c FatalErr%c UnsupReq%c AuxPwr%c TransPend%c\n",
        FLAG(w, PCI_EXP_DEVSTA_CED),
        FLAG(w, PCI_EXP_DEVSTA_NFED),
        FLAG(w, PCI_EXP_DEVSTA_FED),
@@ -758,16 +758,25 @@ static const char *aspm_enabled(int code)
 
 static void cap_express_link(struct device *d, int where, int type)
 {
-  u32 t;
+  u32 t, aspm;
   u16 w;
 
   t = get_conf_long(d, where + PCI_EXP_LNKCAP);
-  printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s, Exit Latency L0s %s, L1 %s\n",
+  aspm = (t & PCI_EXP_LNKCAP_ASPM) >> 10;
+  printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s",
        t >> 24,
        link_speed(t & PCI_EXP_LNKCAP_SPEED), (t & PCI_EXP_LNKCAP_WIDTH) >> 4,
-       aspm_support((t & PCI_EXP_LNKCAP_ASPM) >> 10),
-       latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12),
-       latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
+       aspm_support(aspm));
+  if (aspm)
+    {
+      printf(", Exit Latency ");
+      if (aspm & 1)
+       printf("L0s %s", latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12));
+      if (aspm & 2)
+       printf("%sL1 %s", (aspm & 1) ? ", " : "",
+           latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
+    }
+  printf("\n");
   printf("\t\t\tClockPM%c Surprise%c LLActRep%c BwNot%c ASPMOptComp%c\n",
        FLAG(t, PCI_EXP_LNKCAP_CLOCKPM),
        FLAG(t, PCI_EXP_LNKCAP_SURPRISE),
@@ -822,7 +831,7 @@ static void cap_express_slot(struct device *d, int where)
        FLAG(t, PCI_EXP_SLTCAP_HPC),
        FLAG(t, PCI_EXP_SLTCAP_HPS));
   printf("\t\t\tSlot #%d, PowerLimit %.3fW; Interlock%c NoCompl%c\n",
-       t >> 19,
+       (t & PCI_EXP_SLTCAP_PSN) >> 19,
        power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7, (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15),
        FLAG(t, PCI_EXP_SLTCAP_INTERLOCK),
        FLAG(t, PCI_EXP_SLTCAP_NOCMDCOMP));
@@ -870,7 +879,7 @@ static void cap_express_root(struct device *d, int where)
   printf("\t\tRootCap: CRSVisible%c\n",
        FLAG(w, PCI_EXP_RTCAP_CRSVIS));
 
-  w = get_conf_word(d, where + PCI_EXP_RTSTA);
+  w = get_conf_long(d, where + PCI_EXP_RTSTA);
   printf("\t\tRootSta: PME ReqID %04x, PMEStatus%c PMEPending%c\n",
        w & PCI_EXP_RTSTA_PME_REQID,
        FLAG(w, PCI_EXP_RTSTA_PME_STATUS),
@@ -1000,7 +1009,7 @@ static void cap_express_dev2(struct device *d, int where, int type)
   if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
       type == PCI_EXP_TYPE_DOWNSTREAM || has_mem_bar)
     {
-       printf("\t\tAtomicOpsCap:");
+       printf("\t\t\t AtomicOpsCap:");
        if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
            type == PCI_EXP_TYPE_DOWNSTREAM)
          printf(" Routing%c", FLAG(l, PCI_EXP_DEVCAP2_ATOMICOP_ROUTING));
@@ -1026,7 +1035,7 @@ static void cap_express_dev2(struct device *d, int where, int type)
       type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ENDPOINT ||
       type == PCI_EXP_TYPE_ROOT_INT_EP || type == PCI_EXP_TYPE_LEG_END)
     {
-      printf("\t\tAtomicOpsCtl:");
+      printf("\t\t\t AtomicOpsCtl:");
       if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ENDPOINT ||
           type == PCI_EXP_TYPE_ROOT_INT_EP || type == PCI_EXP_TYPE_LEG_END)
         printf(" ReqEn%c", FLAG(w, PCI_EXP_DEV2_ATOMICOP_REQUESTER_EN));
@@ -1159,7 +1168,9 @@ cap_express(struct device *d, int where, int cap)
       printf("PCI-Express to PCI/PCI-X Bridge");
       break;
     case PCI_EXP_TYPE_PCIE_BRIDGE:
-      printf("PCI/PCI-X to PCI-Express Bridge");
+      slot = cap & PCI_EXP_FLAGS_SLOT;
+      printf("PCI/PCI-X to PCI-Express Bridge (Slot%c)",
+            FLAG(cap, PCI_EXP_FLAGS_SLOT));
       break;
     case PCI_EXP_TYPE_ROOT_INT_EP:
       link = 0;