*
* Copyright (c) 1997--2018 Martin Mares <mj@ucw.cz>
*
- * Can be freely distributed and used under the terms of the GNU GPL.
+ * Can be freely distributed and used under the terms of the GNU GPL v2+.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
*/
#include <stdio.h>
b = get_conf_byte(d, where + PCI_PM_PPB_EXTENSIONS);
if (b)
printf("\t\tBridge: PM%c B3%c\n",
- FLAG(t, PCI_PM_BPCC_ENABLE),
- FLAG(~t, PCI_PM_PPB_B2_B3));
+ FLAG(b, PCI_PM_BPCC_ENABLE),
+ FLAG(~b, PCI_PM_PPB_B2_B3));
}
static void
break;
offl = get_conf_long(d, where + PCI_HT_MSIM_ADDR_LO);
offh = get_conf_long(d, where + PCI_HT_MSIM_ADDR_HI);
- printf("\t\tMapping Address Base: %016llx\n", ((unsigned long long)offh << 32) | (offl & ~0xfffff));
+ printf("\t\tMapping Address Base: %016" PCI_U64_FMT_X "\n", ((u64)offh << 32) | (offl & ~0xfffff));
}
break;
case PCI_HT_CMD_TYP_DR:
}
}
-static float power_limit(int value, int scale)
+static int exp_downstream_port(int type)
+{
+ return type == PCI_EXP_TYPE_ROOT_PORT ||
+ type == PCI_EXP_TYPE_DOWNSTREAM ||
+ type == PCI_EXP_TYPE_PCIE_BRIDGE; /* PCI/PCI-X to PCIe Bridge */
+}
+
+static void show_power_limit(int value, int scale)
{
static const float scales[4] = { 1.0, 0.1, 0.01, 0.001 };
- return value * scales[scale];
+
+ if (scale == 0 && value == 0xFF)
+ {
+ printf(">600W");
+ return;
+ }
+
+ if (scale == 0 && value >= 0xF0 && value <= 0xFE)
+ value = 250 + 25 * (value - 0xF0);
+
+ printf("%gW", value * scales[scale]);
}
static const char *latency_l0s(int value)
FLAG(t, PCI_EXP_DEVCAP_ATN_IND), FLAG(t, PCI_EXP_DEVCAP_PWR_IND));
printf(" RBE%c",
FLAG(t, PCI_EXP_DEVCAP_RBE));
- if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END))
+ if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_ROOT_INT_EP))
printf(" FLReset%c",
FLAG(t, PCI_EXP_DEVCAP_FLRESET));
if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_UPSTREAM) ||
(type == PCI_EXP_TYPE_PCI_BRIDGE))
- printf(" SlotPowerLimit %.3fW",
- power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18,
- (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26));
+ {
+ printf(" SlotPowerLimit ");
+ show_power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18, (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26);
+ }
+ printf(" TEE-IO%c", FLAG(t, PCI_EXP_DEVCAP_TEE_IO));
printf("\n");
w = get_conf_word(d, where + PCI_EXP_DEVCTL);
FLAG(w, PCI_EXP_DEVCTL_NOSNOOP));
if (type == PCI_EXP_TYPE_PCI_BRIDGE)
printf(" BrConfRtry%c", FLAG(w, PCI_EXP_DEVCTL_BCRE));
- if (((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END)) &&
+ if (((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_ROOT_INT_EP)) &&
(t & PCI_EXP_DEVCAP_FLRESET))
printf(" FLReset%c", FLAG(w, PCI_EXP_DEVCTL_FLRESET));
printf("\n\t\t\tMaxPayload %d bytes, MaxReadReq %d bytes\n",
return "8GT/s";
case 4:
return "16GT/s";
+ case 5:
+ return "32GT/s";
+ case 6:
+ return "64GT/s";
default:
return "unknown";
}
}
-static char *link_compare(int sta, int cap)
+static char *link_compare(int type, int sta, int cap)
{
- if (sta < cap)
- return "downgraded";
if (sta > cap)
- return "strange";
- return "ok";
+ return " (overdriven)";
+ if (sta == cap)
+ return "";
+ if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_DOWNSTREAM) ||
+ (type == PCI_EXP_TYPE_PCIE_BRIDGE))
+ return "";
+ return " (downgraded)";
}
static char *aspm_support(int code)
printf("\t\tLnkCtl:\tASPM %s;", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM));
if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) ||
(type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
- printf(" RCB %d bytes", w & PCI_EXP_LNKCTL_RCB ? 128 : 64);
- printf(" Disabled%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n",
+ printf(" RCB %d bytes,", w & PCI_EXP_LNKCTL_RCB ? 128 : 64);
+ printf(" LnkDisable%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n",
FLAG(w, PCI_EXP_LNKCTL_DISABLE),
FLAG(w, PCI_EXP_LNKCTL_CLOCK),
FLAG(w, PCI_EXP_LNKCTL_XSYNCH),
w = get_conf_word(d, where + PCI_EXP_LNKSTA);
sta_speed = w & PCI_EXP_LNKSTA_SPEED;
sta_width = (w & PCI_EXP_LNKSTA_WIDTH) >> 4;
- printf("\t\tLnkSta:\tSpeed %s (%s), Width x%d (%s)\n",
+ printf("\t\tLnkSta:\tSpeed %s%s, Width x%d%s\n",
link_speed(sta_speed),
- link_compare(sta_speed, cap_speed),
+ link_compare(type, sta_speed, cap_speed),
sta_width,
- link_compare(sta_width, cap_width));
+ link_compare(type, sta_width, cap_width));
printf("\t\t\tTrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n",
FLAG(w, PCI_EXP_LNKSTA_TR_ERR),
FLAG(w, PCI_EXP_LNKSTA_TRAIN),
FLAG(t, PCI_EXP_SLTCAP_PWRI),
FLAG(t, PCI_EXP_SLTCAP_HPC),
FLAG(t, PCI_EXP_SLTCAP_HPS));
- printf("\t\t\tSlot #%d, PowerLimit %.3fW; Interlock%c NoCompl%c\n",
- (t & PCI_EXP_SLTCAP_PSN) >> 19,
- power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7, (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15),
+ printf("\t\t\tSlot #%d, PowerLimit ",
+ (t & PCI_EXP_SLTCAP_PSN) >> 19);
+ show_power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7, (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15);
+ printf("; Interlock%c NoCompl%c\n",
FLAG(t, PCI_EXP_SLTCAP_INTERLOCK),
FLAG(t, PCI_EXP_SLTCAP_NOCMDCOMP));
static void cap_express_root(struct device *d, int where)
{
- u32 w = get_conf_word(d, where + PCI_EXP_RTCTL);
+ u32 w;
+
+ w = get_conf_word(d, where + PCI_EXP_RTCAP);
+ printf("\t\tRootCap: CRSVisible%c\n",
+ FLAG(w, PCI_EXP_RTCAP_CRSVIS));
+
+ w = get_conf_word(d, where + PCI_EXP_RTCTL);
printf("\t\tRootCtl: ErrCorrectable%c ErrNon-Fatal%c ErrFatal%c PMEIntEna%c CRSVisible%c\n",
FLAG(w, PCI_EXP_RTCTL_SECEE),
FLAG(w, PCI_EXP_RTCTL_SENFEE),
FLAG(w, PCI_EXP_RTCTL_PMEIE),
FLAG(w, PCI_EXP_RTCTL_CRSVIS));
- w = get_conf_word(d, where + PCI_EXP_RTCAP);
- printf("\t\tRootCap: CRSVisible%c\n",
- FLAG(w, PCI_EXP_RTCAP_CRSVIS));
-
w = get_conf_long(d, where + PCI_EXP_RTSTA);
printf("\t\tRootSta: PME ReqID %04x, PMEStatus%c PMEPending%c\n",
w & PCI_EXP_RTSTA_PME_REQID,
}
}
+static const char *cap_express_devcap2_epr(int epr)
+{
+ switch (epr)
+ {
+ case 1:
+ return "Dev Specific";
+ case 2:
+ return "Form Factor Dev Specific";
+ case 3:
+ return "Reserved";
+ default:
+ return "Not Supported";
+ }
+}
+
+static const char *cap_express_devcap2_lncls(int lncls)
+{
+ switch (lncls)
+ {
+ case 1:
+ return "64byte cachelines";
+ case 2:
+ return "128byte cachelines";
+ case 3:
+ return "Reserved";
+ default:
+ return "Not Supported";
+ }
+}
+
+static const char *cap_express_devcap2_tphcomp(int tph)
+{
+ switch (tph)
+ {
+ case 1:
+ return "TPHComp+ ExtTPHComp-";
+ case 2:
+ /* Reserved; intentionally left blank */
+ return "";
+ case 3:
+ return "TPHComp+ ExtTPHComp+";
+ default:
+ return "TPHComp- ExtTPHComp-";
+ }
+}
+
static const char *cap_express_devctl2_obff(int obff)
{
switch (obff)
int i, found = 0;
for (i=0; i<6; i++)
- if (p->base_addr[i] && p->size[i])
+ if (p->base_addr[i] || p->size[i])
{
if (!(p->base_addr[i] & PCI_BASE_ADDRESS_SPACE_IO))
{
int has_mem_bar = device_has_memory_space_bar(d);
l = get_conf_long(d, where + PCI_EXP_DEVCAP2);
- printf("\t\tDevCap2: Completion Timeout: %s, TimeoutDis%c, LTR%c, OBFF %s",
- cap_express_dev2_timeout_range(PCI_EXP_DEV2_TIMEOUT_RANGE(l)),
- FLAG(l, PCI_EXP_DEV2_TIMEOUT_DIS),
- FLAG(l, PCI_EXP_DEVCAP2_LTR),
- cap_express_devcap2_obff(PCI_EXP_DEVCAP2_OBFF(l)));
+ printf("\t\tDevCap2: Completion Timeout: %s, TimeoutDis%c NROPrPrP%c LTR%c",
+ cap_express_dev2_timeout_range(PCI_EXP_DEVCAP2_TIMEOUT_RANGE(l)),
+ FLAG(l, PCI_EXP_DEVCAP2_TIMEOUT_DIS),
+ FLAG(l, PCI_EXP_DEVCAP2_NROPRPRP),
+ FLAG(l, PCI_EXP_DEVCAP2_LTR));
+ printf("\n\t\t\t 10BitTagComp%c 10BitTagReq%c OBFF %s, ExtFmt%c EETLPPrefix%c",
+ FLAG(l, PCI_EXP_DEVCAP2_10BIT_TAG_COMP),
+ FLAG(l, PCI_EXP_DEVCAP2_10BIT_TAG_REQ),
+ cap_express_devcap2_obff(PCI_EXP_DEVCAP2_OBFF(l)),
+ FLAG(l, PCI_EXP_DEVCAP2_EXTFMT),
+ FLAG(l, PCI_EXP_DEVCAP2_EE_TLP));
+
+ if (PCI_EXP_DEVCAP2_EE_TLP == (l & PCI_EXP_DEVCAP2_EE_TLP))
+ {
+ printf(", MaxEETLPPrefixes %d",
+ PCI_EXP_DEVCAP2_MEE_TLP(l) ? PCI_EXP_DEVCAP2_MEE_TLP(l) : 4);
+ }
+
+ printf("\n\t\t\t EmergencyPowerReduction %s, EmergencyPowerReductionInit%c",
+ cap_express_devcap2_epr(PCI_EXP_DEVCAP2_EPR(l)),
+ FLAG(l, PCI_EXP_DEVCAP2_EPR_INIT));
+ printf("\n\t\t\t FRS%c", FLAG(l, PCI_EXP_DEVCAP2_FRS));
+
+ if (type == PCI_EXP_TYPE_ROOT_PORT)
+ printf(" LN System CLS %s,",
+ cap_express_devcap2_lncls(PCI_EXP_DEVCAP2_LN_CLS(l)));
+
+ if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ENDPOINT)
+ printf(" %s", cap_express_devcap2_tphcomp(PCI_EXP_DEVCAP2_TPH_COMP(l)));
+
if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
- printf(" ARIFwd%c\n", FLAG(l, PCI_EXP_DEV2_ARI));
+ printf(" ARIFwd%c\n", FLAG(l, PCI_EXP_DEVCAP2_ARI));
else
printf("\n");
if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
}
w = get_conf_word(d, where + PCI_EXP_DEVCTL2);
- printf("\t\tDevCtl2: Completion Timeout: %s, TimeoutDis%c, LTR%c, OBFF %s",
- cap_express_dev2_timeout_value(PCI_EXP_DEV2_TIMEOUT_VALUE(w)),
- FLAG(w, PCI_EXP_DEV2_TIMEOUT_DIS),
- FLAG(w, PCI_EXP_DEV2_LTR),
- cap_express_devctl2_obff(PCI_EXP_DEV2_OBFF(w)));
+ printf("\t\tDevCtl2: Completion Timeout: %s, TimeoutDis%c",
+ cap_express_dev2_timeout_value(PCI_EXP_DEVCTL2_TIMEOUT_VALUE(w)),
+ FLAG(w, PCI_EXP_DEVCTL2_TIMEOUT_DIS));
if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
- printf(" ARIFwd%c\n", FLAG(w, PCI_EXP_DEV2_ARI));
+ printf(" ARIFwd%c\n", FLAG(w, PCI_EXP_DEVCTL2_ARI));
else
printf("\n");
if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
printf("\t\t\t AtomicOpsCtl:");
if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ENDPOINT ||
type == PCI_EXP_TYPE_ROOT_INT_EP || type == PCI_EXP_TYPE_LEG_END)
- printf(" ReqEn%c", FLAG(w, PCI_EXP_DEV2_ATOMICOP_REQUESTER_EN));
+ printf(" ReqEn%c", FLAG(w, PCI_EXP_DEVCTL2_ATOMICOP_REQUESTER_EN));
if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
type == PCI_EXP_TYPE_DOWNSTREAM)
- printf(" EgressBlck%c", FLAG(w, PCI_EXP_DEV2_ATOMICOP_EGRESS_BLOCK));
+ printf(" EgressBlck%c", FLAG(w, PCI_EXP_DEVCTL2_ATOMICOP_EGRESS_BLOCK));
printf("\n");
}
+ printf("\t\t\t IDOReq%c IDOCompl%c LTR%c EmergencyPowerReductionReq%c\n",
+ FLAG(w, PCI_EXP_DEVCTL2_IDO_REQ_EN),
+ FLAG(w, PCI_EXP_DEVCTL2_IDO_CMP_EN),
+ FLAG(w, PCI_EXP_DEVCTL2_LTR),
+ FLAG(w, PCI_EXP_DEVCTL2_EPR_REQ));
+ printf("\t\t\t 10BitTagReq%c OBFF %s, EETLPPrefixBlk%c\n",
+ FLAG(w, PCI_EXP_DEVCTL2_10BIT_TAG_REQ),
+ cap_express_devctl2_obff(PCI_EXP_DEVCTL2_OBFF(w)),
+ FLAG(w, PCI_EXP_DEVCTL2_EE_TLP_BLK));
+}
+
+static const char *cap_express_link2_speed_cap(int vector)
+{
+ /*
+ * Per PCIe r5.0, sec 8.2.1, a device must support 2.5GT/s and is not
+ * permitted to skip support for any data rates between 2.5GT/s and the
+ * highest supported rate.
+ */
+ if (vector & 0x40)
+ return "RsvdP";
+ if (vector & 0x20)
+ return "2.5-64GT/s";
+ if (vector & 0x10)
+ return "2.5-32GT/s";
+ if (vector & 0x08)
+ return "2.5-16GT/s";
+ if (vector & 0x04)
+ return "2.5-8GT/s";
+ if (vector & 0x02)
+ return "2.5-5GT/s";
+ if (vector & 0x01)
+ return "2.5GT/s";
+
+ return "Unknown";
}
static const char *cap_express_link2_speed(int type)
return "8GT/s";
case 4:
return "16GT/s";
+ case 5:
+ return "32GT/s";
+ case 6:
+ return "64GT/s";
default:
return "Unknown";
}
}
}
+static const char *cap_express_link2_compliance_preset(int type)
+{
+ switch (type)
+ {
+ case 0:
+ return "-6dB de-emphasis, 0dB preshoot";
+ case 1:
+ return "-3.5dB de-emphasis, 0dB preshoot";
+ case 2:
+ return "-4.4dB de-emphasis, 0dB preshoot";
+ case 3:
+ return "-2.5dB de-emphasis, 0dB preshoot";
+ case 4:
+ return "0dB de-emphasis, 0dB preshoot";
+ case 5:
+ return "0dB de-emphasis, 1.9dB preshoot";
+ case 6:
+ return "0dB de-emphasis, 2.5dB preshoot";
+ case 7:
+ return "-6.0dB de-emphasis, 3.5dB preshoot";
+ case 8:
+ return "-3.5dB de-emphasis, 3.5dB preshoot";
+ case 9:
+ return "0dB de-emphasis, 3.5dB preshoot";
+ default:
+ return "Unknown";
+ }
+}
+
static const char *cap_express_link2_transmargin(int type)
{
switch (type)
}
}
+static const char *cap_express_link2_crosslink_res(int crosslink)
+{
+ switch (crosslink)
+ {
+ case 0:
+ return "unsupported";
+ case 1:
+ return "Upstream Port";
+ case 2:
+ return "Downstream Port";
+ default:
+ return "incomplete";
+ }
+}
+
+static const char *cap_express_link2_component(int presence)
+{
+ switch (presence)
+ {
+ case 0:
+ return "Link Down - Not Determined";
+ case 1:
+ return "Link Down - Not Present";
+ case 2:
+ return "Link Down - Present";
+ case 4:
+ return "Link Up - Present";
+ case 5:
+ return "Link Up - Present and DRS Received";
+ default:
+ return "Reserved";
+ }
+}
+
static void cap_express_link2(struct device *d, int where, int type)
{
+ u32 l = 0;
u16 w;
if (!((type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_LEG_END) &&
(d->dev->dev != 0 || d->dev->func != 0))) {
+ /* Link Capabilities 2 was reserved before PCIe r3.0 */
+ l = get_conf_long(d, where + PCI_EXP_LNKCAP2);
+ if (l) {
+ printf("\t\tLnkCap2: Supported Link Speeds: %s, Crosslink%c "
+ "Retimer%c 2Retimers%c DRS%c\n",
+ cap_express_link2_speed_cap(PCI_EXP_LNKCAP2_SPEED(l)),
+ FLAG(l, PCI_EXP_LNKCAP2_CROSSLINK),
+ FLAG(l, PCI_EXP_LNKCAP2_RETIMER),
+ FLAG(l, PCI_EXP_LNKCAP2_2RETIMERS),
+ FLAG(l, PCI_EXP_LNKCAP2_DRS));
+ }
+
w = get_conf_word(d, where + PCI_EXP_LNKCTL2);
printf("\t\tLnkCtl2: Target Link Speed: %s, EnterCompliance%c SpeedDis%c",
cap_express_link2_speed(PCI_EXP_LNKCTL2_SPEED(w)),
cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_DEEMPHASIS(w)));
printf("\n"
"\t\t\t Transmit Margin: %s, EnterModifiedCompliance%c ComplianceSOS%c\n"
- "\t\t\t Compliance De-emphasis: %s\n",
+ "\t\t\t Compliance Preset/De-emphasis: %s\n",
cap_express_link2_transmargin(PCI_EXP_LNKCTL2_MARGIN(w)),
FLAG(w, PCI_EXP_LNKCTL2_MOD_CMPLNC),
FLAG(w, PCI_EXP_LNKCTL2_CMPLNC_SOS),
- cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_COM_DEEMPHASIS(w)));
+ cap_express_link2_compliance_preset(PCI_EXP_LNKCTL2_COM_DEEMPHASIS(w)));
}
w = get_conf_word(d, where + PCI_EXP_LNKSTA2);
- printf("\t\tLnkSta2: Current De-emphasis Level: %s, EqualizationComplete%c, EqualizationPhase1%c\n"
- "\t\t\t EqualizationPhase2%c, EqualizationPhase3%c, LinkEqualizationRequest%c\n",
+ printf("\t\tLnkSta2: Current De-emphasis Level: %s, EqualizationComplete%c EqualizationPhase1%c\n"
+ "\t\t\t EqualizationPhase2%c EqualizationPhase3%c LinkEqualizationRequest%c\n"
+ "\t\t\t Retimer%c 2Retimers%c CrosslinkRes: %s",
cap_express_link2_deemphasis(PCI_EXP_LINKSTA2_DEEMPHASIS(w)),
FLAG(w, PCI_EXP_LINKSTA2_EQU_COMP),
FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE1),
FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE2),
FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE3),
- FLAG(w, PCI_EXP_LINKSTA2_EQU_REQ));
+ FLAG(w, PCI_EXP_LINKSTA2_EQU_REQ),
+ FLAG(w, PCI_EXP_LINKSTA2_RETIMER),
+ FLAG(w, PCI_EXP_LINKSTA2_2RETIMERS),
+ cap_express_link2_crosslink_res(PCI_EXP_LINKSTA2_CROSSLINK(w)));
+
+ if (exp_downstream_port(type) && (l & PCI_EXP_LNKCAP2_DRS)) {
+ printf(", DRS%c\n"
+ "\t\t\t DownstreamComp: %s\n",
+ FLAG(w, PCI_EXP_LINKSTA2_DRS_RCVD),
+ cap_express_link2_component(PCI_EXP_LINKSTA2_COMPONENT(w)));
+ } else
+ printf("\n");
}
static void cap_express_slot2(struct device *d UNUSED, int where UNUSED)
default:
printf("Unknown type %d", type);
}
- printf(", MSI %02x\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
+ printf(", IntMsgNum %d\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
if (verbose < 2)
return type;
projects / thirdparty / pciutils.git / blobdiff