return;
l = get_conf_long(d, where + PCI_ERR_UNCOR_STATUS);
- printf("\t\tUESta:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
- "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
+ printf("\t\tUESta:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c MalfTLP%c\n"
+ "\t\t\tECRC%c UnsupReq%c ACSViol%c UncorrIntErr%c BlockedTLP%c AtomicOpBlocked%c TLPBlockedErr%c\n"
+ "\t\t\tPoisonTLPBlocked%c DMWrReqBlocked%c IDECheck%c MisIDETLP%c PCRC_CHECK%c TLPXlatBlocked%c\n",
FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
- FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
+ FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL),
+ FLAG(l, PCI_ERR_UNC_INTERNAL), FLAG(l, PCI_ERR_UNC_MC_BLOCKED_TLP),
+ FLAG(l, PCI_ERR_UNC_ATOMICOP_EGRESS_BLOCKED), FLAG(l, PCI_ERR_UNC_TLP_PREFIX_BLOCKED),
+ FLAG(l, PCI_ERR_UNC_POISONED_TLP_EGRESS), FLAG(l, PCI_ERR_UNC_DMWR_REQ_EGRESS_BLOCKED),
+ FLAG(l, PCI_ERR_UNC_IDE_CHECK), FLAG(l, PCI_ERR_UNC_MISR_IDE_TLP), FLAG(l, PCI_ERR_UNC_PCRC_CHECK),
+ FLAG(l, PCI_ERR_UNC_TLP_XLAT_EGRESS_BLOCKED));
l = get_conf_long(d, where + PCI_ERR_UNCOR_MASK);
- printf("\t\tUEMsk:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
- "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
+ printf("\t\tUEMsk:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c MalfTLP%c\n"
+ "\t\t\tECRC%c UnsupReq%c ACSViol%c UncorrIntErr%c BlockedTLP%c AtomicOpBlocked%c TLPBlockedErr%c\n"
+ "\t\t\tPoisonTLPBlocked%c DMWrReqBlocked%c IDECheck%c MisIDETLP%c PCRC_CHECK%c TLPXlatBlocked%c\n",
FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
- FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
+ FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL),
+ FLAG(l, PCI_ERR_UNC_INTERNAL), FLAG(l, PCI_ERR_UNC_MC_BLOCKED_TLP),
+ FLAG(l, PCI_ERR_UNC_ATOMICOP_EGRESS_BLOCKED), FLAG(l, PCI_ERR_UNC_TLP_PREFIX_BLOCKED),
+ FLAG(l, PCI_ERR_UNC_POISONED_TLP_EGRESS), FLAG(l, PCI_ERR_UNC_DMWR_REQ_EGRESS_BLOCKED),
+ FLAG(l, PCI_ERR_UNC_IDE_CHECK), FLAG(l, PCI_ERR_UNC_MISR_IDE_TLP), FLAG(l, PCI_ERR_UNC_PCRC_CHECK),
+ FLAG(l, PCI_ERR_UNC_TLP_XLAT_EGRESS_BLOCKED));
l = get_conf_long(d, where + PCI_ERR_UNCOR_SEVER);
- printf("\t\tUESvrt:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
- "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
+ printf("\t\tUESvrt:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c MalfTLP%c\n"
+ "\t\t\tECRC%c UnsupReq%c ACSViol%c UncorrIntErr%c BlockedTLP%c AtomicOpBlocked%c TLPBlockedErr%c\n"
+ "\t\t\tPoisonTLPBlocked%c DMWrReqBlocked%c IDECheck%c MisIDETLP%c PCRC_CHECK%c TLPXlatBlocked%c\n",
FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
- FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
+ FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL),
+ FLAG(l, PCI_ERR_UNC_INTERNAL), FLAG(l, PCI_ERR_UNC_MC_BLOCKED_TLP),
+ FLAG(l, PCI_ERR_UNC_ATOMICOP_EGRESS_BLOCKED), FLAG(l, PCI_ERR_UNC_TLP_PREFIX_BLOCKED),
+ FLAG(l, PCI_ERR_UNC_POISONED_TLP_EGRESS), FLAG(l, PCI_ERR_UNC_DMWR_REQ_EGRESS_BLOCKED),
+ FLAG(l, PCI_ERR_UNC_IDE_CHECK), FLAG(l, PCI_ERR_UNC_MISR_IDE_TLP), FLAG(l, PCI_ERR_UNC_PCRC_CHECK),
+ FLAG(l, PCI_ERR_UNC_TLP_XLAT_EGRESS_BLOCKED));
l = get_conf_long(d, where + PCI_ERR_COR_STATUS);
- printf("\t\tCESta:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c AdvNonFatalErr%c\n",
+ printf("\t\tCESta:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c AdvNonFatalErr%c "
+ "CorrIntErr%c HeaderOF%c\n",
FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
- FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE));
+ FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE),
+ FLAG(l, PCI_ERR_COR_INTERNAL), FLAG(l, PCI_ERR_COR_HDRLOG_OVER));
l = get_conf_long(d, where + PCI_ERR_COR_MASK);
- printf("\t\tCEMsk:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c AdvNonFatalErr%c\n",
+ printf("\t\tCEMsk:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c AdvNonFatalErr%c "
+ "CorrIntErr%c HeaderOF%c\n",
FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
- FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE));
+ FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE),
+ FLAG(l, PCI_ERR_COR_INTERNAL), FLAG(l, PCI_ERR_COR_HDRLOG_OVER));
l = get_conf_long(d, where + PCI_ERR_CAP);
printf("\t\tAERCap:\tFirst Error Pointer: %02x, ECRCGenCap%c ECRCGenEn%c ECRCChkCap%c ECRCChkEn%c\n"
"\t\t\tMultHdrRecCap%c MultHdrRecEn%c TLPPfxPres%c HdrLogCap%c\n",
printf("\t\tAssociatedBusNumbers: %02x-%02x\n", nextbusn, lastbusn );
}
+static void
+cap_lmr(struct device *d, int where)
+{
+ printf("Lane Margining at the Receiver\n");
+
+ if (verbose < 2)
+ return;
+
+ if (!config_fetch(d, where, 8))
+ return;
+
+ u16 port_caps = get_conf_word(d, where + PCI_LMR_CAPS);
+ u16 port_status = get_conf_word(d, where + PCI_LMR_PORT_STS);
+
+ printf("\t\tPortCap: Uses Driver%c\n", FLAG(port_caps, PCI_LMR_CAPS_DRVR));
+ printf("\t\tPortSta: MargReady%c MargSoftReady%c\n",
+ FLAG(port_status, PCI_LMR_PORT_STS_READY),
+ FLAG(port_status, PCI_LMR_PORT_STS_SOFT_READY));
+}
+
static void
cxl_range(u64 base, u64 size, int n)
{
FLAG(l, PCI_DOE_STS_OBJECT_READY));
}
+static const char *offstr(char *buf, u32 off)
+{
+ if (verbose < 3)
+ return "";
+
+ sprintf(buf, "[%x]", off);
+ return buf;
+}
+
+static const char *ide_alg(char *buf, size_t len, u32 l)
+{
+ const char *algo[] = { "AES-GCM-256-96b" }; // AES-GCM 256 key size, 96b MAC
+
+ if (l == 0)
+ snprintf(buf, len, "%s", algo[l]);
+ else
+ snprintf(buf, len, "%s", "reserved");
+ return buf;
+}
+
+static void
+cap_ide(struct device *d, int where)
+{
+ const char *hdr_enc_mode[] = { "no", "17:2", "25:2", "33:2", "41:2" };
+ const char *stream_state[] = { "insecure", "reserved", "secure" };
+ const char *aggr[] = { "-", "=2", "=4", "=8" };
+ u32 l, l2, linknum = 0, selnum = 0, addrnum, off, i, j;
+ char buf1[16], buf2[16], offs[16];
+
+ printf("Integrity & Data Encryption\n");
+
+ if (verbose < 2)
+ return;
+
+ if (!config_fetch(d, where + PCI_IDE_CAP, 8))
+ {
+ printf("\t\t<unreadable>\n");
+ return;
+ }
+
+ l = get_conf_long(d, where + PCI_IDE_CAP);
+ if (l & PCI_IDE_CAP_LINK_IDE_SUPP)
+ linknum = PCI_IDE_CAP_LINK_TC_NUM(l) + 1;
+ if (l & PCI_IDE_CAP_SELECTIVE_IDE_SUPP)
+ selnum = PCI_IDE_CAP_SELECTIVE_STREAMS_NUM(l) + 1;
+
+ printf("\t\tIDECap: Lnk=%d Sel=%d FlowThru%c PartHdr%c Aggr%c PCPC%c IDE_KM%c Alg='%s' TCs=%d TeeLim%c\n",
+ linknum,
+ selnum,
+ FLAG(l, PCI_IDE_CAP_FLOWTHROUGH_IDE_SUPP),
+ FLAG(l, PCI_IDE_CAP_PARTIAL_HEADER_ENC_SUPP),
+ FLAG(l, PCI_IDE_CAP_AGGREGATION_SUPP),
+ FLAG(l, PCI_IDE_CAP_PCRC_SUPP),
+ FLAG(l, PCI_IDE_CAP_IDE_KM_SUPP),
+ ide_alg(buf2, sizeof(buf2), PCI_IDE_CAP_ALG(l)),
+ PCI_IDE_CAP_LINK_TC_NUM(l) + 1,
+ FLAG(l, PCI_IDE_CAP_TEE_LIMITED_SUPP)
+ );
+
+ l = get_conf_long(d, where + PCI_IDE_CTL);
+ printf("\t\tIDECtl: FTEn%c\n",
+ FLAG(l, PCI_IDE_CTL_FLOWTHROUGH_IDE));
+
+ // The rest of the capability is variable length arrays
+ off = where + PCI_IDE_LINK_STREAM;
+
+ // Link IDE Register Block repeated 0 to 8 times
+ if (linknum)
+ {
+ if (!config_fetch(d, off, 8 * linknum))
+ {
+ printf("\t\t<unreadable>\n");
+ return;
+ }
+ for (i = 0; i < linknum; ++i)
+ {
+ // Link IDE Stream Control Register
+ l = get_conf_long(d, off);
+ printf("\t\t%sLinkIDE#%d Ctl: En%c NPR%s PR%s CPL%s PCRC%c HdrEnc=%s Alg='%s' TC%d ID%d\n",
+ offstr(offs, off),
+ i,
+ FLAG(l, PCI_IDE_LINK_CTL_EN),
+ aggr[PCI_IDE_LINK_CTL_TX_AGGR_NPR(l)],
+ aggr[PCI_IDE_LINK_CTL_TX_AGGR_PR(l)],
+ aggr[PCI_IDE_LINK_CTL_TX_AGGR_CPL(l)],
+ FLAG(l, PCI_IDE_LINK_CTL_EN),
+ TABLE(hdr_enc_mode, PCI_IDE_LINK_CTL_PART_ENC(l), buf1),
+ ide_alg(buf2, sizeof(buf2), PCI_IDE_LINK_CTL_ALG(l)),
+ PCI_IDE_LINK_CTL_TC(l),
+ PCI_IDE_LINK_CTL_ID(l)
+ );
+ off += 4;
+
+ /* Link IDE Stream Status Register */
+ l = get_conf_long(d, off);
+ printf("\t\t%sLinkIDE#%d Sta: Status=%s RecvChkFail%c\n",
+ offstr(offs, off),
+ i,
+ TABLE(stream_state, PCI_IDE_LINK_STS_STATUS(l), buf1),
+ FLAG(l, PCI_IDE_LINK_STS_RECVD_INTEGRITY_CHECK));
+ off += 4;
+ }
+ }
+
+ for (i = 0; i < selnum; ++i)
+ {
+ // Fetching Selective IDE Stream Capability/Control/Status/RID1/RID2
+ if (!config_fetch(d, off, 20))
+ {
+ printf("\t\t<unreadable>\n");
+ return;
+ }
+
+ // Selective IDE Stream Capability Register
+ l = get_conf_long(d, off);
+ printf("\t\t%sSelectiveIDE#%d Cap: RID#=%d\n",
+ offstr(offs, off),
+ i,
+ PCI_IDE_SEL_CAP_BLOCKS_NUM(l));
+ off += 4;
+ addrnum = PCI_IDE_SEL_CAP_BLOCKS_NUM(l);
+
+ // Selective IDE Stream Control Register
+ l = get_conf_long(d, off);
+
+ printf("\t\t%sSelectiveIDE#%d Ctl: En%c NPR%s PR%s CPL%s PCRC%c CFG%c HdrEnc=%s Alg='%s' TC%d ID%d%s\n",
+ offstr(offs, off),
+ i,
+ FLAG(l, PCI_IDE_SEL_CTL_EN),
+ aggr[PCI_IDE_SEL_CTL_TX_AGGR_NPR(l)],
+ aggr[PCI_IDE_SEL_CTL_TX_AGGR_PR(l)],
+ aggr[PCI_IDE_SEL_CTL_TX_AGGR_CPL(l)],
+ FLAG(l, PCI_IDE_SEL_CTL_PCRC_EN),
+ FLAG(l, PCI_IDE_SEL_CTL_CFG_EN),
+ TABLE(hdr_enc_mode, PCI_IDE_SEL_CTL_PART_ENC(l), buf1),
+ ide_alg(buf2, sizeof(buf2), PCI_IDE_SEL_CTL_ALG(l)),
+ PCI_IDE_SEL_CTL_TC(l),
+ PCI_IDE_SEL_CTL_ID(l),
+ (l & PCI_IDE_SEL_CTL_DEFAULT) ? " Default" : ""
+ );
+ off += 4;
+
+ // Selective IDE Stream Status Register
+ l = get_conf_long(d, off);
+ printf("\t\t%sSelectiveIDE#%d Sta: %s RecvChkFail%c\n",
+ offstr(offs, off),
+ i ,
+ TABLE(stream_state, PCI_IDE_SEL_STS_STATUS(l), buf1),
+ FLAG(l, PCI_IDE_SEL_STS_RECVD_INTEGRITY_CHECK));
+ off += 4;
+
+ // IDE RID Association Registers
+ l = get_conf_long(d, off);
+ l2 = get_conf_long(d, off + 4);
+
+ printf("\t\t%sSelectiveIDE#%d RID: Valid%c Base=%x Limit=%x SegBase=%x\n",
+ offstr(offs, off),
+ i,
+ FLAG(l2, PCI_IDE_SEL_RID_2_VALID),
+ PCI_IDE_SEL_RID_2_BASE(l2),
+ PCI_IDE_SEL_RID_1_LIMIT(l),
+ PCI_IDE_SEL_RID_2_SEG_BASE(l2));
+ off += 8;
+
+ if (!config_fetch(d, off, addrnum * 12))
+ {
+ printf("\t\t<unreadable>\n");
+ return;
+ }
+
+ // IDE Address Association Registers
+ for (j = 0; j < addrnum; ++j)
+ {
+ u64 limit, base;
+
+ l = get_conf_long(d, off);
+ limit = get_conf_long(d, off + 4);
+ limit <<= 32;
+ limit |= (PCI_IDE_SEL_ADDR_1_LIMIT_LOW(l) << 20) | 0xFFFFF;
+ base = get_conf_long(d, off + 8);
+ base <<= 32;
+ base |= PCI_IDE_SEL_ADDR_1_BASE_LOW(l) << 20;
+ printf("\t\t%sSelectiveIDE#%d RID#%d: Valid%c Base=%lx Limit=%lx\n",
+ offstr(offs, off),
+ i,
+ j,
+ FLAG(l, PCI_IDE_SEL_ADDR_1_VALID),
+ base,
+ limit);
+ off += 12;
+ }
+ }
+}
+
void
show_ext_caps(struct device *d, int type)
{
printf("Physical Layer 16.0 GT/s <?>\n");
break;
case PCI_EXT_CAP_ID_LMR:
- printf("Lane Margining at the Receiver <?>\n");
+ cap_lmr(d, where);
break;
case PCI_EXT_CAP_ID_HIER_ID:
printf("Hierarchy ID <?>\n");
case PCI_EXT_CAP_ID_DOE:
cap_doe(d, where);
break;
+ case PCI_EXT_CAP_ID_IDE:
+ cap_ide(d, where);
+ break;
default:
printf("Extended Capability ID %#02x\n", id);
break;
projects / thirdparty / pciutils.git / blobdiff