#define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel */
#define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */
#define PCI_EXT_CAP_ID_PB 0x04 /* Power Budgeting */
+#define PCI_EXT_CAP_ID_RCLINK 0x05 /* Root Complex Link Declaration */
+#define PCI_EXT_CAP_ID_RCILINK 0x06 /* Root Complex Internal Link Declaration */
+#define PCI_EXT_CAP_ID_RCECOLL 0x07 /* Root Complex Event Collector */
+#define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function Virtual Channel */
+#define PCI_EXT_CAP_ID_RBCB 0x0a /* Root Bridge Control Block */
+#define PCI_EXT_CAP_ID_VNDR 0x0b /* Vendor specific */
+#define PCI_EXT_CAP_ID_ACS 0x0d /* Access Controls */
/* Power Management Registers */
#define PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
#define PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */
#define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
+#define PCI_EXP_DEVCAP_RBE 0x8000 /* Role-Based Error Reporting */
#define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
#define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
+#define PCI_EXP_DEVCAP_FLRESET 0x10000000 /* Function-Level Reset */
#define PCI_EXP_DEVCTL 0x8 /* Device Control */
#define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */
#define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
#define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
#define PCI_EXP_DEVCTL_NOSNOOP 0x0800 /* Enable No Snoop */
#define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
+#define PCI_EXP_DEVCTL_BCRE 0x8000 /* Bridge Configuration Retry Enable */
+#define PCI_EXP_DEVCTL_FLRESET 0x8000 /* Function-Level Reset [bit shared with BCRE] */
#define PCI_EXP_DEVSTA 0xa /* Device Status */
#define PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
#define PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
#define PCI_EXP_LNKCAP_ASPM 0x00c00 /* Active State Power Management */
#define PCI_EXP_LNKCAP_L0S 0x07000 /* L0s Acceptable Latency */
#define PCI_EXP_LNKCAP_L1 0x38000 /* L1 Acceptable Latency */
+#define PCI_EXP_LNKCAP_CLOCKPM 0x40000 /* Clock Power Management */
+#define PCI_EXP_LNKCAP_SURPRISE 0x80000 /* Surprise Down Error Reporting */
+#define PCI_EXP_LNKCAP_DLLA 0x100000 /* Data Link Layer Active Reporting */
+#define PCI_EXP_LNKCAP_LBNC 0x200000 /* Link Bandwidth Notification Capability */
#define PCI_EXP_LNKCAP_PORT 0xff000000 /* Port Number */
#define PCI_EXP_LNKCTL 0x10 /* Link Control */
#define PCI_EXP_LNKCTL_ASPM 0x0003 /* ASPM Control */
#define PCI_EXP_LNKCTL_RETRAIN 0x0020 /* Retrain Link */
#define PCI_EXP_LNKCTL_CLOCK 0x0040 /* Common Clock Configuration */
#define PCI_EXP_LNKCTL_XSYNCH 0x0080 /* Extended Synch */
+#define PCI_EXP_LNKCTL_CLOCKPM 0x0100 /* Clock Power Management */
+#define PCI_EXP_LNKCTL_HWAUTWD 0x0200 /* Hardware Autonomous Width Disable */
+#define PCI_EXP_LNKCTL_BWMIE 0x0400 /* Bandwidth Mgmt Interrupt Enable */
+#define PCI_EXP_LNKCTL_AUTBWIE 0x0800 /* Autonomous Bandwidth Mgmt Interrupt Enable */
#define PCI_EXP_LNKSTA 0x12 /* Link Status */
#define PCI_EXP_LNKSTA_SPEED 0x000f /* Negotiated Link Speed */
#define PCI_EXP_LNKSTA_WIDTH 0x03f0 /* Negotiated Link Width */
-#define PCI_EXP_LNKSTA_TR_ERR 0x0400 /* Training Error */
+#define PCI_EXP_LNKSTA_TR_ERR 0x0400 /* Training Error (obsolete) */
#define PCI_EXP_LNKSTA_TRAIN 0x0800 /* Link Training */
#define PCI_EXP_LNKSTA_SL_CLK 0x1000 /* Slot Clock Configuration */
+#define PCI_EXP_LNKSTA_DL_ACT 0x2000 /* Data Link Layer in DL_Active State */
+#define PCI_EXP_LNKSTA_BWMGMT 0x4000 /* Bandwidth Mgmt Status */
+#define PCI_EXP_LNKSTA_AUTBW 0x8000 /* Autonomous Bandwidth Mgmt Status */
#define PCI_EXP_SLTCAP 0x14 /* Slot Capabilities */
#define PCI_EXP_SLTCAP_ATNB 0x0001 /* Attention Button Present */
#define PCI_EXP_SLTCAP_PWRC 0x0002 /* Power Controller Present */
#define PCI_EXP_SLTCAP_HPC 0x0040 /* Hot-Plug Capable */
#define PCI_EXP_SLTCAP_PWR_VAL 0x00007f80 /* Slot Power Limit Value */
#define PCI_EXP_SLTCAP_PWR_SCL 0x00018000 /* Slot Power Limit Scale */
+#define PCI_EXP_SLTCAP_INTERLOCK 0x020000 /* Electromechanical Interlock Present */
+#define PCI_EXP_SLTCAP_NOCMDCOMP 0x040000 /* No Command Completed Support */
#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
#define PCI_EXP_SLTCTL 0x18 /* Slot Control */
#define PCI_EXP_SLTCTL_ATNB 0x0001 /* Attention Button Pressed Enable */
#define PCI_EXP_SLTCTL_PRSD 0x0008 /* Presence Detect Changed Enable */
#define PCI_EXP_SLTCTL_CMDC 0x0010 /* Command Completed Interrupt Enable */
#define PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */
-#define PCI_EXP_SLTCTL_ATNI 0x00C0 /* Attention Indicator Control */
+#define PCI_EXP_SLTCTL_ATNI 0x00c0 /* Attention Indicator Control */
#define PCI_EXP_SLTCTL_PWRI 0x0300 /* Power Indicator Control */
#define PCI_EXP_SLTCTL_PWRC 0x0400 /* Power Controller Control */
+#define PCI_EXP_SLTCTL_INTERLOCK 0x0800 /* Electromechanical Interlock Control */
+#define PCI_EXP_SLTCTL_LLCHG 0x1000 /* Data Link Layer State Changed Enable */
#define PCI_EXP_SLTSTA 0x1a /* Slot Status */
+#define PCI_EXP_SLTSTA_ATNB 0x0001 /* Attention Button Pressed */
+#define PCI_EXP_SLTSTA_PWRF 0x0002 /* Power Fault Detected */
+#define PCI_EXP_SLTSTA_MRLS 0x0004 /* MRL Sensor Changed */
+#define PCI_EXP_SLTSTA_PRSD 0x0008 /* Presence Detect Changed */
+#define PCI_EXP_SLTSTA_CMDC 0x0010 /* Command Completed */
+#define PCI_EXP_SLTSTA_MRL_ST 0x0020 /* MRL Sensor State */
+#define PCI_EXP_SLTSTA_PRES 0x0040 /* Presence Detect State */
+#define PCI_EXP_SLTSTA_INTERLOCK 0x0080 /* Electromechanical Interlock Status */
+#define PCI_EXP_SLTSTA_LLCHG 0x0100 /* Data Link Layer State Changed */
#define PCI_EXP_RTCTL 0x1c /* Root Control */
-#define PCI_EXP_RTCTL_SECEE 0x1 /* System Error on Correctable Error */
-#define PCI_EXP_RTCTL_SENFEE 0x1 /* System Error on Non-Fatal Error */
-#define PCI_EXP_RTCTL_SEFEE 0x1 /* System Error on Fatal Error */
-#define PCI_EXP_RTCTL_PMEIE 0x1 /* PME Interrupt Enable */
+#define PCI_EXP_RTCTL_SECEE 0x0001 /* System Error on Correctable Error */
+#define PCI_EXP_RTCTL_SENFEE 0x0002 /* System Error on Non-Fatal Error */
+#define PCI_EXP_RTCTL_SEFEE 0x0004 /* System Error on Fatal Error */
+#define PCI_EXP_RTCTL_PMEIE 0x0008 /* PME Interrupt Enable */
+#define PCI_EXP_RTCTL_CRSVIS 0x0010 /* Configuration Request Retry Status Visible to SW */
+#define PCI_EXP_RTCAP 0x1e /* Root Capabilities */
+#define PCI_EXP_RTCAP_CRSVIS 0x0010 /* Configuration Request Retry Status Visible to SW */
#define PCI_EXP_RTSTA 0x20 /* Root Status */
+#define PCI_EXP_RTSTA_PME_REQID 0x0000ffff /* PME Requester ID */
+#define PCI_EXP_RTSTA_PME_STATUS 0x00010000 /* PME Status */
+#define PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending */
/* MSI-X */
#define PCI_MSIX_ENABLE 0x8000
u16 w;
t = get_conf_long(d, where + PCI_EXP_DEVCAP);
- printf("\t\tDevice: Supported: MaxPayload %d bytes, PhantFunc %d, ExtTag%c\n",
+ printf("\t\tDevCap:\tMaxPayload %d bytes, PhantFunc %d, Latency L0s %s, L1 %s\n",
128 << (t & PCI_EXP_DEVCAP_PAYLOAD),
(1 << ((t & PCI_EXP_DEVCAP_PHANTOM) >> 3)) - 1,
- FLAG(t, PCI_EXP_DEVCAP_EXT_TAG));
- printf("\t\tDevice: Latency L0s %s, L1 %s\n",
latency_l0s((t & PCI_EXP_DEVCAP_L0S) >> 6),
latency_l1((t & PCI_EXP_DEVCAP_L1) >> 9));
+ printf("\t\t\tExtTag%c", FLAG(t, PCI_EXP_DEVCAP_EXT_TAG));
if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) ||
(type == PCI_EXP_TYPE_UPSTREAM) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
- printf("\t\tDevice: AtnBtn%c AtnInd%c PwrInd%c\n",
+ printf(" AttnBtn%c AttnInd%c PwrInd%c",
FLAG(t, PCI_EXP_DEVCAP_ATN_BUT),
FLAG(t, PCI_EXP_DEVCAP_ATN_IND), FLAG(t, PCI_EXP_DEVCAP_PWR_IND));
+ printf(" RBE%c FLReset%c",
+ FLAG(t, PCI_EXP_DEVCAP_RBE),
+ FLAG(t, PCI_EXP_DEVCAP_FLRESET));
if (type == PCI_EXP_TYPE_UPSTREAM)
- printf("\t\tDevice: SlotPowerLimit %f\n",
+ printf("SlotPowerLimit %fW",
power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18,
(t & PCI_EXP_DEVCAP_PWR_SCL) >> 26));
+ printf("\n");
w = get_conf_word(d, where + PCI_EXP_DEVCTL);
- printf("\t\tDevice: Errors: Correctable%c Non-Fatal%c Fatal%c Unsupported%c\n",
+ printf("\t\tDevCtl:\tReport errors: Correctable%c Non-Fatal%c Fatal%c Unsupported%c\n",
FLAG(w, PCI_EXP_DEVCTL_CERE),
FLAG(w, PCI_EXP_DEVCTL_NFERE),
FLAG(w, PCI_EXP_DEVCTL_FERE),
FLAG(w, PCI_EXP_DEVCTL_URRE));
- printf("\t\tDevice: RlxdOrd%c ExtTag%c PhantFunc%c AuxPwr%c NoSnoop%c\n",
+ printf("\t\t\tRlxdOrd%c ExtTag%c PhantFunc%c AuxPwr%c NoSnoop%c",
FLAG(w, PCI_EXP_DEVCTL_RELAXED),
FLAG(w, PCI_EXP_DEVCTL_EXT_TAG),
FLAG(w, PCI_EXP_DEVCTL_PHANTOM),
FLAG(w, PCI_EXP_DEVCTL_AUX_PME),
FLAG(w, PCI_EXP_DEVCTL_NOSNOOP));
- printf("\t\tDevice: MaxPayload %d bytes, MaxReadReq %d bytes\n",
+ if (type == PCI_EXP_TYPE_PCI_BRIDGE || type == PCI_EXP_TYPE_PCIE_BRIDGE)
+ printf(" BrConfRtry%c", FLAG(w, PCI_EXP_DEVCTL_BCRE));
+ if (type == PCI_EXP_TYPE_ENDPOINT && (t & PCI_EXP_DEVCAP_FLRESET))
+ printf(" FLReset%c", FLAG(w, PCI_EXP_DEVCTL_FLRESET));
+ printf("\n\t\t\tMaxPayload %d bytes, MaxReadReq %d bytes\n",
128 << ((w & PCI_EXP_DEVCTL_PAYLOAD) >> 5),
128 << ((w & PCI_EXP_DEVCTL_READRQ) >> 12));
+
+ w = get_conf_word(d, where + PCI_EXP_DEVSTA);
+ printf("\t\tDevSta:\tCorrErr%c UncorrErr%c FatalErr%c UnsuppReq%c AuxPwr%c TransPend%c\n",
+ FLAG(w, PCI_EXP_DEVSTA_CED),
+ FLAG(w, PCI_EXP_DEVSTA_NFED),
+ FLAG(w, PCI_EXP_DEVSTA_FED),
+ FLAG(w, PCI_EXP_DEVSTA_URD),
+ FLAG(w, PCI_EXP_DEVSTA_AUXPD),
+ FLAG(w, PCI_EXP_DEVSTA_TRPND));
+
+ /* FIXME: Second set of control/status registers is not supported yet. */
}
static char *link_speed(int speed)
switch (speed)
{
case 1:
- return "2.5Gb/s";
+ return "2.5GT/s";
+ case 2:
+ return "5GT/s";
default:
return "unknown";
}
u16 w;
t = get_conf_long(d, where + PCI_EXP_LNKCAP);
- printf("\t\tLink: Supported Speed %s, Width x%d, ASPM %s, Port %d\n",
+ printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s, Latency L0 %s, L1 %s\n",
+ t >> 24,
link_speed(t & PCI_EXP_LNKCAP_SPEED), (t & PCI_EXP_LNKCAP_WIDTH) >> 4,
aspm_support((t & PCI_EXP_LNKCAP_ASPM) >> 10),
- t >> 24);
- printf("\t\tLink: Latency L0s %s, L1 %s\n",
latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12),
latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
+ printf("\t\t\tClockPM%c Suprise%c LLActRep%c BwNot%c\n",
+ FLAG(t, PCI_EXP_LNKCAP_CLOCKPM),
+ FLAG(t, PCI_EXP_LNKCAP_SURPRISE),
+ FLAG(t, PCI_EXP_LNKCAP_DLLA),
+ FLAG(t, PCI_EXP_LNKCAP_LBNC));
+
w = get_conf_word(d, where + PCI_EXP_LNKCTL);
- printf("\t\tLink: ASPM %s", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM));
+ printf("\t\tLnkCtl:\tASPM %s;", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM));
if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) ||
(type == PCI_EXP_TYPE_LEG_END))
printf(" RCB %d bytes", w & PCI_EXP_LNKCTL_RCB ? 128 : 64);
- if (w & PCI_EXP_LNKCTL_DISABLE)
- printf(" Disabled");
- printf(" CommClk%c ExtSynch%c\n", FLAG(w, PCI_EXP_LNKCTL_CLOCK),
- FLAG(w, PCI_EXP_LNKCTL_XSYNCH));
+ printf(" Disabled%c Retrain%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n",
+ FLAG(w, PCI_EXP_LNKCTL_DISABLE),
+ FLAG(w, PCI_EXP_LNKCTL_RETRAIN),
+ FLAG(w, PCI_EXP_LNKCTL_CLOCK),
+ FLAG(w, PCI_EXP_LNKCTL_XSYNCH),
+ FLAG(w, PCI_EXP_LNKCTL_CLOCKPM),
+ FLAG(w, PCI_EXP_LNKCTL_HWAUTWD),
+ FLAG(w, PCI_EXP_LNKCTL_BWMIE),
+ FLAG(w, PCI_EXP_LNKCTL_AUTBWIE));
+
w = get_conf_word(d, where + PCI_EXP_LNKSTA);
- printf("\t\tLink: Speed %s, Width x%d\n",
- link_speed(w & PCI_EXP_LNKSTA_SPEED), (w & PCI_EXP_LNKSTA_WIDTH) >> 4);
+ printf("\t\tLnkSta:\tSpeed %s, Width x%d, TrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n",
+ link_speed(w & PCI_EXP_LNKSTA_SPEED),
+ (w & PCI_EXP_LNKSTA_WIDTH) >> 4,
+ FLAG(w, PCI_EXP_LNKSTA_TR_ERR),
+ FLAG(w, PCI_EXP_LNKSTA_TRAIN),
+ FLAG(w, PCI_EXP_LNKSTA_SL_CLK),
+ FLAG(w, PCI_EXP_LNKSTA_DL_ACT),
+ FLAG(w, PCI_EXP_LNKSTA_BWMGMT),
+ FLAG(w, PCI_EXP_LNKSTA_AUTBW));
}
static const char *indicator(int code)
u16 w;
t = get_conf_long(d, where + PCI_EXP_SLTCAP);
- printf("\t\tSlot: AtnBtn%c PwrCtrl%c MRL%c AtnInd%c PwrInd%c HotPlug%c Surpise%c\n",
+ printf("\t\tSltCap:\tAttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surpise%c\n",
FLAG(t, PCI_EXP_SLTCAP_ATNB),
FLAG(t, PCI_EXP_SLTCAP_PWRC),
FLAG(t, PCI_EXP_SLTCAP_MRL),
FLAG(t, PCI_EXP_SLTCAP_PWRI),
FLAG(t, PCI_EXP_SLTCAP_HPC),
FLAG(t, PCI_EXP_SLTCAP_HPS));
- printf("\t\tSlot: Number %d, PowerLimit %f\n", t >> 19,
- power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7,
- (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15));
+ printf("\t\t\tSlot #%3x, PowerLimit %f; Interlock%c NoCompl%c\n",
+ t >> 19,
+ power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7, (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15),
+ FLAG(t, PCI_EXP_SLTCAP_INTERLOCK),
+ FLAG(t, PCI_EXP_SLTCAP_NOCMDCOMP));
+
w = get_conf_word(d, where + PCI_EXP_SLTCTL);
- printf("\t\tSlot: Enabled AtnBtn%c PwrFlt%c MRL%c PresDet%c CmdCplt%c HPIrq%c\n",
+ printf("\t\tSltCtl:\tEnable: AttnBtn%c PwrFlt%c MRL%c PresDet%c CmdCplt%c HPIrq%c LinkChg%c\n",
FLAG(w, PCI_EXP_SLTCTL_ATNB),
FLAG(w, PCI_EXP_SLTCTL_PWRF),
FLAG(w, PCI_EXP_SLTCTL_MRLS),
FLAG(w, PCI_EXP_SLTCTL_PRSD),
FLAG(w, PCI_EXP_SLTCTL_CMDC),
- FLAG(w, PCI_EXP_SLTCTL_HPIE));
- printf("\t\tSlot: AttnInd %s, PwrInd %s, Power%c\n",
+ FLAG(w, PCI_EXP_SLTCTL_HPIE),
+ FLAG(w, PCI_EXP_SLTCTL_LLCHG));
+ printf("\t\t\tControl: AttnInd %s, PwrInd %s, Power%c Interlock%c\n",
indicator((w & PCI_EXP_SLTCTL_ATNI) >> 6),
indicator((w & PCI_EXP_SLTCTL_PWRI) >> 8),
- FLAG(w, w & PCI_EXP_SLTCTL_PWRC));
+ FLAG(w, PCI_EXP_SLTCTL_PWRC),
+ FLAG(w, PCI_EXP_SLTCTL_INTERLOCK));
+
+ w = get_conf_word(d, where + PCI_EXP_SLTSTA);
+ printf("\t\tSltSta:\tStatus: AttnBtn%c PowerFlt%c MRL%c CmdCplt%c PresDet%c Interlock%c\n",
+ FLAG(w, PCI_EXP_SLTSTA_ATNB),
+ FLAG(w, PCI_EXP_SLTSTA_PWRF),
+ FLAG(w, PCI_EXP_SLTSTA_MRL_ST),
+ FLAG(w, PCI_EXP_SLTSTA_CMDC),
+ FLAG(w, PCI_EXP_SLTSTA_PRES),
+ FLAG(w, PCI_EXP_SLTSTA_INTERLOCK));
+ printf("\t\t\tChanged: MRL%c PresDet%c LinkState%c\n",
+ FLAG(w, PCI_EXP_SLTSTA_MRLS),
+ FLAG(w, PCI_EXP_SLTSTA_PRSD),
+ FLAG(w, PCI_EXP_SLTSTA_LLCHG));
}
static void show_express_root(struct device *d, int where)
{
- u16 w = get_conf_word(d, where + PCI_EXP_RTCTL);
- printf("\t\tRoot: Correctable%c Non-Fatal%c Fatal%c PME%c\n",
+ u32 w = get_conf_word(d, where + PCI_EXP_RTCTL);
+ printf("\t\tRootCtl: ErrCorrectable%c ErrNon-Fatal%c ErrFatal%c PMEIntEna%c CRSVisible%c\n",
FLAG(w, PCI_EXP_RTCTL_SECEE),
FLAG(w, PCI_EXP_RTCTL_SENFEE),
FLAG(w, PCI_EXP_RTCTL_SEFEE),
- FLAG(w, PCI_EXP_RTCTL_PMEIE));
+ FLAG(w, PCI_EXP_RTCTL_PMEIE),
+ FLAG(w, PCI_EXP_RTCTL_CRSVIS));
+
+ w = get_conf_word(d, where + PCI_EXP_RTCAP);
+ printf("\t\tRootCap: CRSVisible%c\n",
+ FLAG(w, PCI_EXP_RTCAP_CRSVIS));
+
+ w = get_conf_word(d, where + PCI_EXP_RTSTA);
+ printf("\t\tRootSta: PME ReqID %04x, PMEStatus%c PMEPending%c\n",
+ w & PCI_EXP_RTSTA_PME_REQID,
+ FLAG(w, PCI_EXP_RTSTA_PME_STATUS),
+ FLAG(w, PCI_EXP_RTSTA_PME_PENDING));
}
static void
default:
printf("Unknown type %d", type);
}
- printf(" IRQ %d\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
+ printf(", MSI %02x\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
if (verbose < 2)
return;
d->dev->vendor_id, d->dev->device_id, subsys_v, subsys_d));
}
-static void
-show_aer(struct device *d UNUSED, int where UNUSED)
-{
- printf("Advanced Error Reporting\n");
-}
-
-static void
-show_vc(struct device *d UNUSED, int where UNUSED)
-{
- printf("Virtual Channel\n");
-}
-
static void
show_dsn(struct device *d, int where)
{
t2 & 0xff, (t2 >> 8) & 0xff, (t2 >> 16) & 0xff, t2 >> 24);
}
-static void
-show_pb(struct device *d UNUSED, int where UNUSED)
-{
- printf("Power Budgeting\n");
-}
-
static void
show_ext_caps(struct device *d)
{
switch (id)
{
case PCI_EXT_CAP_ID_AER:
- show_aer(d, where);
+ printf("Advanced Error Reporting\n");
+ /* FIXME: Not decoded yet */
break;
case PCI_EXT_CAP_ID_VC:
- show_vc(d, where);
+ printf("Virtual Channel\n");
+ /* FIXME: Not decoded yet */
break;
case PCI_EXT_CAP_ID_DSN:
show_dsn(d, where);
break;
case PCI_EXT_CAP_ID_PB:
- show_pb(d, where);
+ printf("Power Budgeting\n");
+ /* FIXME: Not decoded yet */
+ break;
+ case PCI_EXT_CAP_ID_RCLINK:
+ printf("Root Complex Link\n");
+ /* FIXME: Not decoded yet */
+ break;
+ case PCI_EXT_CAP_ID_RCILINK:
+ printf("Root Complex Internal Link\n");
+ /* FIXME: Not decoded yet */
+ break;
+ case PCI_EXT_CAP_ID_RCECOLL:
+ printf("Root Complex Event Collector\n");
+ /* FIXME: Not decoded yet */
+ break;
+ case PCI_EXT_CAP_ID_MFVC:
+ printf("Multi-Function Virtual Channel\n");
+ /* FIXME: Not decoded yet */
+ break;
+ case PCI_EXT_CAP_ID_RBCB:
+ printf("Root Bridge Control Block\n");
+ /* FIXME: Not decoded yet */
+ break;
+ case PCI_EXT_CAP_ID_VNDR:
+ printf("Vendor specific\n");
+ break;
+ case PCI_EXT_CAP_ID_ACS:
+ printf("Access Controls\n");
+ /* FIXME: Not decoded yet */
break;
default:
- printf("Unknown (%d)\n", id);
+ printf("#%02x\n", id);
break;
}
where = header >> 20;
projects / thirdparty / pciutils.git / commitdiff
