target-mips: Streamline indexed cp1 memory addressing.

We've already eliminated both base and index being zero.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
(cherry picked from commit 05168674505153a641c7bfddb691d2eda11d13d1)

Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 7687566e8f9545d5ae30bf430bb98c3246eae52c..cb6077d8066b6ded3fe57db772e49359d6a85fad 100644 (file)
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -7742,8 +7742,7 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
     } else if (index == 0) {
         gen_load_gpr(t0, base);
     } else {
-        gen_load_gpr(t0, index);
-        gen_op_addr_add(ctx, t0, cpu_gpr[base], t0);
+        gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[index]);
     }
     /* Don't do NOP if destination is zero: we must perform the actual
        memory access. */