[thirdparty/u-boot.git] / board / xilinx / zynqmp / zynqmp.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2014 - 2015 Xilinx, Inc.
 * Michal Simek <michal.simek@xilinx.com>
 */

#include <common.h>
#include <sata.h>
#include <ahci.h>
#include <scsi.h>
#include <malloc.h>
#include <wdt.h>
#include <asm/arch/clk.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/psu_init_gpl.h>
#include <asm/io.h>
#include <dm/uclass.h>
#include <usb.h>
#include <dwc3-uboot.h>
#include <zynqmppl.h>
#include <i2c.h>
#include <g_dnl.h>

DECLARE_GLOBAL_DATA_PTR;

#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
static struct udevice *watchdog_dev;
#endif

#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
    !defined(CONFIG_SPL_BUILD)
static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;

static const struct {
	u32 id;
	u32 ver;
	char *name;
	bool evexists;
} zynqmp_devices[] = {
	{
		.id = 0x10,
		.name = "3eg",
	},
	{
		.id = 0x10,
		.ver = 0x2c,
		.name = "3cg",
	},
	{
		.id = 0x11,
		.name = "2eg",
	},
	{
		.id = 0x11,
		.ver = 0x2c,
		.name = "2cg",
	},
	{
		.id = 0x20,
		.name = "5ev",
		.evexists = 1,
	},
	{
		.id = 0x20,
		.ver = 0x100,
		.name = "5eg",
		.evexists = 1,
	},
	{
		.id = 0x20,
		.ver = 0x12c,
		.name = "5cg",
	},
	{
		.id = 0x21,
		.name = "4ev",
		.evexists = 1,
	},
	{
		.id = 0x21,
		.ver = 0x100,
		.name = "4eg",
		.evexists = 1,
	},
	{
		.id = 0x21,
		.ver = 0x12c,
		.name = "4cg",
	},
	{
		.id = 0x30,
		.name = "7ev",
		.evexists = 1,
	},
	{
		.id = 0x30,
		.ver = 0x100,
		.name = "7eg",
		.evexists = 1,
	},
	{
		.id = 0x30,
		.ver = 0x12c,
		.name = "7cg",
	},
	{
		.id = 0x38,
		.name = "9eg",
	},
	{
		.id = 0x38,
		.ver = 0x2c,
		.name = "9cg",
	},
	{
		.id = 0x39,
		.name = "6eg",
	},
	{
		.id = 0x39,
		.ver = 0x2c,
		.name = "6cg",
	},
	{
		.id = 0x40,
		.name = "11eg",
	},
	{ /* For testing purpose only */
		.id = 0x50,
		.ver = 0x2c,
		.name = "15cg",
	},
	{
		.id = 0x50,
		.name = "15eg",
	},
	{
		.id = 0x58,
		.name = "19eg",
	},
	{
		.id = 0x59,
		.name = "17eg",
	},
	{
		.id = 0x61,
		.name = "21dr",
	},
	{
		.id = 0x63,
		.name = "23dr",
	},
	{
		.id = 0x65,
		.name = "25dr",
	},
	{
		.id = 0x64,
		.name = "27dr",
	},
	{
		.id = 0x60,
		.name = "28dr",
	},
	{
		.id = 0x62,
		.name = "29dr",
	},
};
#endif

int chip_id(unsigned char id)
{
	struct pt_regs regs;
	int val = -EINVAL;

	if (current_el() != 3) {
		regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
		regs.regs[1] = 0;
		regs.regs[2] = 0;
		regs.regs[3] = 0;

		smc_call(&regs);

		/*
		 * SMC returns:
		 * regs[0][31:0]  = status of the operation
		 * regs[0][63:32] = CSU.IDCODE register
		 * regs[1][31:0]  = CSU.version register
		 * regs[1][63:32] = CSU.IDCODE2 register
		 */
		switch (id) {
		case IDCODE:
			regs.regs[0] = upper_32_bits(regs.regs[0]);
			regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
					ZYNQMP_CSU_IDCODE_SVD_MASK;
			regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
			val = regs.regs[0];
			break;
		case VERSION:
			regs.regs[1] = lower_32_bits(regs.regs[1]);
			regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
			val = regs.regs[1];
			break;
		case IDCODE2:
			regs.regs[1] = lower_32_bits(regs.regs[1]);
			regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
			val = regs.regs[1];
			break;
		default:
			printf("%s, Invalid Req:0x%x\n", __func__, id);
		}
	} else {
		switch (id) {
		case IDCODE:
			val = readl(ZYNQMP_CSU_IDCODE_ADDR);
			val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
			       ZYNQMP_CSU_IDCODE_SVD_MASK;
			val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
			break;
		case VERSION:
			val = readl(ZYNQMP_CSU_VER_ADDR);
			val &= ZYNQMP_CSU_SILICON_VER_MASK;
			break;
		default:
			printf("%s, Invalid Req:0x%x\n", __func__, id);
		}
	}

	return val;
}

#define ZYNQMP_VERSION_SIZE		9
#define ZYNQMP_PL_STATUS_BIT		9
#define ZYNQMP_PL_STATUS_MASK		BIT(ZYNQMP_PL_STATUS_BIT)
#define ZYNQMP_CSU_VERSION_MASK		~(ZYNQMP_PL_STATUS_MASK)

#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
	!defined(CONFIG_SPL_BUILD)
static char *zynqmp_get_silicon_idcode_name(void)
{
	u32 i, id, ver;
	char *buf;
	static char name[ZYNQMP_VERSION_SIZE];

	id = chip_id(IDCODE);
	ver = chip_id(IDCODE2);

	for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
		if ((zynqmp_devices[i].id == id) &&
		    (zynqmp_devices[i].ver == (ver &
		    ZYNQMP_CSU_VERSION_MASK))) {
			strncat(name, "zu", 2);
			strncat(name, zynqmp_devices[i].name,
				ZYNQMP_VERSION_SIZE - 3);
			break;
		}
	}

	if (i >= ARRAY_SIZE(zynqmp_devices))
		return "unknown";

	if (!zynqmp_devices[i].evexists)
		return name;

	if (ver & ZYNQMP_PL_STATUS_MASK)
		return name;

	if (strstr(name, "eg") || strstr(name, "ev")) {
		buf = strstr(name, "e");
		*buf = '\0';
	}

	return name;
}
#endif

int board_early_init_f(void)
{
	int ret = 0;
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
	zynqmp_pmufw_version();
#endif

#if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
	ret = psu_init();
#endif

#if defined(CONFIG_WDT) && !defined(CONFIG_SPL_BUILD)
	/* bss is not cleared at time when watchdog_reset() is called */
	watchdog_dev = NULL;
#endif

	return ret;
}

int board_init(void)
{
	printf("EL Level:\tEL%d\n", current_el());

#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
    !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
    defined(CONFIG_SPL_BUILD))
	if (current_el() != 3) {
		zynqmppl.name = zynqmp_get_silicon_idcode_name();
		printf("Chip ID:\t%s\n", zynqmppl.name);
		fpga_init();
		fpga_add(fpga_xilinx, &zynqmppl);
	}
#endif

#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
	if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
		puts("Watchdog: Not found!\n");
	} else {
		wdt_start(watchdog_dev, 0, 0);
		puts("Watchdog: Started\n");
	}
#endif

	return 0;
}

#ifdef CONFIG_WATCHDOG
/* Called by macro WATCHDOG_RESET */
void watchdog_reset(void)
{
# if !defined(CONFIG_SPL_BUILD)
	static ulong next_reset;
	ulong now;

	if (!watchdog_dev)
		return;

	now = timer_get_us();

	/* Do not reset the watchdog too often */
	if (now > next_reset) {
		wdt_reset(watchdog_dev);
		next_reset = now + 1000;
	}
# endif
}
#endif

int board_early_init_r(void)
{
	u32 val;

	if (current_el() != 3)
		return 0;

	val = readl(&crlapb_base->timestamp_ref_ctrl);
	val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;

	if (!val) {
		val = readl(&crlapb_base->timestamp_ref_ctrl);
		val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
		writel(val, &crlapb_base->timestamp_ref_ctrl);

		/* Program freq register in System counter */
		writel(zynqmp_get_system_timer_freq(),
		       &iou_scntr_secure->base_frequency_id_register);
		/* And enable system counter */
		writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
		       &iou_scntr_secure->counter_control_register);
	}
	return 0;
}

int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
{
#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
    defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
    defined(CONFIG_ZYNQ_EEPROM_BUS)
	i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS);

	if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
			CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
			ethaddr, 6))
		printf("I2C EEPROM MAC address read failed\n");
#endif

	return 0;
}

unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
			 char * const argv[])
{
	int ret = 0;

	if (current_el() > 1) {
		smp_kick_all_cpus();
		dcache_disable();
		armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
				    ES_TO_AARCH64);
	} else {
		printf("FAIL: current EL is not above EL1\n");
		ret = EINVAL;
	}
	return ret;
}

#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
int dram_init_banksize(void)
{
	return fdtdec_setup_memory_banksize();
}

int dram_init(void)
{
	if (fdtdec_setup_memory_size() != 0)
		return -EINVAL;

	return 0;
}
#else
int dram_init(void)
{
	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
				    CONFIG_SYS_SDRAM_SIZE);

	return 0;
}
#endif

void reset_cpu(ulong addr)
{
}

int board_late_init(void)
{
	u32 reg = 0;
	u8 bootmode;
	const char *mode;
	char *new_targets;
	char *env_targets;
	int ret;

	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
		debug("Saved variables - Skipping\n");
		return 0;
	}

	ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
	if (ret)
		return -EINVAL;

	if (reg >> BOOT_MODE_ALT_SHIFT)
		reg >>= BOOT_MODE_ALT_SHIFT;

	bootmode = reg & BOOT_MODES_MASK;

	puts("Bootmode: ");
	switch (bootmode) {
	case USB_MODE:
		puts("USB_MODE\n");
		mode = "usb";
		env_set("modeboot", "usb_dfu_spl");
		break;
	case JTAG_MODE:
		puts("JTAG_MODE\n");
		mode = "pxe dhcp";
		env_set("modeboot", "jtagboot");
		break;
	case QSPI_MODE_24BIT:
	case QSPI_MODE_32BIT:
		mode = "qspi0";
		puts("QSPI_MODE\n");
		env_set("modeboot", "qspiboot");
		break;
	case EMMC_MODE:
		puts("EMMC_MODE\n");
		mode = "mmc0";
		env_set("modeboot", "emmcboot");
		break;
	case SD_MODE:
		puts("SD_MODE\n");
		mode = "mmc0";
		env_set("modeboot", "sdboot");
		break;
	case SD1_LSHFT_MODE:
		puts("LVL_SHFT_");
		/* fall through */
	case SD_MODE1:
		puts("SD_MODE1\n");
#if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
		mode = "mmc1";
		env_set("sdbootdev", "1");
#else
		mode = "mmc0";
#endif
		env_set("modeboot", "sdboot");
		break;
	case NAND_MODE:
		puts("NAND_MODE\n");
		mode = "nand0";
		env_set("modeboot", "nandboot");
		break;
	default:
		mode = "";
		printf("Invalid Boot Mode:0x%x\n", bootmode);
		break;
	}

	/*
	 * One terminating char + one byte for space between mode
	 * and default boot_targets
	 */
	env_targets = env_get("boot_targets");
	if (env_targets) {
		new_targets = calloc(1, strlen(mode) +
				     strlen(env_targets) + 2);
		sprintf(new_targets, "%s %s", mode, env_targets);
	} else {
		new_targets = calloc(1, strlen(mode) + 2);
		sprintf(new_targets, "%s", mode);
	}

	env_set("boot_targets", new_targets);

	return 0;
}

int checkboard(void)
{
	puts("Board: Xilinx ZynqMP\n");
	return 0;
}

#ifdef CONFIG_USB_DWC3
static struct dwc3_device dwc3_device_data0 = {
	.maximum_speed = USB_SPEED_HIGH,
	.base = ZYNQMP_USB0_XHCI_BASEADDR,
	.dr_mode = USB_DR_MODE_PERIPHERAL,
	.index = 0,
};

static struct dwc3_device dwc3_device_data1 = {
	.maximum_speed = USB_SPEED_HIGH,
	.base = ZYNQMP_USB1_XHCI_BASEADDR,
	.dr_mode = USB_DR_MODE_PERIPHERAL,
	.index = 1,
};

int usb_gadget_handle_interrupts(int index)
{
	dwc3_uboot_handle_interrupt(index);
	return 0;
}

int board_usb_init(int index, enum usb_init_type init)
{
	debug("%s: index %x\n", __func__, index);

#if defined(CONFIG_USB_GADGET_DOWNLOAD)
	g_dnl_set_serialnumber(CONFIG_SYS_CONFIG_NAME);
#endif

	switch (index) {
	case 0:
		return dwc3_uboot_init(&dwc3_device_data0);
	case 1:
		return dwc3_uboot_init(&dwc3_device_data1);
	};

	return -1;
}

int board_usb_cleanup(int index, enum usb_init_type init)
{
	dwc3_uboot_exit(index);
	return 0;
}
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
84c7204b MS	2	/*
	3	* (C) Copyright 2014 - 2015 Xilinx, Inc.
	4	* Michal Simek <michal.simek@xilinx.com>
84c7204b MS	5	*/
	6
	7	#include <common.h>
679b994a	8	#include <sata.h>
6fe6f135 MS	9	#include <ahci.h>
6fe6f135 MS	10	#include <scsi.h>
b72894f1	11	#include <malloc.h>
4490e013	12	#include <wdt.h>
0785dfd8	13	#include <asm/arch/clk.h>
84c7204b MS	14	#include <asm/arch/hardware.h>
84c7204b MS	15	#include <asm/arch/sys_proto.h>
2ad341ed	16	#include <asm/arch/psu_init_gpl.h>
84c7204b	17	#include <asm/io.h>
4490e013	18	#include <dm/uclass.h>
16fa00a7 SDPP	19	#include <usb.h>
16fa00a7 SDPP	20	#include <dwc3-uboot.h>
47e60cbd	21	#include <zynqmppl.h>
6919b4bf	22	#include <i2c.h>
9feff385	23	#include <g_dnl.h>
84c7204b MS	24
	25	DECLARE_GLOBAL_DATA_PTR;
	26
4490e013 MS	27	#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
	28	static struct udevice *watchdog_dev;
	29	#endif
	30
47e60cbd MS	31	#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
	32	!defined(CONFIG_SPL_BUILD)
	33	static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
	34
	35	static const struct {
8ebdf9ef	36	u32 id;
494fffe7	37	u32 ver;
47e60cbd	38	char *name;
83bf2ff0	39	bool evexists;
47e60cbd MS	40	} zynqmp_devices[] = {
	41	{
	42	.id = 0x10,
	43	.name = "3eg",
	44	},
494fffe7 MS	45	{
	46	.id = 0x10,
	47	.ver = 0x2c,
	48	.name = "3cg",
	49	},
47e60cbd MS	50	{
	51	.id = 0x11,
	52	.name = "2eg",
	53	},
494fffe7 MS	54	{
	55	.id = 0x11,
	56	.ver = 0x2c,
	57	.name = "2cg",
	58	},
47e60cbd MS	59	{
	60	.id = 0x20,
	61	.name = "5ev",
83bf2ff0	62	.evexists = 1,
47e60cbd	63	},
494fffe7 MS	64	{
	65	.id = 0x20,
	66	.ver = 0x100,
	67	.name = "5eg",
83bf2ff0	68	.evexists = 1,
494fffe7 MS	69	},
	70	{
	71	.id = 0x20,
	72	.ver = 0x12c,
	73	.name = "5cg",
	74	},
47e60cbd MS	75	{
	76	.id = 0x21,
	77	.name = "4ev",
83bf2ff0	78	.evexists = 1,
47e60cbd	79	},
494fffe7 MS	80	{
	81	.id = 0x21,
	82	.ver = 0x100,
	83	.name = "4eg",
83bf2ff0	84	.evexists = 1,
494fffe7 MS	85	},
	86	{
	87	.id = 0x21,
	88	.ver = 0x12c,
	89	.name = "4cg",
	90	},
47e60cbd MS	91	{
	92	.id = 0x30,
	93	.name = "7ev",
83bf2ff0	94	.evexists = 1,
47e60cbd	95	},
494fffe7 MS	96	{
	97	.id = 0x30,
	98	.ver = 0x100,
	99	.name = "7eg",
83bf2ff0	100	.evexists = 1,
494fffe7 MS	101	},
	102	{
	103	.id = 0x30,
	104	.ver = 0x12c,
	105	.name = "7cg",
	106	},
47e60cbd MS	107	{
	108	.id = 0x38,
	109	.name = "9eg",
	110	},
494fffe7 MS	111	{
	112	.id = 0x38,
	113	.ver = 0x2c,
	114	.name = "9cg",
	115	},
47e60cbd MS	116	{
	117	.id = 0x39,
	118	.name = "6eg",
	119	},
494fffe7 MS	120	{
	121	.id = 0x39,
	122	.ver = 0x2c,
	123	.name = "6cg",
	124	},
47e60cbd MS	125	{
	126	.id = 0x40,
	127	.name = "11eg",
	128	},
494fffe7 MS	129	{ /* For testing purpose only */
	130	.id = 0x50,
	131	.ver = 0x2c,
	132	.name = "15cg",
	133	},
47e60cbd MS	134	{
	135	.id = 0x50,
	136	.name = "15eg",
	137	},
	138	{
	139	.id = 0x58,
	140	.name = "19eg",
	141	},
	142	{
	143	.id = 0x59,
	144	.name = "17eg",
	145	},
b030fedf MS	146	{
	147	.id = 0x61,
	148	.name = "21dr",
	149	},
	150	{
	151	.id = 0x63,
	152	.name = "23dr",
	153	},
	154	{
	155	.id = 0x65,
	156	.name = "25dr",
	157	},
	158	{
	159	.id = 0x64,
	160	.name = "27dr",
	161	},
	162	{
	163	.id = 0x60,
	164	.name = "28dr",
	165	},
	166	{
	167	.id = 0x62,
	168	.name = "29dr",
	169	},
47e60cbd	170	};
74ba69db	171	#endif
47e60cbd	172
f52bf5a3	173	int chip_id(unsigned char id)
47e60cbd MS	174	{
47e60cbd MS	175	struct pt_regs regs;
db3123b4	176	int val = -EINVAL;
47e60cbd	177
74ba69db SDPP	178	if (current_el() != 3) {
	179	regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
	180	regs.regs[1] = 0;
	181	regs.regs[2] = 0;
	182	regs.regs[3] = 0;
	183
	184	smc_call(&regs);
	185
	186	/*
	187	* SMC returns:
	188	* regs[0][31:0] = status of the operation
	189	* regs[0][63:32] = CSU.IDCODE register
	190	* regs[1][31:0] = CSU.version register
494fffe7	191	* regs[1][63:32] = CSU.IDCODE2 register
74ba69db SDPP	192	*/
	193	switch (id) {
	194	case IDCODE:
	195	regs.regs[0] = upper_32_bits(regs.regs[0]);
	196	regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK \|
	197	ZYNQMP_CSU_IDCODE_SVD_MASK;
	198	regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
	199	val = regs.regs[0];
	200	break;
	201	case VERSION:
	202	regs.regs[1] = lower_32_bits(regs.regs[1]);
	203	regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
	204	val = regs.regs[1];
	205	break;
494fffe7 MS	206	case IDCODE2:
	207	regs.regs[1] = lower_32_bits(regs.regs[1]);
	208	regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
	209	val = regs.regs[1];
	210	break;
74ba69db SDPP	211	default:
	212	printf("%s, Invalid Req:0x%x\n", __func__, id);
	213	}
	214	} else {
	215	switch (id) {
	216	case IDCODE:
	217	val = readl(ZYNQMP_CSU_IDCODE_ADDR);
	218	val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK \|
	219	ZYNQMP_CSU_IDCODE_SVD_MASK;
	220	val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
	221	break;
	222	case VERSION:
	223	val = readl(ZYNQMP_CSU_VER_ADDR);
	224	val &= ZYNQMP_CSU_SILICON_VER_MASK;
	225	break;
	226	default:
	227	printf("%s, Invalid Req:0x%x\n", __func__, id);
	228	}
db3123b4	229	}
0cba6abb	230
db3123b4	231	return val;
47e60cbd MS	232	}
47e60cbd MS	233
83bf2ff0 SDPP	234	#define ZYNQMP_VERSION_SIZE 9
	235	#define ZYNQMP_PL_STATUS_BIT 9
	236	#define ZYNQMP_PL_STATUS_MASK BIT(ZYNQMP_PL_STATUS_BIT)
	237	#define ZYNQMP_CSU_VERSION_MASK ~(ZYNQMP_PL_STATUS_MASK)
	238
74ba69db SDPP	239	#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
74ba69db SDPP	240	!defined(CONFIG_SPL_BUILD)
47e60cbd MS	241	static char *zynqmp_get_silicon_idcode_name(void)
47e60cbd MS	242	{
494fffe7	243	u32 i, id, ver;
83bf2ff0 SDPP	244	char *buf;
83bf2ff0 SDPP	245	static char name[ZYNQMP_VERSION_SIZE];
47e60cbd	246
db3123b4	247	id = chip_id(IDCODE);
494fffe7 MS	248	ver = chip_id(IDCODE2);
494fffe7 MS	249
47e60cbd	250	for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
83bf2ff0 SDPP	251	if ((zynqmp_devices[i].id == id) &&
	252	(zynqmp_devices[i].ver == (ver &
	253	ZYNQMP_CSU_VERSION_MASK))) {
	254	strncat(name, "zu", 2);
	255	strncat(name, zynqmp_devices[i].name,
	256	ZYNQMP_VERSION_SIZE - 3);
	257	break;
	258	}
47e60cbd	259	}
83bf2ff0 SDPP	260
	261	if (i >= ARRAY_SIZE(zynqmp_devices))
	262	return "unknown";
	263
	264	if (!zynqmp_devices[i].evexists)
	265	return name;
	266
	267	if (ver & ZYNQMP_PL_STATUS_MASK)
	268	return name;
	269
	270	if (strstr(name, "eg") \|\| strstr(name, "ev")) {
	271	buf = strstr(name, "e");
	272	*buf = '\0';
	273	}
	274
	275	return name;
47e60cbd MS	276	}
	277	#endif
	278
fb4000e8 MS	279	int board_early_init_f(void)
fb4000e8 MS	280	{
f32e79f1	281	int ret = 0;
fb4000e8 MS	282	#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
	283	zynqmp_pmufw_version();
	284	#endif
55de0929	285
88f05a92	286	#if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
f32e79f1	287	ret = psu_init();
55de0929 MS	288	#endif
55de0929 MS	289
4490e013 MS	290	#if defined(CONFIG_WDT) && !defined(CONFIG_SPL_BUILD)
	291	/* bss is not cleared at time when watchdog_reset() is called */
	292	watchdog_dev = NULL;
	293	#endif
	294
f32e79f1	295	return ret;
fb4000e8 MS	296	}
fb4000e8 MS	297
84c7204b MS	298	int board_init(void)
84c7204b MS	299	{
a0736efb MS	300	printf("EL Level:\tEL%d\n", current_el());
a0736efb MS	301
47e60cbd MS	302	#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
	303	!defined(CONFIG_SPL_BUILD) \|\| (defined(CONFIG_SPL_FPGA_SUPPORT) && \
	304	defined(CONFIG_SPL_BUILD))
	305	if (current_el() != 3) {
83bf2ff0	306	zynqmppl.name = zynqmp_get_silicon_idcode_name();
47e60cbd MS	307	printf("Chip ID:\t%s\n", zynqmppl.name);
	308	fpga_init();
	309	fpga_add(fpga_xilinx, &zynqmppl);
	310	}
	311	#endif
	312
4490e013 MS	313	#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
	314	if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
	315	puts("Watchdog: Not found!\n");
	316	} else {
	317	wdt_start(watchdog_dev, 0, 0);
	318	puts("Watchdog: Started\n");
	319	}
	320	#endif
	321
84c7204b MS	322	return 0;
	323	}
	324
4490e013 MS	325	#ifdef CONFIG_WATCHDOG
	326	/* Called by macro WATCHDOG_RESET */
	327	void watchdog_reset(void)
	328	{
	329	# if !defined(CONFIG_SPL_BUILD)
	330	static ulong next_reset;
	331	ulong now;
	332
	333	if (!watchdog_dev)
	334	return;
	335
	336	now = timer_get_us();
	337
	338	/* Do not reset the watchdog too often */
	339	if (now > next_reset) {
	340	wdt_reset(watchdog_dev);
	341	next_reset = now + 1000;
	342	}
	343	# endif
	344	}
	345	#endif
	346
84c7204b MS	347	int board_early_init_r(void)
	348	{
	349	u32 val;
	350
ec60a279 SDPP	351	if (current_el() != 3)
	352	return 0;
	353
90a35db4 MS	354	val = readl(&crlapb_base->timestamp_ref_ctrl);
	355	val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
	356
ec60a279	357	if (!val) {
0785dfd8 MS	358	val = readl(&crlapb_base->timestamp_ref_ctrl);
	359	val \|= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
	360	writel(val, &crlapb_base->timestamp_ref_ctrl);
84c7204b	361
0785dfd8 MS	362	/* Program freq register in System counter */
	363	writel(zynqmp_get_system_timer_freq(),
	364	&iou_scntr_secure->base_frequency_id_register);
	365	/* And enable system counter */
	366	writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
	367	&iou_scntr_secure->counter_control_register);
	368	}
84c7204b MS	369	return 0;
	370	}
	371
6919b4bf MS	372	int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
	373	{
	374	#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
	375	defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
	376	defined(CONFIG_ZYNQ_EEPROM_BUS)
	377	i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS);
	378
	379	if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
	380	CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
	381	ethaddr, 6))
	382	printf("I2C EEPROM MAC address read failed\n");
	383	#endif
	384
	385	return 0;
	386	}
	387
51916864 NJ	388	unsigned long do_go_exec(ulong (entry)(int, char const []), int argc,
	389	char * const argv[])
	390	{
	391	int ret = 0;
	392
	393	if (current_el() > 1) {
	394	smp_kick_all_cpus();
	395	dcache_disable();
	396	armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
	397	ES_TO_AARCH64);
	398	} else {
	399	printf("FAIL: current EL is not above EL1\n");
	400	ret = EINVAL;
	401	}
	402	return ret;
	403	}
	404
8d59d7f6	405	#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
76b00aca	406	int dram_init_banksize(void)
361a8799	407	{
da3f003b	408	return fdtdec_setup_memory_banksize();
8a5db0ab	409	}
8d59d7f6	410
361a8799	411	int dram_init(void)
8a5db0ab	412	{
950f86ca NR	413	if (fdtdec_setup_memory_size() != 0)
950f86ca NR	414	return -EINVAL;
8a5db0ab	415
361a8799	416	return 0;
8d59d7f6 MS	417	}
8d59d7f6 MS	418	#else
84c7204b MS	419	int dram_init(void)
84c7204b MS	420	{
61dc92a2 MS	421	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
61dc92a2 MS	422	CONFIG_SYS_SDRAM_SIZE);
84c7204b MS	423
	424	return 0;
	425	}
8d59d7f6	426	#endif
84c7204b	427
84c7204b MS	428	void reset_cpu(ulong addr)
	429	{
	430	}
	431
84c7204b MS	432	int board_late_init(void)
	433	{
	434	u32 reg = 0;
	435	u8 bootmode;
b72894f1 MS	436	const char *mode;
b72894f1 MS	437	char *new_targets;
01c42d3d	438	char *env_targets;
d1db89f4	439	int ret;
b72894f1 MS	440
	441	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
	442	debug("Saved variables - Skipping\n");
	443	return 0;
	444	}
84c7204b	445
d1db89f4 SDPP	446	ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
	447	if (ret)
	448	return -EINVAL;
	449
47359a03 MS	450	if (reg >> BOOT_MODE_ALT_SHIFT)
	451	reg >>= BOOT_MODE_ALT_SHIFT;
	452
84c7204b MS	453	bootmode = reg & BOOT_MODES_MASK;
84c7204b MS	454
fb90917c	455	puts("Bootmode: ");
84c7204b	456	switch (bootmode) {
d58fc12e MS	457	case USB_MODE:
	458	puts("USB_MODE\n");
	459	mode = "usb";
07656ba5	460	env_set("modeboot", "usb_dfu_spl");
d58fc12e	461	break;
0a5bcc8c	462	case JTAG_MODE:
fb90917c	463	puts("JTAG_MODE\n");
b72894f1	464	mode = "pxe dhcp";
07656ba5	465	env_set("modeboot", "jtagboot");
0a5bcc8c SDPP	466	break;
	467	case QSPI_MODE_24BIT:
	468	case QSPI_MODE_32BIT:
b72894f1	469	mode = "qspi0";
fb90917c	470	puts("QSPI_MODE\n");
07656ba5	471	env_set("modeboot", "qspiboot");
0a5bcc8c	472	break;
39c56f55	473	case EMMC_MODE:
78678fee	474	puts("EMMC_MODE\n");
b72894f1	475	mode = "mmc0";
07656ba5	476	env_set("modeboot", "emmcboot");
78678fee MS	477	break;
78678fee MS	478	case SD_MODE:
fb90917c	479	puts("SD_MODE\n");
b72894f1	480	mode = "mmc0";
07656ba5	481	env_set("modeboot", "sdboot");
84c7204b	482	break;
e1992276 SDPP	483	case SD1_LSHFT_MODE:
	484	puts("LVL_SHFT_");
	485	/* fall through */
af813acd	486	case SD_MODE1:
fb90917c	487	puts("SD_MODE1\n");
2d9925bc	488	#if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
b72894f1	489	mode = "mmc1";
07656ba5	490	env_set("sdbootdev", "1");
b72894f1 MS	491	#else
b72894f1 MS	492	mode = "mmc0";
2d9925bc	493	#endif
07656ba5	494	env_set("modeboot", "sdboot");
af813acd MS	495	break;
af813acd MS	496	case NAND_MODE:
fb90917c	497	puts("NAND_MODE\n");
b72894f1	498	mode = "nand0";
07656ba5	499	env_set("modeboot", "nandboot");
af813acd	500	break;
84c7204b	501	default:
b72894f1	502	mode = "";
84c7204b MS	503	printf("Invalid Boot Mode:0x%x\n", bootmode);
	504	break;
	505	}
	506
b72894f1 MS	507	/*
	508	* One terminating char + one byte for space between mode
	509	* and default boot_targets
	510	*/
01c42d3d SDPP	511	env_targets = env_get("boot_targets");
	512	if (env_targets) {
	513	new_targets = calloc(1, strlen(mode) +
	514	strlen(env_targets) + 2);
	515	sprintf(new_targets, "%s %s", mode, env_targets);
	516	} else {
	517	new_targets = calloc(1, strlen(mode) + 2);
	518	sprintf(new_targets, "%s", mode);
	519	}
b72894f1	520
382bee57	521	env_set("boot_targets", new_targets);
b72894f1	522
84c7204b MS	523	return 0;
84c7204b MS	524	}
84696ff5 SDPP	525
	526	int checkboard(void)
	527	{
5af08556	528	puts("Board: Xilinx ZynqMP\n");
84696ff5 SDPP	529	return 0;
84696ff5 SDPP	530	}
16fa00a7 SDPP	531
16fa00a7 SDPP	532	#ifdef CONFIG_USB_DWC3
275bd6d1	533	static struct dwc3_device dwc3_device_data0 = {
16fa00a7 SDPP	534	.maximum_speed = USB_SPEED_HIGH,
	535	.base = ZYNQMP_USB0_XHCI_BASEADDR,
	536	.dr_mode = USB_DR_MODE_PERIPHERAL,
	537	.index = 0,
	538	};
	539
275bd6d1 MS	540	static struct dwc3_device dwc3_device_data1 = {
	541	.maximum_speed = USB_SPEED_HIGH,
	542	.base = ZYNQMP_USB1_XHCI_BASEADDR,
	543	.dr_mode = USB_DR_MODE_PERIPHERAL,
	544	.index = 1,
	545	};
	546
9feff385	547	int usb_gadget_handle_interrupts(int index)
16fa00a7	548	{
9feff385	549	dwc3_uboot_handle_interrupt(index);
16fa00a7 SDPP	550	return 0;
	551	}
	552
	553	int board_usb_init(int index, enum usb_init_type init)
	554	{
275bd6d1 MS	555	debug("%s: index %x\n", __func__, index);
275bd6d1 MS	556
8ecd50c8 MS	557	#if defined(CONFIG_USB_GADGET_DOWNLOAD)
	558	g_dnl_set_serialnumber(CONFIG_SYS_CONFIG_NAME);
	559	#endif
	560
275bd6d1 MS	561	switch (index) {
	562	case 0:
	563	return dwc3_uboot_init(&dwc3_device_data0);
	564	case 1:
	565	return dwc3_uboot_init(&dwc3_device_data1);
	566	};
	567
	568	return -1;
16fa00a7 SDPP	569	}
	570
	571	int board_usb_cleanup(int index, enum usb_init_type init)
	572	{
	573	dwc3_uboot_exit(index);
	574	return 0;
	575	}
	576	#endif