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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
c5c1af21 CLS |
2 | /* |
3 | * (C) Copyright 2013 Altera Corporation <www.altera.com> | |
c5c1af21 CLS |
4 | */ |
5 | ||
6 | #include <common.h> | |
f7ae49fc | 7 | #include <log.h> |
c5c1af21 | 8 | #include <asm/arch/clock_manager.h> |
6b38cc2f | 9 | #include <asm/arch/secure_reg_helper.h> |
c5c1af21 | 10 | #include <asm/arch/system_manager.h> |
12ea13ad | 11 | #include <clk.h> |
c35ed77a MV |
12 | #include <dm.h> |
13 | #include <dwmmc.h> | |
14 | #include <errno.h> | |
15 | #include <fdtdec.h> | |
401d1c4f | 16 | #include <asm/global_data.h> |
336d4615 | 17 | #include <dm/device_compat.h> |
6b38cc2f | 18 | #include <linux/intel-smc.h> |
b08c8c48 | 19 | #include <linux/libfdt.h> |
c35ed77a MV |
20 | #include <linux/err.h> |
21 | #include <malloc.h> | |
2d4d6937 | 22 | #include <reset.h> |
c35ed77a MV |
23 | |
24 | DECLARE_GLOBAL_DATA_PTR; | |
c5c1af21 | 25 | |
f1a485aa SG |
26 | struct socfpga_dwmci_plat { |
27 | struct mmc_config cfg; | |
28 | struct mmc mmc; | |
29 | }; | |
30 | ||
c35ed77a | 31 | /* socfpga implmentation specific driver private data */ |
9a41404d | 32 | struct dwmci_socfpga_priv_data { |
c35ed77a MV |
33 | struct dwmci_host host; |
34 | unsigned int drvsel; | |
35 | unsigned int smplsel; | |
9a41404d CLS |
36 | }; |
37 | ||
2d4d6937 LFT |
38 | static void socfpga_dwmci_reset(struct udevice *dev) |
39 | { | |
40 | struct reset_ctl_bulk reset_bulk; | |
41 | int ret; | |
42 | ||
43 | ret = reset_get_bulk(dev, &reset_bulk); | |
44 | if (ret) { | |
45 | dev_warn(dev, "Can't get reset: %d\n", ret); | |
46 | return; | |
47 | } | |
48 | ||
49 | reset_deassert_bulk(&reset_bulk); | |
50 | } | |
51 | ||
d456dfba | 52 | static int socfpga_dwmci_clksel(struct dwmci_host *host) |
9a41404d CLS |
53 | { |
54 | struct dwmci_socfpga_priv_data *priv = host->priv; | |
a1684b61 DN |
55 | u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) | |
56 | ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT); | |
c5c1af21 CLS |
57 | |
58 | /* Disable SDMMC clock. */ | |
94172c79 LFT |
59 | clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN, |
60 | CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); | |
c5c1af21 | 61 | |
9a41404d CLS |
62 | debug("%s: drvsel %d smplsel %d\n", __func__, |
63 | priv->drvsel, priv->smplsel); | |
6b38cc2f CHA |
64 | |
65 | #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) | |
66 | int ret; | |
67 | ||
68 | ret = socfpga_secure_reg_write32(SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC, | |
69 | sdmmc_mask); | |
70 | if (ret) { | |
71 | printf("DWMMC: Failed to set clksel via SMC call"); | |
72 | return ret; | |
73 | } | |
74 | #else | |
db5741f7 | 75 | writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC); |
c5c1af21 CLS |
76 | |
77 | debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__, | |
db5741f7 | 78 | readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC)); |
6b38cc2f | 79 | #endif |
c5c1af21 CLS |
80 | |
81 | /* Enable SDMMC clock */ | |
94172c79 LFT |
82 | setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN, |
83 | CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); | |
d456dfba SCL |
84 | |
85 | return 0; | |
c5c1af21 CLS |
86 | } |
87 | ||
12ea13ad | 88 | static int socfpga_dwmmc_get_clk_rate(struct udevice *dev) |
c5c1af21 | 89 | { |
c35ed77a MV |
90 | struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev); |
91 | struct dwmci_host *host = &priv->host; | |
12ea13ad MV |
92 | #if CONFIG_IS_ENABLED(CLK) |
93 | struct clk clk; | |
94 | int ret; | |
95 | ||
96 | ret = clk_get_by_index(dev, 1, &clk); | |
97 | if (ret) | |
98 | return ret; | |
498d1a62 | 99 | |
12ea13ad MV |
100 | host->bus_hz = clk_get_rate(&clk); |
101 | ||
12ea13ad MV |
102 | #else |
103 | /* Fixed clock divide by 4 which due to the SDMMC wrapper */ | |
104 | host->bus_hz = cm_get_mmc_controller_clk_hz(); | |
105 | #endif | |
106 | if (host->bus_hz == 0) { | |
c35ed77a | 107 | printf("DWMMC: MMC clock is zero!"); |
129adf5b MV |
108 | return -EINVAL; |
109 | } | |
110 | ||
12ea13ad MV |
111 | return 0; |
112 | } | |
113 | ||
d1998a9f | 114 | static int socfpga_dwmmc_of_to_plat(struct udevice *dev) |
12ea13ad MV |
115 | { |
116 | struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev); | |
117 | struct dwmci_host *host = &priv->host; | |
118 | int fifo_depth; | |
119 | ||
e160f7d4 | 120 | fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), |
c35ed77a | 121 | "fifo-depth", 0); |
129adf5b | 122 | if (fifo_depth < 0) { |
c35ed77a | 123 | printf("DWMMC: Can't get FIFO depth\n"); |
129adf5b MV |
124 | return -EINVAL; |
125 | } | |
126 | ||
c35ed77a | 127 | host->name = dev->name; |
8613c8d8 | 128 | host->ioaddr = dev_read_addr_ptr(dev); |
e160f7d4 | 129 | host->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), |
c35ed77a | 130 | "bus-width", 4); |
c5c1af21 | 131 | host->clksel = socfpga_dwmci_clksel; |
c35ed77a MV |
132 | |
133 | /* | |
134 | * TODO(sjg@chromium.org): Remove the need for this hack. | |
135 | * We only have one dwmmc block on gen5 SoCFPGA. | |
136 | */ | |
137 | host->dev_index = 0; | |
c5c1af21 | 138 | host->fifoth_val = MSIZE(0x2) | |
129adf5b | 139 | RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2); |
e160f7d4 | 140 | priv->drvsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), |
c35ed77a | 141 | "drvsel", 3); |
e160f7d4 | 142 | priv->smplsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), |
c35ed77a | 143 | "smplsel", 0); |
9a41404d | 144 | host->priv = priv; |
c5c1af21 | 145 | |
1925e657 LFT |
146 | host->fifo_mode = dev_read_bool(dev, "fifo-mode"); |
147 | ||
129adf5b MV |
148 | return 0; |
149 | } | |
150 | ||
c35ed77a | 151 | static int socfpga_dwmmc_probe(struct udevice *dev) |
129adf5b | 152 | { |
f1a485aa | 153 | #ifdef CONFIG_BLK |
c69cda25 | 154 | struct socfpga_dwmci_plat *plat = dev_get_plat(dev); |
f1a485aa | 155 | #endif |
c35ed77a MV |
156 | struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); |
157 | struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev); | |
158 | struct dwmci_host *host = &priv->host; | |
12ea13ad MV |
159 | int ret; |
160 | ||
161 | ret = socfpga_dwmmc_get_clk_rate(dev); | |
162 | if (ret) | |
163 | return ret; | |
f1a485aa | 164 | |
2d4d6937 LFT |
165 | socfpga_dwmci_reset(dev); |
166 | ||
f1a485aa | 167 | #ifdef CONFIG_BLK |
e5113c33 | 168 | dwmci_setup_cfg(&plat->cfg, host, host->bus_hz, 400000); |
f1a485aa SG |
169 | host->mmc = &plat->mmc; |
170 | #else | |
129adf5b | 171 | |
c35ed77a MV |
172 | ret = add_dwmci(host, host->bus_hz, 400000); |
173 | if (ret) | |
174 | return ret; | |
f1a485aa SG |
175 | #endif |
176 | host->mmc->priv = &priv->host; | |
c35ed77a | 177 | upriv->mmc = host->mmc; |
cffe5d86 | 178 | host->mmc->dev = dev; |
129adf5b | 179 | |
55118ec9 | 180 | return dwmci_probe(dev); |
129adf5b | 181 | } |
c35ed77a | 182 | |
f1a485aa SG |
183 | static int socfpga_dwmmc_bind(struct udevice *dev) |
184 | { | |
185 | #ifdef CONFIG_BLK | |
c69cda25 | 186 | struct socfpga_dwmci_plat *plat = dev_get_plat(dev); |
f1a485aa SG |
187 | int ret; |
188 | ||
189 | ret = dwmci_bind(dev, &plat->mmc, &plat->cfg); | |
190 | if (ret) | |
191 | return ret; | |
192 | #endif | |
193 | ||
194 | return 0; | |
195 | } | |
196 | ||
c35ed77a MV |
197 | static const struct udevice_id socfpga_dwmmc_ids[] = { |
198 | { .compatible = "altr,socfpga-dw-mshc" }, | |
199 | { } | |
200 | }; | |
201 | ||
202 | U_BOOT_DRIVER(socfpga_dwmmc_drv) = { | |
203 | .name = "socfpga_dwmmc", | |
204 | .id = UCLASS_MMC, | |
205 | .of_match = socfpga_dwmmc_ids, | |
d1998a9f | 206 | .of_to_plat = socfpga_dwmmc_of_to_plat, |
f55ae197 | 207 | .ops = &dm_dwmci_ops, |
f1a485aa | 208 | .bind = socfpga_dwmmc_bind, |
c35ed77a | 209 | .probe = socfpga_dwmmc_probe, |
41575d8e | 210 | .priv_auto = sizeof(struct dwmci_socfpga_priv_data), |
caa4daa2 | 211 | .plat_auto = sizeof(struct socfpga_dwmci_plat), |
c35ed77a | 212 | }; |