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efi_loader: Fix efi_add_runtime_mmio definition
[thirdparty/u-boot.git] / drivers / net / fsl-mc / mc.c
CommitLineData
b940ca64
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1/*
2 * Copyright (C) 2014 Freescale Semiconductor
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
21c69870 6#include <common.h>
b940ca64 7#include <errno.h>
84b8bf6d 8#include <linux/bug.h>
b940ca64 9#include <asm/io.h>
21c69870
SY
10#include <libfdt.h>
11#include <fdt_support.h>
7b3bd9a7
GR
12#include <fsl-mc/fsl_mc.h>
13#include <fsl-mc/fsl_mc_sys.h>
a2a55e51 14#include <fsl-mc/fsl_mc_private.h>
7b3bd9a7 15#include <fsl-mc/fsl_dpmng.h>
a2a55e51
PK
16#include <fsl-mc/fsl_dprc.h>
17#include <fsl-mc/fsl_dpio.h>
fb4a87a7 18#include <fsl-mc/fsl_dpni.h>
a2a55e51 19#include <fsl-mc/fsl_qbman_portal.h>
fb4a87a7 20#include <fsl-mc/ldpaa_wriop.h>
b940ca64 21
125e2bc1
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22#define MC_RAM_BASE_ADDR_ALIGNMENT (512UL * 1024 * 1024)
23#define MC_RAM_BASE_ADDR_ALIGNMENT_MASK (~(MC_RAM_BASE_ADDR_ALIGNMENT - 1))
24#define MC_RAM_SIZE_ALIGNMENT (256UL * 1024 * 1024)
25
26#define MC_MEM_SIZE_ENV_VAR "mcmemsize"
27#define MC_BOOT_TIMEOUT_ENV_VAR "mcboottimeout"
28
b940ca64 29DECLARE_GLOBAL_DATA_PTR;
fb4a87a7
PK
30static int mc_boot_status = -1;
31static int mc_dpl_applied = -1;
32#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
33static int mc_aiop_applied = -1;
34#endif
1730a17d
PK
35struct fsl_mc_io *root_mc_io = NULL;
36struct fsl_mc_io *dflt_mc_io = NULL; /* child container */
37uint16_t root_dprc_handle = 0;
a2a55e51 38uint16_t dflt_dprc_handle = 0;
1730a17d 39int child_dprc_id;
a2a55e51
PK
40struct fsl_dpbp_obj *dflt_dpbp = NULL;
41struct fsl_dpio_obj *dflt_dpio = NULL;
1730a17d 42struct fsl_dpni_obj *dflt_dpni = NULL;
125e2bc1
GR
43
44#ifdef DEBUG
45void dump_ram_words(const char *title, void *addr)
46{
47 int i;
48 uint32_t *words = addr;
49
50 printf("Dumping beginning of %s (%p):\n", title, addr);
51 for (i = 0; i < 16; i++)
52 printf("%#x ", words[i]);
53
54 printf("\n");
55}
b940ca64 56
125e2bc1
GR
57void dump_mc_ccsr_regs(struct mc_ccsr_registers __iomem *mc_ccsr_regs)
58{
59 printf("MC CCSR registers:\n"
60 "reg_gcr1 %#x\n"
61 "reg_gsr %#x\n"
62 "reg_sicbalr %#x\n"
63 "reg_sicbahr %#x\n"
64 "reg_sicapr %#x\n"
65 "reg_mcfbalr %#x\n"
66 "reg_mcfbahr %#x\n"
67 "reg_mcfapr %#x\n"
68 "reg_psr %#x\n",
69 mc_ccsr_regs->reg_gcr1,
70 mc_ccsr_regs->reg_gsr,
71 mc_ccsr_regs->reg_sicbalr,
72 mc_ccsr_regs->reg_sicbahr,
73 mc_ccsr_regs->reg_sicapr,
74 mc_ccsr_regs->reg_mcfbalr,
75 mc_ccsr_regs->reg_mcfbahr,
76 mc_ccsr_regs->reg_mcfapr,
77 mc_ccsr_regs->reg_psr);
78}
79#else
80
81#define dump_ram_words(title, addr)
82#define dump_mc_ccsr_regs(mc_ccsr_regs)
83
84#endif /* DEBUG */
85
86#ifndef CONFIG_SYS_LS_MC_FW_IN_DDR
b940ca64
GR
87/**
88 * Copying MC firmware or DPL image to DDR
89 */
90static int mc_copy_image(const char *title,
7b3bd9a7 91 u64 image_addr, u32 image_size, u64 mc_ram_addr)
b940ca64
GR
92{
93 debug("%s copied to address %p\n", title, (void *)mc_ram_addr);
94 memcpy((void *)mc_ram_addr, (void *)image_addr, image_size);
125e2bc1 95 flush_dcache_range(mc_ram_addr, mc_ram_addr + image_size);
b940ca64
GR
96 return 0;
97}
98
99/**
100 * MC firmware FIT image parser checks if the image is in FIT
101 * format, verifies integrity of the image and calculates
102 * raw image address and size values.
7b3bd9a7 103 * Returns 0 on success and a negative errno on error.
b940ca64
GR
104 * task fail.
105 **/
fb4a87a7
PK
106int parse_mc_firmware_fit_image(u64 mc_fw_addr,
107 const void **raw_image_addr,
b940ca64
GR
108 size_t *raw_image_size)
109{
110 int format;
111 void *fit_hdr;
112 int node_offset;
113 const void *data;
114 size_t size;
115 const char *uname = "firmware";
116
fb4a87a7 117 fit_hdr = (void *)mc_fw_addr;
b940ca64
GR
118
119 /* Check if Image is in FIT format */
120 format = genimg_get_format(fit_hdr);
121
122 if (format != IMAGE_FORMAT_FIT) {
fb4a87a7 123 printf("fsl-mc: ERR: Bad firmware image (not a FIT image)\n");
7b3bd9a7 124 return -EINVAL;
b940ca64
GR
125 }
126
127 if (!fit_check_format(fit_hdr)) {
fb4a87a7 128 printf("fsl-mc: ERR: Bad firmware image (bad FIT header)\n");
7b3bd9a7 129 return -EINVAL;
b940ca64
GR
130 }
131
132 node_offset = fit_image_get_node(fit_hdr, uname);
133
134 if (node_offset < 0) {
fb4a87a7 135 printf("fsl-mc: ERR: Bad firmware image (missing subimage)\n");
7b3bd9a7 136 return -ENOENT;
b940ca64
GR
137 }
138
139 /* Verify MC firmware image */
140 if (!(fit_image_verify(fit_hdr, node_offset))) {
fb4a87a7 141 printf("fsl-mc: ERR: Bad firmware image (bad CRC)\n");
7b3bd9a7 142 return -EINVAL;
b940ca64
GR
143 }
144
145 /* Get address and size of raw image */
146 fit_image_get_data(fit_hdr, node_offset, &data, &size);
147
148 *raw_image_addr = data;
149 *raw_image_size = size;
150
151 return 0;
152}
125e2bc1
GR
153#endif
154
155/*
156 * Calculates the values to be used to specify the address range
157 * for the MC private DRAM block, in the MCFBALR/MCFBAHR registers.
158 * It returns the highest 512MB-aligned address within the given
159 * address range, in '*aligned_base_addr', and the number of 256 MiB
160 * blocks in it, in 'num_256mb_blocks'.
161 */
162static int calculate_mc_private_ram_params(u64 mc_private_ram_start_addr,
163 size_t mc_ram_size,
164 u64 *aligned_base_addr,
165 u8 *num_256mb_blocks)
166{
167 u64 addr;
168 u16 num_blocks;
169
170 if (mc_ram_size % MC_RAM_SIZE_ALIGNMENT != 0) {
171 printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n",
172 mc_ram_size);
173 return -EINVAL;
174 }
175
176 num_blocks = mc_ram_size / MC_RAM_SIZE_ALIGNMENT;
177 if (num_blocks < 1 || num_blocks > 0xff) {
178 printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n",
179 mc_ram_size);
180 return -EINVAL;
181 }
182
183 addr = (mc_private_ram_start_addr + mc_ram_size - 1) &
184 MC_RAM_BASE_ADDR_ALIGNMENT_MASK;
185
186 if (addr < mc_private_ram_start_addr) {
187 printf("fsl-mc: ERROR: bad start address %#llx\n",
188 mc_private_ram_start_addr);
189 return -EFAULT;
190 }
191
192 *aligned_base_addr = addr;
193 *num_256mb_blocks = num_blocks;
194 return 0;
195}
196
21c69870
SY
197static int mc_fixup_dpc(u64 dpc_addr)
198{
199 void *blob = (void *)dpc_addr;
200 int nodeoffset;
201
202 /* delete any existing ICID pools */
203 nodeoffset = fdt_path_offset(blob, "/resources/icid_pools");
204 if (fdt_del_node(blob, nodeoffset) < 0)
205 printf("\nfsl-mc: WARNING: could not delete ICID pool\n");
206
207 /* add a new pool */
208 nodeoffset = fdt_path_offset(blob, "/resources");
209 if (nodeoffset < 0) {
210 printf("\nfsl-mc: ERROR: DPC is missing /resources\n");
211 return -EINVAL;
212 }
213 nodeoffset = fdt_add_subnode(blob, nodeoffset, "icid_pools");
214 nodeoffset = fdt_add_subnode(blob, nodeoffset, "icid_pool@0");
215 do_fixup_by_path_u32(blob, "/resources/icid_pools/icid_pool@0",
216 "base_icid", FSL_DPAA2_STREAM_ID_START, 1);
217 do_fixup_by_path_u32(blob, "/resources/icid_pools/icid_pool@0",
218 "num",
219 FSL_DPAA2_STREAM_ID_END -
220 FSL_DPAA2_STREAM_ID_START + 1, 1);
221
222 flush_dcache_range(dpc_addr, dpc_addr + fdt_totalsize(blob));
223
224 return 0;
225}
226
fb4a87a7 227static int load_mc_dpc(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpc_addr)
125e2bc1
GR
228{
229 u64 mc_dpc_offset;
230#ifndef CONFIG_SYS_LS_MC_DPC_IN_DDR
231 int error;
232 void *dpc_fdt_hdr;
233 int dpc_size;
234#endif
235
236#ifdef CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET
237 BUILD_BUG_ON((CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET & 0x3) != 0 ||
238 CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET > 0xffffffff);
239
240 mc_dpc_offset = CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET;
241#else
242#error "CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET not defined"
243#endif
244
245 /*
246 * Load the MC DPC blob in the MC private DRAM block:
247 */
248#ifdef CONFIG_SYS_LS_MC_DPC_IN_DDR
249 printf("MC DPC is preloaded to %#llx\n", mc_ram_addr + mc_dpc_offset);
250#else
251 /*
252 * Get address and size of the DPC blob stored in flash:
253 */
fb4a87a7 254 dpc_fdt_hdr = (void *)mc_dpc_addr;
125e2bc1
GR
255
256 error = fdt_check_header(dpc_fdt_hdr);
257 if (error != 0) {
258 /*
259 * Don't return with error here, since the MC firmware can
260 * still boot without a DPC
261 */
cc088c3a 262 printf("\nfsl-mc: WARNING: No DPC image found");
125e2bc1
GR
263 return 0;
264 }
265
266 dpc_size = fdt_totalsize(dpc_fdt_hdr);
267 if (dpc_size > CONFIG_SYS_LS_MC_DPC_MAX_LENGTH) {
cc088c3a 268 printf("\nfsl-mc: ERROR: Bad DPC image (too large: %d)\n",
125e2bc1
GR
269 dpc_size);
270 return -EINVAL;
271 }
272
273 mc_copy_image("MC DPC blob",
274 (u64)dpc_fdt_hdr, dpc_size, mc_ram_addr + mc_dpc_offset);
275#endif /* not defined CONFIG_SYS_LS_MC_DPC_IN_DDR */
276
21c69870
SY
277 if (mc_fixup_dpc(mc_ram_addr + mc_dpc_offset))
278 return -EINVAL;
279
125e2bc1
GR
280 dump_ram_words("DPC", (void *)(mc_ram_addr + mc_dpc_offset));
281 return 0;
282}
283
fb4a87a7 284static int load_mc_dpl(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpl_addr)
125e2bc1
GR
285{
286 u64 mc_dpl_offset;
287#ifndef CONFIG_SYS_LS_MC_DPL_IN_DDR
288 int error;
289 void *dpl_fdt_hdr;
290 int dpl_size;
291#endif
292
293#ifdef CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET
294 BUILD_BUG_ON((CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET & 0x3) != 0 ||
295 CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET > 0xffffffff);
296
297 mc_dpl_offset = CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET;
298#else
299#error "CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET not defined"
300#endif
301
302 /*
303 * Load the MC DPL blob in the MC private DRAM block:
304 */
305#ifdef CONFIG_SYS_LS_MC_DPL_IN_DDR
306 printf("MC DPL is preloaded to %#llx\n", mc_ram_addr + mc_dpl_offset);
307#else
308 /*
309 * Get address and size of the DPL blob stored in flash:
310 */
fb4a87a7 311 dpl_fdt_hdr = (void *)mc_dpl_addr;
125e2bc1
GR
312
313 error = fdt_check_header(dpl_fdt_hdr);
314 if (error != 0) {
cc088c3a 315 printf("\nfsl-mc: ERROR: Bad DPL image (bad header)\n");
125e2bc1
GR
316 return error;
317 }
318
319 dpl_size = fdt_totalsize(dpl_fdt_hdr);
320 if (dpl_size > CONFIG_SYS_LS_MC_DPL_MAX_LENGTH) {
cc088c3a 321 printf("\nfsl-mc: ERROR: Bad DPL image (too large: %d)\n",
125e2bc1
GR
322 dpl_size);
323 return -EINVAL;
324 }
325
326 mc_copy_image("MC DPL blob",
327 (u64)dpl_fdt_hdr, dpl_size, mc_ram_addr + mc_dpl_offset);
328#endif /* not defined CONFIG_SYS_LS_MC_DPL_IN_DDR */
329
330 dump_ram_words("DPL", (void *)(mc_ram_addr + mc_dpl_offset));
331 return 0;
332}
333
334/**
335 * Return the MC boot timeout value in milliseconds
336 */
337static unsigned long get_mc_boot_timeout_ms(void)
338{
339 unsigned long timeout_ms = CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS;
340
341 char *timeout_ms_env_var = getenv(MC_BOOT_TIMEOUT_ENV_VAR);
342
343 if (timeout_ms_env_var) {
344 timeout_ms = simple_strtoul(timeout_ms_env_var, NULL, 10);
345 if (timeout_ms == 0) {
346 printf("fsl-mc: WARNING: Invalid value for \'"
347 MC_BOOT_TIMEOUT_ENV_VAR
348 "\' environment variable: %lu\n",
349 timeout_ms);
350
351 timeout_ms = CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS;
352 }
353 }
354
355 return timeout_ms;
356}
357
fb4a87a7 358#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
3c1d218a
YS
359
360__weak bool soc_has_aiop(void)
361{
362 return false;
363}
364
fb4a87a7 365static int load_mc_aiop_img(u64 aiop_fw_addr)
c1000c12 366{
fb4a87a7
PK
367 u64 mc_ram_addr = mc_get_dram_addr();
368#ifndef CONFIG_SYS_LS_MC_DPC_IN_DDR
c1000c12 369 void *aiop_img;
fb4a87a7 370#endif
c1000c12 371
3c1d218a
YS
372 /* Check if AIOP is available */
373 if (!soc_has_aiop())
374 return -ENODEV;
c1000c12
GR
375 /*
376 * Load the MC AIOP image in the MC private DRAM block:
377 */
378
fb4a87a7
PK
379#ifdef CONFIG_SYS_LS_MC_DPC_IN_DDR
380 printf("MC AIOP is preloaded to %#llx\n", mc_ram_addr +
381 CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET);
382#else
383 aiop_img = (void *)aiop_fw_addr;
c1000c12
GR
384 mc_copy_image("MC AIOP image",
385 (u64)aiop_img, CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH,
386 mc_ram_addr + CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET);
fb4a87a7
PK
387#endif
388 mc_aiop_applied = 0;
c1000c12
GR
389
390 return 0;
391}
392#endif
fb4a87a7 393
125e2bc1
GR
394static int wait_for_mc(bool booting_mc, u32 *final_reg_gsr)
395{
396 u32 reg_gsr;
397 u32 mc_fw_boot_status;
398 unsigned long timeout_ms = get_mc_boot_timeout_ms();
399 struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR;
400
401 dmb();
125e2bc1
GR
402 assert(timeout_ms > 0);
403 for (;;) {
404 udelay(1000); /* throttle polling */
405 reg_gsr = in_le32(&mc_ccsr_regs->reg_gsr);
406 mc_fw_boot_status = (reg_gsr & GSR_FS_MASK);
407 if (mc_fw_boot_status & 0x1)
408 break;
409
410 timeout_ms--;
411 if (timeout_ms == 0)
412 break;
413 }
414
415 if (timeout_ms == 0) {
cc088c3a 416 printf("ERROR: timeout\n");
125e2bc1
GR
417
418 /* TODO: Get an error status from an MC CCSR register */
419 return -ETIMEDOUT;
420 }
421
422 if (mc_fw_boot_status != 0x1) {
423 /*
424 * TODO: Identify critical errors from the GSR register's FS
425 * field and for those errors, set error to -ENODEV or other
426 * appropriate errno, so that the status property is set to
427 * failure in the fsl,dprc device tree node.
428 */
cc088c3a
GR
429 printf("WARNING: Firmware returned an error (GSR: %#x)\n",
430 reg_gsr);
431 } else {
432 printf("SUCCESS\n");
125e2bc1
GR
433 }
434
cc088c3a 435
125e2bc1
GR
436 *final_reg_gsr = reg_gsr;
437 return 0;
438}
b940ca64 439
fb4a87a7 440int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr)
b940ca64
GR
441{
442 int error = 0;
a2a55e51 443 int portal_id = 0;
b940ca64 444 struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR;
fb4a87a7 445 u64 mc_ram_addr = mc_get_dram_addr();
b940ca64 446 u32 reg_gsr;
125e2bc1
GR
447 u32 reg_mcfbalr;
448#ifndef CONFIG_SYS_LS_MC_FW_IN_DDR
b940ca64
GR
449 const void *raw_image_addr;
450 size_t raw_image_size = 0;
125e2bc1 451#endif
7b3bd9a7 452 struct mc_version mc_ver_info;
125e2bc1
GR
453 u64 mc_ram_aligned_base_addr;
454 u8 mc_ram_num_256mb_blocks;
455 size_t mc_ram_size = mc_get_dram_block_size();
b940ca64 456
b940ca64 457
125e2bc1
GR
458 error = calculate_mc_private_ram_params(mc_ram_addr,
459 mc_ram_size,
460 &mc_ram_aligned_base_addr,
461 &mc_ram_num_256mb_blocks);
462 if (error != 0)
463 goto out;
464
b940ca64
GR
465 /*
466 * Management Complex cores should be held at reset out of POR.
a187559e 467 * U-Boot should be the first software to touch MC. To be safe,
b940ca64
GR
468 * we reset all cores again by setting GCR1 to 0. It doesn't do
469 * anything if they are held at reset. After we setup the firmware
470 * we kick off MC by deasserting the reset bit for core 0, and
471 * deasserting the reset bits for Command Portal Managers.
472 * The stop bits are not touched here. They are used to stop the
473 * cores when they are active. Setting stop bits doesn't stop the
474 * cores from fetching instructions when they are released from
475 * reset.
476 */
477 out_le32(&mc_ccsr_regs->reg_gcr1, 0);
478 dmb();
479
125e2bc1
GR
480#ifdef CONFIG_SYS_LS_MC_FW_IN_DDR
481 printf("MC firmware is preloaded to %#llx\n", mc_ram_addr);
482#else
fb4a87a7
PK
483 error = parse_mc_firmware_fit_image(mc_fw_addr, &raw_image_addr,
484 &raw_image_size);
b940ca64
GR
485 if (error != 0)
486 goto out;
487 /*
488 * Load the MC FW at the beginning of the MC private DRAM block:
489 */
7b3bd9a7
GR
490 mc_copy_image("MC Firmware",
491 (u64)raw_image_addr, raw_image_size, mc_ram_addr);
7b3bd9a7 492#endif
125e2bc1 493 dump_ram_words("firmware", (void *)mc_ram_addr);
7b3bd9a7 494
fb4a87a7 495 error = load_mc_dpc(mc_ram_addr, mc_ram_size, mc_dpc_addr);
125e2bc1 496 if (error != 0)
b940ca64 497 goto out;
b940ca64
GR
498
499 debug("mc_ccsr_regs %p\n", mc_ccsr_regs);
125e2bc1 500 dump_mc_ccsr_regs(mc_ccsr_regs);
b940ca64
GR
501
502 /*
125e2bc1 503 * Tell MC what is the address range of the DRAM block assigned to it:
b940ca64 504 */
125e2bc1
GR
505 reg_mcfbalr = (u32)mc_ram_aligned_base_addr |
506 (mc_ram_num_256mb_blocks - 1);
507 out_le32(&mc_ccsr_regs->reg_mcfbalr, reg_mcfbalr);
508 out_le32(&mc_ccsr_regs->reg_mcfbahr,
509 (u32)(mc_ram_aligned_base_addr >> 32));
39da644e 510 out_le32(&mc_ccsr_regs->reg_mcfapr, FSL_BYPASS_AMQ);
b940ca64
GR
511
512 /*
125e2bc1 513 * Tell the MC that we want delayed DPL deployment.
b940ca64 514 */
125e2bc1 515 out_le32(&mc_ccsr_regs->reg_gsr, 0xDD00);
b940ca64 516
cc088c3a 517 printf("\nfsl-mc: Booting Management Complex ... ");
7b3bd9a7 518
b940ca64
GR
519 /*
520 * Deassert reset and release MC core 0 to run
521 */
522 out_le32(&mc_ccsr_regs->reg_gcr1, GCR1_P1_DE_RST | GCR1_M_ALL_DE_RST);
125e2bc1
GR
523 error = wait_for_mc(true, &reg_gsr);
524 if (error != 0)
b940ca64 525 goto out;
b940ca64 526
7b3bd9a7
GR
527 /*
528 * TODO: need to obtain the portal_id for the root container from the
529 * DPL
530 */
531 portal_id = 0;
532
533 /*
a2a55e51
PK
534 * Initialize the global default MC portal
535 * And check that the MC firmware is responding portal commands:
7b3bd9a7 536 */
1730a17d
PK
537 root_mc_io = (struct fsl_mc_io *)malloc(sizeof(struct fsl_mc_io));
538 if (!root_mc_io) {
a2a55e51
PK
539 printf(" No memory: malloc() failed\n");
540 return -ENOMEM;
541 }
542
1730a17d 543 root_mc_io->mmio_regs = SOC_MC_PORTAL_ADDR(portal_id);
7b3bd9a7 544 debug("Checking access to MC portal of root DPRC container (portal_id %d, portal physical addr %p)\n",
1730a17d 545 portal_id, root_mc_io->mmio_regs);
7b3bd9a7 546
1730a17d 547 error = mc_get_version(root_mc_io, MC_CMD_NO_FLAGS, &mc_ver_info);
7b3bd9a7
GR
548 if (error != 0) {
549 printf("fsl-mc: ERROR: Firmware version check failed (error: %d)\n",
550 error);
551 goto out;
552 }
553
7b3bd9a7
GR
554 printf("fsl-mc: Management Complex booted (version: %d.%d.%d, boot status: %#x)\n",
555 mc_ver_info.major, mc_ver_info.minor, mc_ver_info.revision,
125e2bc1
GR
556 reg_gsr & GSR_FS_MASK);
557
fb4a87a7
PK
558out:
559 if (error != 0)
560 mc_boot_status = error;
561 else
562 mc_boot_status = 0;
563
564 return error;
565}
566
567int mc_apply_dpl(u64 mc_dpl_addr)
568{
569 struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR;
570 int error = 0;
571 u32 reg_gsr;
572 u64 mc_ram_addr = mc_get_dram_addr();
573 size_t mc_ram_size = mc_get_dram_block_size();
574
575 error = load_mc_dpl(mc_ram_addr, mc_ram_size, mc_dpl_addr);
576 if (error != 0)
577 return error;
578
125e2bc1
GR
579 /*
580 * Tell the MC to deploy the DPL:
581 */
582 out_le32(&mc_ccsr_regs->reg_gsr, 0x0);
cc088c3a 583 printf("fsl-mc: Deploying data path layout ... ");
125e2bc1 584 error = wait_for_mc(false, &reg_gsr);
cc088c3a 585
fb4a87a7
PK
586 if (!error)
587 mc_dpl_applied = 0;
b940ca64
GR
588
589 return error;
590}
591
592int get_mc_boot_status(void)
593{
594 return mc_boot_status;
595}
596
fb4a87a7
PK
597#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
598int get_aiop_apply_status(void)
599{
600 return mc_aiop_applied;
601}
602#endif
603
604int get_dpl_apply_status(void)
605{
606 return mc_dpl_applied;
607}
608
609/**
610 * Return the MC address of private DRAM block.
611 */
612u64 mc_get_dram_addr(void)
613{
614 u64 mc_ram_addr;
615
616 /*
617 * The MC private DRAM block was already carved at the end of DRAM
618 * by board_init_f() using CONFIG_SYS_MEM_TOP_HIDE:
619 */
620 if (gd->bd->bi_dram[1].start) {
621 mc_ram_addr =
622 gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size;
623 } else {
624 mc_ram_addr =
625 gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
626 }
627
628 return mc_ram_addr;
629}
630
b940ca64
GR
631/**
632 * Return the actual size of the MC private DRAM block.
b940ca64
GR
633 */
634unsigned long mc_get_dram_block_size(void)
635{
125e2bc1
GR
636 unsigned long dram_block_size = CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE;
637
638 char *dram_block_size_env_var = getenv(MC_MEM_SIZE_ENV_VAR);
639
640 if (dram_block_size_env_var) {
641 dram_block_size = simple_strtoul(dram_block_size_env_var, NULL,
642 10);
643
644 if (dram_block_size < CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE) {
645 printf("fsl-mc: WARNING: Invalid value for \'"
646 MC_MEM_SIZE_ENV_VAR
647 "\' environment variable: %lu\n",
648 dram_block_size);
649
650 dram_block_size = CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE;
651 }
652 }
653
654 return dram_block_size;
b940ca64 655}
a2a55e51 656
1730a17d
PK
657int fsl_mc_ldpaa_init(bd_t *bis)
658{
c919ab9e
PK
659 int i;
660
661 for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++)
662 if ((wriop_is_enabled_dpmac(i) == 1) &&
663 (wriop_get_phy_address(i) != -1))
664 ldpaa_eth_init(i, wriop_get_enet_if(i));
1730a17d
PK
665 return 0;
666}
667
9a696f56
PK
668static int dprc_version_check(struct fsl_mc_io *mc_io, uint16_t handle)
669{
670 struct dprc_attributes attr;
671 int error;
672
673 memset(&attr, 0, sizeof(struct dprc_attributes));
674 error = dprc_get_attributes(mc_io, MC_CMD_NO_FLAGS, handle, &attr);
675 if (error == 0) {
676 if ((attr.version.major != DPRC_VER_MAJOR) ||
677 (attr.version.minor != DPRC_VER_MINOR)) {
678 printf("DPRC version mismatch found %u.%u,",
679 attr.version.major,
680 attr.version.minor);
681 printf("supported version is %u.%u\n",
682 DPRC_VER_MAJOR, DPRC_VER_MINOR);
683 }
684 }
685 return error;
686}
687
1730a17d 688static int dpio_init(void)
a2a55e51
PK
689{
690 struct qbman_swp_desc p_des;
691 struct dpio_attr attr;
1730a17d 692 struct dpio_cfg dpio_cfg;
a2a55e51
PK
693 int err = 0;
694
695 dflt_dpio = (struct fsl_dpio_obj *)malloc(sizeof(struct fsl_dpio_obj));
696 if (!dflt_dpio) {
1730a17d
PK
697 printf("No memory: malloc() failed\n");
698 err = -ENOMEM;
699 goto err_malloc;
a2a55e51
PK
700 }
701
1730a17d
PK
702 dpio_cfg.channel_mode = DPIO_LOCAL_CHANNEL;
703 dpio_cfg.num_priorities = 8;
a2a55e51 704
1730a17d
PK
705 err = dpio_create(dflt_mc_io, MC_CMD_NO_FLAGS, &dpio_cfg,
706 &dflt_dpio->dpio_handle);
707 if (err < 0) {
708 printf("dpio_create() failed: %d\n", err);
709 err = -ENODEV;
710 goto err_create;
a2a55e51
PK
711 }
712
1730a17d 713 memset(&attr, 0, sizeof(struct dpio_attr));
87457d11 714 err = dpio_get_attributes(dflt_mc_io, MC_CMD_NO_FLAGS,
1730a17d
PK
715 dflt_dpio->dpio_handle, &attr);
716 if (err < 0) {
717 printf("dpio_get_attributes() failed: %d\n", err);
a2a55e51
PK
718 goto err_get_attr;
719 }
720
9a696f56
PK
721 if ((attr.version.major != DPIO_VER_MAJOR) ||
722 (attr.version.minor != DPIO_VER_MINOR)) {
723 printf("DPIO version mismatch found %u.%u,",
724 attr.version.major, attr.version.minor);
725 printf("supported version is %u.%u\n",
726 DPIO_VER_MAJOR, DPIO_VER_MINOR);
727 }
728
1730a17d
PK
729 dflt_dpio->dpio_id = attr.id;
730#ifdef DEBUG
731 printf("Init: DPIO id=0x%d\n", dflt_dpio->dpio_id);
732#endif
1730a17d
PK
733 err = dpio_enable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
734 if (err < 0) {
a2a55e51
PK
735 printf("dpio_enable() failed %d\n", err);
736 goto err_get_enable;
737 }
1f1c25c7
PK
738 debug("ce_offset=0x%llx, ci_offset=0x%llx, portalid=%d, prios=%d\n",
739 attr.qbman_portal_ce_offset,
740 attr.qbman_portal_ci_offset,
a2a55e51
PK
741 attr.qbman_portal_id,
742 attr.num_priorities);
743
1f1c25c7
PK
744 p_des.cena_bar = (void *)(SOC_QBMAN_PORTALS_BASE_ADDR
745 + attr.qbman_portal_ce_offset);
746 p_des.cinh_bar = (void *)(SOC_QBMAN_PORTALS_BASE_ADDR
747 + attr.qbman_portal_ci_offset);
a2a55e51
PK
748
749 dflt_dpio->sw_portal = qbman_swp_init(&p_des);
750 if (dflt_dpio->sw_portal == NULL) {
751 printf("qbman_swp_init() failed\n");
752 goto err_get_swp_init;
753 }
754 return 0;
755
756err_get_swp_init:
1730a17d 757 dpio_disable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
a2a55e51 758err_get_enable:
1730a17d
PK
759err_get_attr:
760 dpio_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
761 dpio_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
762err_create:
cd7b3fbc 763 free(dflt_dpio);
1730a17d
PK
764err_malloc:
765 return err;
766}
767
768static int dpio_exit(void)
769{
770 int err;
771
772 err = dpio_disable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
773 if (err < 0) {
774 printf("dpio_disable() failed: %d\n", err);
775 goto err;
776 }
777
778 err = dpio_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
779 if (err < 0) {
780 printf("dpio_destroy() failed: %d\n", err);
781 goto err;
782 }
783
784#ifdef DEBUG
785 printf("Exit: DPIO id=0x%d\n", dflt_dpio->dpio_id);
786#endif
787
788 if (dflt_dpio)
789 free(dflt_dpio);
790
791 return 0;
792err:
793 return err;
794}
795
796static int dprc_init(void)
797{
798 int err, child_portal_id, container_id;
799 struct dprc_cfg cfg;
800 uint64_t mc_portal_offset;
801
802 /* Open root container */
803 err = dprc_get_container_id(root_mc_io, MC_CMD_NO_FLAGS, &container_id);
804 if (err < 0) {
805 printf("dprc_get_container_id(): Root failed: %d\n", err);
806 goto err_root_container_id;
807 }
808
809#ifdef DEBUG
810 printf("Root container id = %d\n", container_id);
811#endif
812 err = dprc_open(root_mc_io, MC_CMD_NO_FLAGS, container_id,
813 &root_dprc_handle);
814 if (err < 0) {
815 printf("dprc_open(): Root Container failed: %d\n", err);
816 goto err_root_open;
817 }
818
819 if (!root_dprc_handle) {
820 printf("dprc_open(): Root Container Handle is not valid\n");
821 goto err_root_open;
822 }
823
9a696f56
PK
824 err = dprc_version_check(root_mc_io, root_dprc_handle);
825 if (err < 0) {
826 printf("dprc_version_check() failed: %d\n", err);
827 goto err_root_open;
828 }
829
5373b204 830 memset(&cfg, 0, sizeof(struct dprc_cfg));
1730a17d
PK
831 cfg.options = DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED |
832 DPRC_CFG_OPT_OBJ_CREATE_ALLOWED |
833 DPRC_CFG_OPT_ALLOC_ALLOWED;
834 cfg.icid = DPRC_GET_ICID_FROM_POOL;
335b1936 835 cfg.portal_id = DPRC_GET_PORTAL_ID_FROM_POOL;
1730a17d
PK
836 err = dprc_create_container(root_mc_io, MC_CMD_NO_FLAGS,
837 root_dprc_handle,
838 &cfg,
839 &child_dprc_id,
840 &mc_portal_offset);
841 if (err < 0) {
842 printf("dprc_create_container() failed: %d\n", err);
843 goto err_create;
844 }
845
846 dflt_mc_io = (struct fsl_mc_io *)malloc(sizeof(struct fsl_mc_io));
847 if (!dflt_mc_io) {
848 err = -ENOMEM;
849 printf(" No memory: malloc() failed\n");
850 goto err_malloc;
851 }
852
853 child_portal_id = MC_PORTAL_OFFSET_TO_PORTAL_ID(mc_portal_offset);
854 dflt_mc_io->mmio_regs = SOC_MC_PORTAL_ADDR(child_portal_id);
855#ifdef DEBUG
856 printf("MC portal of child DPRC container: %d, physical addr %p)\n",
857 child_dprc_id, dflt_mc_io->mmio_regs);
858#endif
859
860 err = dprc_open(dflt_mc_io, MC_CMD_NO_FLAGS, child_dprc_id,
861 &dflt_dprc_handle);
862 if (err < 0) {
863 printf("dprc_open(): Child container failed: %d\n", err);
864 goto err_child_open;
865 }
866
867 if (!dflt_dprc_handle) {
868 printf("dprc_open(): Child container Handle is not valid\n");
869 goto err_child_open;
870 }
871
872 return 0;
873err_child_open:
874 free(dflt_mc_io);
875err_malloc:
876 dprc_destroy_container(root_mc_io, MC_CMD_NO_FLAGS,
877 root_dprc_handle, child_dprc_id);
878err_create:
879 dprc_close(root_mc_io, MC_CMD_NO_FLAGS, root_dprc_handle);
880err_root_open:
881err_root_container_id:
882 return err;
883}
884
885static int dprc_exit(void)
886{
887 int err;
888
889 err = dprc_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dprc_handle);
890 if (err < 0) {
891 printf("dprc_close(): Child failed: %d\n", err);
892 goto err;
893 }
894
895 err = dprc_destroy_container(root_mc_io, MC_CMD_NO_FLAGS,
896 root_dprc_handle, child_dprc_id);
897 if (err < 0) {
898 printf("dprc_destroy_container() failed: %d\n", err);
899 goto err;
900 }
901
902 err = dprc_close(root_mc_io, MC_CMD_NO_FLAGS, root_dprc_handle);
903 if (err < 0) {
904 printf("dprc_close(): Root failed: %d\n", err);
905 goto err;
906 }
907
908 if (dflt_mc_io)
909 free(dflt_mc_io);
910
911 if (root_mc_io)
912 free(root_mc_io);
913
914 return 0;
915
916err:
a2a55e51
PK
917 return err;
918}
919
1730a17d 920static int dpbp_init(void)
a2a55e51 921{
1730a17d
PK
922 int err;
923 struct dpbp_attr dpbp_attr;
924 struct dpbp_cfg dpbp_cfg;
925
a2a55e51
PK
926 dflt_dpbp = (struct fsl_dpbp_obj *)malloc(sizeof(struct fsl_dpbp_obj));
927 if (!dflt_dpbp) {
1730a17d
PK
928 printf("No memory: malloc() failed\n");
929 err = -ENOMEM;
930 goto err_malloc;
931 }
932
933 dpbp_cfg.options = 512;
934
935 err = dpbp_create(dflt_mc_io, MC_CMD_NO_FLAGS, &dpbp_cfg,
936 &dflt_dpbp->dpbp_handle);
937
938 if (err < 0) {
939 err = -ENODEV;
940 printf("dpbp_create() failed: %d\n", err);
941 goto err_create;
942 }
943
944 memset(&dpbp_attr, 0, sizeof(struct dpbp_attr));
945 err = dpbp_get_attributes(dflt_mc_io, MC_CMD_NO_FLAGS,
946 dflt_dpbp->dpbp_handle,
947 &dpbp_attr);
948 if (err < 0) {
949 printf("dpbp_get_attributes() failed: %d\n", err);
950 goto err_get_attr;
951 }
952
9a696f56
PK
953 if ((dpbp_attr.version.major != DPBP_VER_MAJOR) ||
954 (dpbp_attr.version.minor != DPBP_VER_MINOR)) {
955 printf("DPBP version mismatch found %u.%u,",
956 dpbp_attr.version.major, dpbp_attr.version.minor);
957 printf("supported version is %u.%u\n",
958 DPBP_VER_MAJOR, DPBP_VER_MINOR);
959 }
960
1730a17d
PK
961 dflt_dpbp->dpbp_attr.id = dpbp_attr.id;
962#ifdef DEBUG
963 printf("Init: DPBP id=0x%d\n", dflt_dpbp->dpbp_attr.id);
964#endif
965
966 err = dpbp_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle);
967 if (err < 0) {
968 printf("dpbp_close() failed: %d\n", err);
969 goto err_close;
a2a55e51 970 }
a2a55e51
PK
971
972 return 0;
1730a17d
PK
973
974err_close:
975 free(dflt_dpbp);
976err_get_attr:
977 dpbp_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle);
978 dpbp_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle);
979err_create:
980err_malloc:
981 return err;
a2a55e51
PK
982}
983
1730a17d
PK
984static int dpbp_exit(void)
985{
986 int err;
987
988 err = dpbp_open(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_attr.id,
989 &dflt_dpbp->dpbp_handle);
990 if (err < 0) {
991 printf("dpbp_open() failed: %d\n", err);
992 goto err;
993 }
994
995 err = dpbp_destroy(dflt_mc_io, MC_CMD_NO_FLAGS,
996 dflt_dpbp->dpbp_handle);
997 if (err < 0) {
998 printf("dpbp_destroy() failed: %d\n", err);
999 goto err;
1000 }
1001
1002#ifdef DEBUG
1003 printf("Exit: DPBP id=0x%d\n", dflt_dpbp->dpbp_attr.id);
1004#endif
1005
1006 if (dflt_dpbp)
1007 free(dflt_dpbp);
1008 return 0;
1009
1010err:
1011 return err;
1012}
1013
1014static int dpni_init(void)
1015{
1016 int err;
1017 struct dpni_attr dpni_attr;
879a59ac
PK
1018 uint8_t ext_cfg_buf[256] = {0};
1019 struct dpni_extended_cfg dpni_extended_cfg;
1730a17d
PK
1020 struct dpni_cfg dpni_cfg;
1021
1022 dflt_dpni = (struct fsl_dpni_obj *)malloc(sizeof(struct fsl_dpni_obj));
1023 if (!dflt_dpni) {
1024 printf("No memory: malloc() failed\n");
1025 err = -ENOMEM;
1026 goto err_malloc;
1027 }
1028
879a59ac
PK
1029 memset(&dpni_extended_cfg, 0, sizeof(dpni_extended_cfg));
1030 err = dpni_prepare_extended_cfg(&dpni_extended_cfg, &ext_cfg_buf[0]);
1031 if (err < 0) {
1032 err = -ENODEV;
1033 printf("dpni_prepare_extended_cfg() failed: %d\n", err);
1034 goto err_prepare_extended_cfg;
1035 }
1036
1730a17d
PK
1037 memset(&dpni_cfg, 0, sizeof(dpni_cfg));
1038 dpni_cfg.adv.options = DPNI_OPT_UNICAST_FILTER |
1039 DPNI_OPT_MULTICAST_FILTER;
1040
879a59ac 1041 dpni_cfg.adv.ext_cfg_iova = (uint64_t)&ext_cfg_buf[0];
1730a17d
PK
1042 err = dpni_create(dflt_mc_io, MC_CMD_NO_FLAGS, &dpni_cfg,
1043 &dflt_dpni->dpni_handle);
1044
1045 if (err < 0) {
1046 err = -ENODEV;
1047 printf("dpni_create() failed: %d\n", err);
1048 goto err_create;
1049 }
1050
1051 memset(&dpni_attr, 0, sizeof(struct dpni_attr));
1052 err = dpni_get_attributes(dflt_mc_io, MC_CMD_NO_FLAGS,
1053 dflt_dpni->dpni_handle,
1054 &dpni_attr);
1055 if (err < 0) {
1056 printf("dpni_get_attributes() failed: %d\n", err);
1057 goto err_get_attr;
1058 }
1059
9a696f56
PK
1060 if ((dpni_attr.version.major != DPNI_VER_MAJOR) ||
1061 (dpni_attr.version.minor != DPNI_VER_MINOR)) {
1062 printf("DPNI version mismatch found %u.%u,",
1063 dpni_attr.version.major, dpni_attr.version.minor);
1064 printf("supported version is %u.%u\n",
1065 DPNI_VER_MAJOR, DPNI_VER_MINOR);
1066 }
1067
1730a17d
PK
1068 dflt_dpni->dpni_id = dpni_attr.id;
1069#ifdef DEBUG
1070 printf("Init: DPNI id=0x%d\n", dflt_dpni->dpni_id);
1071#endif
1072
1073 err = dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
1074 if (err < 0) {
1075 printf("dpni_close() failed: %d\n", err);
1076 goto err_close;
1077 }
1078
1079 return 0;
1080
1081err_close:
1730a17d
PK
1082err_get_attr:
1083 dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
1084 dpni_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
1085err_create:
879a59ac
PK
1086err_prepare_extended_cfg:
1087 free(dflt_dpni);
1730a17d
PK
1088err_malloc:
1089 return err;
1090}
1091
1092static int dpni_exit(void)
1093{
1094 int err;
1095
1096 err = dpni_open(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_id,
1097 &dflt_dpni->dpni_handle);
1098 if (err < 0) {
1099 printf("dpni_open() failed: %d\n", err);
1100 goto err;
1101 }
1102
1103 err = dpni_destroy(dflt_mc_io, MC_CMD_NO_FLAGS,
1104 dflt_dpni->dpni_handle);
1105 if (err < 0) {
1106 printf("dpni_destroy() failed: %d\n", err);
1107 goto err;
1108 }
1109
1110#ifdef DEBUG
1111 printf("Exit: DPNI id=0x%d\n", dflt_dpni->dpni_id);
1112#endif
1113
1114 if (dflt_dpni)
1115 free(dflt_dpni);
1116 return 0;
1117
1118err:
1119 return err;
1120}
1121
1122static int mc_init_object(void)
a2a55e51 1123{
1730a17d
PK
1124 int err = 0;
1125
1126 err = dprc_init();
1127 if (err < 0) {
1128 printf("dprc_init() failed: %d\n", err);
1129 goto err;
1130 }
1131
1132 err = dpbp_init();
1133 if (err < 0) {
1134 printf("dpbp_init() failed: %d\n", err);
1135 goto err;
1136 }
1137
1138 err = dpio_init();
1139 if (err < 0) {
1140 printf("dpio_init() failed: %d\n", err);
1141 goto err;
1142 }
1143
1144 err = dpni_init();
1145 if (err < 0) {
1146 printf("dpni_init() failed: %d\n", err);
1147 goto err;
1148 }
a2a55e51 1149
fb4a87a7 1150 return 0;
1730a17d
PK
1151err:
1152 return err;
a2a55e51
PK
1153}
1154
1730a17d 1155int fsl_mc_ldpaa_exit(bd_t *bd)
a2a55e51 1156{
1730a17d
PK
1157 int err = 0;
1158
6dedcedd
PK
1159 /* MC is not loaded intentionally, So return success. */
1160 if (bd && get_mc_boot_status() != 0)
1730a17d
PK
1161 return 0;
1162
1163 if (bd && !get_mc_boot_status() && get_dpl_apply_status() == -1) {
1164 printf("ERROR: fsl-mc: DPL is not applied\n");
1165 err = -ENODEV;
1166 return err;
1167 }
1168
1169 if (bd && !get_mc_boot_status() && !get_dpl_apply_status())
1170 return err;
1171
1172 err = dpbp_exit();
1173 if (err < 0) {
a2a4dc56 1174 printf("dpbp_exit() failed: %d\n", err);
1730a17d
PK
1175 goto err;
1176 }
1177
1178 err = dpio_exit();
1179 if (err < 0) {
1180 printf("dpio_exit() failed: %d\n", err);
1181 goto err;
1182 }
1183
1184 err = dpni_exit();
1185 if (err < 0) {
1186 printf("dpni_exit() failed: %d\n", err);
1187 goto err;
1188 }
1189
1190 err = dprc_exit();
1191 if (err < 0) {
1192 printf("dprc_exit() failed: %d\n", err);
1193 goto err;
1194 }
1195
1196 return 0;
1197err:
1198 return err;
a2a55e51
PK
1199}
1200
fb4a87a7 1201static int do_fsl_mc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
a2a55e51 1202{
fb4a87a7
PK
1203 int err = 0;
1204 if (argc < 3)
1205 goto usage;
1206
1207 switch (argv[1][0]) {
1208 case 's': {
1209 char sub_cmd;
44937214
PK
1210 u64 mc_fw_addr, mc_dpc_addr;
1211#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
1212 u64 aiop_fw_addr;
1213#endif
fb4a87a7
PK
1214
1215 sub_cmd = argv[2][0];
1216 switch (sub_cmd) {
1217 case 'm':
1218 if (argc < 5)
1219 goto usage;
1220
1221 if (get_mc_boot_status() == 0) {
1222 printf("fsl-mc: MC is already booted");
1223 printf("\n");
1224 return err;
1225 }
1226 mc_fw_addr = simple_strtoull(argv[3], NULL, 16);
1227 mc_dpc_addr = simple_strtoull(argv[4], NULL,
1228 16);
1730a17d
PK
1229
1230 if (!mc_init(mc_fw_addr, mc_dpc_addr))
1231 err = mc_init_object();
fb4a87a7
PK
1232 break;
1233
1234#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
1235 case 'a':
1236 if (argc < 4)
1237 goto usage;
1238 if (get_aiop_apply_status() == 0) {
1239 printf("fsl-mc: AIOP FW is already");
1240 printf(" applied\n");
1241 return err;
1242 }
1243
1244 aiop_fw_addr = simple_strtoull(argv[3], NULL,
1245 16);
1246
3c1d218a 1247 /* if SoC doesn't have AIOP, err = -ENODEV */
fb4a87a7
PK
1248 err = load_mc_aiop_img(aiop_fw_addr);
1249 if (!err)
1250 printf("fsl-mc: AIOP FW applied\n");
1251 break;
1252#endif
1253 default:
1254 printf("Invalid option: %s\n", argv[2]);
1255 goto usage;
a2a55e51 1256
fb4a87a7
PK
1257 break;
1258 }
125e2bc1 1259 }
fb4a87a7
PK
1260 break;
1261
1262 case 'a': {
1263 u64 mc_dpl_addr;
1264
1265 if (argc < 4)
1266 goto usage;
1267
1268 if (get_dpl_apply_status() == 0) {
1269 printf("fsl-mc: DPL already applied\n");
1270 return err;
1271 }
1272
1273 mc_dpl_addr = simple_strtoull(argv[3], NULL,
1274 16);
1730a17d 1275
fb4a87a7
PK
1276 if (get_mc_boot_status() != 0) {
1277 printf("fsl-mc: Deploying data path layout ..");
1278 printf("ERROR (MC is not booted)\n");
1279 return -ENODEV;
1280 }
1730a17d
PK
1281
1282 if (!fsl_mc_ldpaa_exit(NULL))
1283 err = mc_apply_dpl(mc_dpl_addr);
fb4a87a7 1284 break;
125e2bc1 1285 }
fb4a87a7
PK
1286 default:
1287 printf("Invalid option: %s\n", argv[1]);
1288 goto usage;
1289 break;
a2a55e51 1290 }
fb4a87a7
PK
1291 return err;
1292 usage:
1293 return CMD_RET_USAGE;
a2a55e51 1294}
fb4a87a7
PK
1295
1296U_BOOT_CMD(
1297 fsl_mc, CONFIG_SYS_MAXARGS, 1, do_fsl_mc,
1298 "DPAA2 command to manage Management Complex (MC)",
1299 "start mc [FW_addr] [DPC_addr] - Start Management Complex\n"
1300 "fsl_mc apply DPL [DPL_addr] - Apply DPL file\n"
1301 "fsl_mc start aiop [FW_addr] - Start AIOP\n"
1302);