Bindings/arm/arm,coresight-stm.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/arm/arm,coresight-stm.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Arm CoreSight System Trace MacroCell
   8
   9 maintainers:
  10   - Mathieu Poirier <mathieu.poirier@linaro.org>
  11   - Mike Leach <mike.leach@linaro.org>
  12   - Leo Yan <leo.yan@linaro.org>
  13   - Suzuki K Poulose <suzuki.poulose@arm.com>
  14
  15 description: |
  16   CoreSight components are compliant with the ARM CoreSight architecture
  17   specification and can be connected in various topologies to suit a particular
  18   SoCs tracing needs. These trace components can generally be classified as
  19   sinks, links and sources. Trace data produced by one or more sources flows
  20   through the intermediate links connecting the source to the currently selected
  21   sink.
  22
  23   The STM is a trace source that is integrated into a CoreSight system, designed
  24   primarily for high-bandwidth trace of instrumentation embedded into software.
  25   This instrumentation is made up of memory-mapped writes to the STM Advanced
  26   eXtensible Interface (AXI) slave, which carry information about the behavior
  27   of the software.
  28
  29 select:
  30   properties:
  31     compatible:
  32       contains:
  33         const: arm,coresight-stm
  34   required:
  35     - compatible
  36
  37 allOf:
  38   - $ref: /schemas/arm/primecell.yaml#
  39
  40 properties:
  41   compatible:
  42     items:
  43       - const: arm,coresight-stm
  44       - const: arm,primecell
  45
  46   reg:
  47     maxItems: 2
  48
  49   reg-names:
  50     items:
  51       - const: stm-base
  52       - const: stm-stimulus-base
  53
  54   clocks:
  55     minItems: 1
  56     maxItems: 2
  57
  58   clock-names:
  59     minItems: 1
  60     items:
  61       - const: apb_pclk
  62       - const: atclk
  63
  64   power-domains:
  65     maxItems: 1
  66
  67   out-ports:
  68     $ref: /schemas/graph.yaml#/properties/ports
  69     additionalProperties: false
  70
  71     properties:
  72       port:
  73         description: Output connection to the CoreSight Trace bus.
  74         $ref: /schemas/graph.yaml#/properties/port
  75
  76 required:
  77   - compatible
  78   - reg
  79   - reg-names
  80   - clocks
  81   - clock-names
  82   - out-ports
  83
  84 unevaluatedProperties: false
  85
  86 examples:
  87   - |
  88     stm@20100000 {
  89         compatible = "arm,coresight-stm", "arm,primecell";
  90         reg = <0x20100000 0x1000>,
  91               <0x28000000 0x180000>;
  92         reg-names = "stm-base", "stm-stimulus-base";
  93
  94         clocks = <&soc_smc50mhz>;
  95         clock-names = "apb_pclk";
  96         out-ports {
  97             port {
  98                 stm_out_port: endpoint {
  99                     remote-endpoint = <&main_funnel_in_port2>;
 100                 };
 101             };
 102         };
 103     };
 104 ...