Bindings/clock/st,stm32-rcc.txt

   1 STMicroelectronics STM32 Reset and Clock Controller
   2 ===================================================
   3
   4 The RCC IP is both a reset and a clock controller.
   5
   6 Please refer to clock-bindings.txt for common clock controller binding usage.
   7 Please also refer to reset.txt for common reset controller binding usage.
   8
   9 Required properties:
  10 - compatible: Should be:
  11   "st,stm32f42xx-rcc"
  12   "st,stm32f469-rcc"
  13   "st,stm32f746-rcc"
  14   "st,stm32f769-rcc"
  15
  16 - reg: should be register base and length as documented in the
  17   datasheet
  18 - #reset-cells: 1, see below
  19 - #clock-cells: 2, device nodes should specify the clock in their "clocks"
  20   property, containing a phandle to the clock device node, an index selecting
  21   between gated clocks and other clocks and an index specifying the clock to
  22   use.
  23 - clocks: External oscillator clock phandle
  24   - high speed external clock signal (HSE)
  25   - external I2S clock (I2S_CKIN)
  26
  27 Example:
  28
  29         rcc: rcc@40023800 {
  30                 #reset-cells = <1>;
  31                 #clock-cells = <2>
  32                 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
  33                 reg = <0x40023800 0x400>;
  34                 clocks = <&clk_hse>, <&clk_i2s_ckin>;
  35         };
  36
  37 Specifying gated clocks
  38 =======================
  39
  40 The primary index must be set to 0.
  41
  42 The secondary index is the bit number within the RCC register bank, starting
  43 from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30).
  44
  45 It is calculated as: index = register_offset / 4 * 32 + bit_offset.
  46 Where bit_offset is the bit offset within the register (LSB is 0, MSB is 31).
  47
  48 To simplify the usage and to share bit definition with the reset and clock
  49 drivers of the RCC IP, macros are available to generate the index in
  50 human-readble format.
  51
  52 For STM32F4 series, the macro are available here:
  53  - include/dt-bindings/mfd/stm32f4-rcc.h
  54
  55 Example:
  56
  57         /* Gated clock, AHB1 bit 0 (GPIOA) */
  58         ... {
  59                 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>
  60         };
  61
  62         /* Gated clock, AHB2 bit 4 (CRYP) */
  63         ... {
  64                 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(CRYP)>
  65         };
  66
  67 Specifying other clocks
  68 =======================
  69
  70 The primary index must be set to 1.
  71
  72 The secondary index is bound with the following magic numbers:
  73
  74         0       SYSTICK
  75         1       FCLK
  76         2       CLK_LSI         (low-power clock source)
  77         3       CLK_LSE         (generated from a 32.768 kHz low-speed external
  78                                  crystal or ceramic resonator)
  79         4       CLK_HSE_RTC     (HSE division factor for RTC clock)
  80         5       CLK_RTC         (real-time clock)
  81         6       PLL_VCO_I2S     (vco frequency of I2S pll)
  82         7       PLL_VCO_SAI     (vco frequency of SAI pll)
  83         8       CLK_LCD         (LCD-TFT)
  84         9       CLK_I2S         (I2S clocks)
  85         10      CLK_SAI1        (audio clocks)
  86         11      CLK_SAI2
  87         12      CLK_I2SQ_PDIV   (post divisor of pll i2s q divisor)
  88         13      CLK_SAIQ_PDIV   (post divisor of pll sai q divisor)
  89
  90         14      CLK_HSI         (Internal ocscillator clock)
  91         15      CLK_SYSCLK      (System Clock)
  92         16      CLK_HDMI_CEC    (HDMI-CEC clock)
  93         17      CLK_SPDIF       (SPDIF-Rx clock)
  94         18      CLK_USART1      (U(s)arts clocks)
  95         19      CLK_USART2
  96         20      CLK_USART3
  97         21      CLK_UART4
  98         22      CLK_UART5
  99         23      CLK_USART6
 100         24      CLK_UART7
 101         25      CLK_UART8
 102         26      CLK_I2C1        (I2S clocks)
 103         27      CLK_I2C2
 104         28      CLK_I2C3
 105         29      CLK_I2C4
 106         30      CLK_LPTIMER     (LPTimer1 clock)
 107         31      CLK_PLL_SRC
 108         32      CLK_DFSDM1
 109         33      CLK_ADFSDM1
 110         34      CLK_F769_DSI
 111 )
 112
 113 Example:
 114
 115         /* Misc clock, FCLK */
 116         ... {
 117                 clocks = <&rcc 1 STM32F4_APB1_CLOCK(TIM2)>
 118         };
 119
 120
 121 Specifying softreset control of devices
 122 =======================================
 123
 124 Device nodes should specify the reset channel required in their "resets"
 125 property, containing a phandle to the reset device node and an index specifying
 126 which channel to use.
 127 The index is the bit number within the RCC registers bank, starting from RCC
 128 base address.
 129 It is calculated as: index = register_offset / 4 * 32 + bit_offset.
 130 Where bit_offset is the bit offset within the register.
 131 For example, for CRC reset:
 132   crc = AHB1RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x10 / 4 * 32 + 12 = 140
 133
 134 example:
 135
 136         timer2 {
 137                 resets  = <&rcc STM32F4_APB1_RESET(TIM2)>;
 138         };