Bindings/crypto/fsl-sec6.txt

   1 SEC 6 is as Freescale's Cryptographic Accelerator and Assurance Module (CAAM).
   2 Currently Freescale powerpc chip C29X is embedded with SEC 6.
   3 SEC 6 device tree binding include:
   4    -SEC 6 Node
   5    -Job Ring Node
   6    -Full Example
   7
   8 =====================================================================
   9 SEC 6 Node
  10
  11 Description
  12
  13     Node defines the base address of the SEC 6 block.
  14     This block specifies the address range of all global
  15     configuration registers for the SEC 6 block.
  16     For example, In C293, we could see three SEC 6 node.
  17
  18 PROPERTIES
  19
  20    - compatible
  21       Usage: required
  22       Value type: <string>
  23       Definition: Must include "fsl,sec-v6.0".
  24
  25    - fsl,sec-era
  26       Usage: optional
  27       Value type: <u32>
  28       Definition: A standard property. Define the 'ERA' of the SEC
  29           device.
  30
  31    - #address-cells
  32        Usage: required
  33        Value type: <u32>
  34        Definition: A standard property.  Defines the number of cells
  35            for representing physical addresses in child nodes.
  36
  37    - #size-cells
  38        Usage: required
  39        Value type: <u32>
  40        Definition: A standard property.  Defines the number of cells
  41            for representing the size of physical addresses in
  42            child nodes.
  43
  44    - reg
  45       Usage: required
  46       Value type: <prop-encoded-array>
  47       Definition: A standard property.  Specifies the physical
  48           address and length of the SEC 6 configuration registers.
  49
  50    - ranges
  51        Usage: required
  52        Value type: <prop-encoded-array>
  53        Definition: A standard property.  Specifies the physical address
  54            range of the SEC 6.0 register space (-SNVS not included).  A
  55            triplet that includes the child address, parent address, &
  56            length.
  57
  58    Note: All other standard properties (see the Devicetree Specification)
  59    are allowed but are optional.
  60
  61 EXAMPLE
  62         crypto@a0000 {
  63                 compatible = "fsl,sec-v6.0";
  64                 fsl,sec-era = <6>;
  65                 #address-cells = <1>;
  66                 #size-cells = <1>;
  67                 reg = <0xa0000 0x20000>;
  68                 ranges = <0 0xa0000 0x20000>;
  69         };
  70
  71 =====================================================================
  72 Job Ring (JR) Node
  73
  74     Child of the crypto node defines data processing interface to SEC 6
  75     across the peripheral bus for purposes of processing
  76     cryptographic descriptors. The specified address
  77     range can be made visible to one (or more) cores.
  78     The interrupt defined for this node is controlled within
  79     the address range of this node.
  80
  81   - compatible
  82       Usage: required
  83       Value type: <string>
  84       Definition: Must include "fsl,sec-v6.0-job-ring".
  85
  86   - reg
  87       Usage: required
  88       Value type: <prop-encoded-array>
  89       Definition: Specifies a two JR parameters:  an offset from
  90            the parent physical address and the length the JR registers.
  91
  92    - interrupts
  93       Usage: required
  94       Value type: <prop_encoded-array>
  95       Definition:  Specifies the interrupts generated by this
  96            device.  The value of the interrupts property
  97            consists of one interrupt specifier. The format
  98            of the specifier is defined by the binding document
  99            describing the node's interrupt parent.
 100
 101 EXAMPLE
 102         jr@1000 {
 103                 compatible = "fsl,sec-v6.0-job-ring";
 104                 reg = <0x1000 0x1000>;
 105                 interrupts = <49 2 0 0>;
 106         };
 107
 108 ===================================================================
 109 Full Example
 110
 111 Since some chips may contain more than one SEC, the dtsi contains
 112 only the node contents, not the node itself.  A chip using the SEC
 113 should include the dtsi inside each SEC node.  Example:
 114
 115 In qoriq-sec6.0.dtsi:
 116
 117         compatible = "fsl,sec-v6.0";
 118         fsl,sec-era = <6>;
 119         #address-cells = <1>;
 120         #size-cells = <1>;
 121
 122         jr@1000 {
 123                 compatible = "fsl,sec-v6.0-job-ring",
 124                              "fsl,sec-v5.2-job-ring",
 125                              "fsl,sec-v5.0-job-ring",
 126                              "fsl,sec-v4.4-job-ring",
 127                              "fsl,sec-v4.0-job-ring";
 128                 reg        = <0x1000 0x1000>;
 129         };
 130
 131         jr@2000 {
 132                 compatible = "fsl,sec-v6.0-job-ring",
 133                              "fsl,sec-v5.2-job-ring",
 134                              "fsl,sec-v5.0-job-ring",
 135                              "fsl,sec-v4.4-job-ring",
 136                              "fsl,sec-v4.0-job-ring";
 137                 reg        = <0x2000 0x1000>;
 138         };
 139
 140 In the C293 device tree, we add the include of public property:
 141
 142         crypto@a0000 {
 143                 /include/ "qoriq-sec6.0.dtsi"
 144         }
 145
 146         crypto@a0000 {
 147                 reg = <0xa0000 0x20000>;
 148                 ranges = <0 0xa0000 0x20000>;
 149
 150                 jr@1000 {
 151                         interrupts = <49 2 0 0>;
 152                 };
 153
 154                 jr@2000 {
 155                         interrupts = <50 2 0 0>;
 156                 };
 157         };