Bindings/display/msm/qcom,sc7280-mdss.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/msm/qcom,sc7280-mdss.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm SC7280 Display MDSS
   8
   9 maintainers:
  10   - Krishna Manikandan <quic_mkrishn@quicinc.com>
  11
  12 description:
  13   Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates
  14   sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
  15   bindings of MDSS are mentioned for SC7280.
  16
  17 $ref: /schemas/display/msm/mdss-common.yaml#
  18
  19 properties:
  20   compatible:
  21     const: qcom,sc7280-mdss
  22
  23   clocks:
  24     items:
  25       - description: Display AHB clock from gcc
  26       - description: Display AHB clock from dispcc
  27       - description: Display core clock
  28
  29   clock-names:
  30     items:
  31       - const: iface
  32       - const: ahb
  33       - const: core
  34
  35   iommus:
  36     maxItems: 1
  37
  38   interconnects:
  39     maxItems: 1
  40
  41   interconnect-names:
  42     maxItems: 1
  43
  44 patternProperties:
  45   "^display-controller@[0-9a-f]+$":
  46     type: object
  47     additionalProperties: true
  48
  49     properties:
  50       compatible:
  51         const: qcom,sc7280-dpu
  52
  53   "^displayport-controller@[0-9a-f]+$":
  54     type: object
  55     additionalProperties: true
  56
  57     properties:
  58       compatible:
  59         const: qcom,sc7280-dp
  60
  61   "^dsi@[0-9a-f]+$":
  62     type: object
  63     additionalProperties: true
  64
  65     properties:
  66       compatible:
  67         items:
  68           - const: qcom,sc7280-dsi-ctrl
  69           - const: qcom,mdss-dsi-ctrl
  70
  71   "^edp@[0-9a-f]+$":
  72     type: object
  73     additionalProperties: true
  74
  75     properties:
  76       compatible:
  77         const: qcom,sc7280-edp
  78
  79   "^phy@[0-9a-f]+$":
  80     type: object
  81     additionalProperties: true
  82
  83     properties:
  84       compatible:
  85         enum:
  86           - qcom,sc7280-dsi-phy-7nm
  87           - qcom,sc7280-edp-phy
  88
  89 required:
  90   - compatible
  91
  92 unevaluatedProperties: false
  93
  94 examples:
  95   - |
  96     #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
  97     #include <dt-bindings/clock/qcom,gcc-sc7280.h>
  98     #include <dt-bindings/clock/qcom,rpmh.h>
  99     #include <dt-bindings/interrupt-controller/arm-gic.h>
 100     #include <dt-bindings/interconnect/qcom,sc7280.h>
 101     #include <dt-bindings/power/qcom-rpmpd.h>
 102
 103     display-subsystem@ae00000 {
 104         #address-cells = <1>;
 105         #size-cells = <1>;
 106         compatible = "qcom,sc7280-mdss";
 107         reg = <0xae00000 0x1000>;
 108         reg-names = "mdss";
 109         power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
 110         clocks = <&gcc GCC_DISP_AHB_CLK>,
 111                  <&dispcc DISP_CC_MDSS_AHB_CLK>,
 112                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
 113         clock-names = "iface",
 114                       "ahb",
 115                       "core";
 116
 117         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 118         interrupt-controller;
 119         #interrupt-cells = <1>;
 120
 121         interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
 122         interconnect-names = "mdp0-mem";
 123
 124         iommus = <&apps_smmu 0x900 0x402>;
 125         ranges;
 126
 127         display-controller@ae01000 {
 128             compatible = "qcom,sc7280-dpu";
 129             reg = <0x0ae01000 0x8f000>,
 130                   <0x0aeb0000 0x2008>;
 131
 132             reg-names = "mdp", "vbif";
 133
 134             clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
 135                      <&gcc GCC_DISP_SF_AXI_CLK>,
 136                      <&dispcc DISP_CC_MDSS_AHB_CLK>,
 137                      <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
 138                      <&dispcc DISP_CC_MDSS_MDP_CLK>,
 139                      <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
 140             clock-names = "bus",
 141                           "nrt_bus",
 142                           "iface",
 143                           "lut",
 144                           "core",
 145                           "vsync";
 146
 147             interrupt-parent = <&mdss>;
 148             interrupts = <0>;
 149             power-domains = <&rpmhpd SC7280_CX>;
 150             operating-points-v2 = <&mdp_opp_table>;
 151
 152             ports {
 153                 #address-cells = <1>;
 154                 #size-cells = <0>;
 155
 156                 port@0 {
 157                     reg = <0>;
 158                     dpu_intf1_out: endpoint {
 159                         remote-endpoint = <&dsi0_in>;
 160                     };
 161                 };
 162
 163                 port@1 {
 164                     reg = <1>;
 165                     dpu_intf5_out: endpoint {
 166                         remote-endpoint = <&edp_in>;
 167                     };
 168                 };
 169
 170                 port@2 {
 171                     reg = <2>;
 172                     dpu_intf0_out: endpoint {
 173                         remote-endpoint = <&dp_in>;
 174                     };
 175                 };
 176             };
 177         };
 178
 179         dsi@ae94000 {
 180             compatible = "qcom,sc7280-dsi-ctrl", "qcom,mdss-dsi-ctrl";
 181             reg = <0x0ae94000 0x400>;
 182             reg-names = "dsi_ctrl";
 183
 184             interrupt-parent = <&mdss>;
 185             interrupts = <4>;
 186
 187             clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
 188                      <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
 189                      <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
 190                      <&dispcc DISP_CC_MDSS_ESC0_CLK>,
 191                      <&dispcc DISP_CC_MDSS_AHB_CLK>,
 192                      <&gcc GCC_DISP_HF_AXI_CLK>;
 193             clock-names = "byte",
 194                           "byte_intf",
 195                           "pixel",
 196                           "core",
 197                           "iface",
 198                           "bus";
 199
 200             assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
 201                               <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
 202             assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>;
 203
 204             operating-points-v2 = <&dsi_opp_table>;
 205             power-domains = <&rpmhpd SC7280_CX>;
 206
 207             phys = <&mdss_dsi_phy>;
 208             phy-names = "dsi";
 209
 210             #address-cells = <1>;
 211             #size-cells = <0>;
 212
 213             ports {
 214                 #address-cells = <1>;
 215                 #size-cells = <0>;
 216
 217                 port@0 {
 218                     reg = <0>;
 219                     dsi0_in: endpoint {
 220                         remote-endpoint = <&dpu_intf1_out>;
 221                     };
 222                 };
 223
 224                 port@1 {
 225                     reg = <1>;
 226                     dsi0_out: endpoint {
 227                     };
 228                 };
 229             };
 230
 231             dsi_opp_table: opp-table {
 232                 compatible = "operating-points-v2";
 233
 234                 opp-187500000 {
 235                     opp-hz = /bits/ 64 <187500000>;
 236                     required-opps = <&rpmhpd_opp_low_svs>;
 237                 };
 238
 239                 opp-300000000 {
 240                     opp-hz = /bits/ 64 <300000000>;
 241                     required-opps = <&rpmhpd_opp_svs>;
 242                 };
 243
 244                 opp-358000000 {
 245                     opp-hz = /bits/ 64 <358000000>;
 246                     required-opps = <&rpmhpd_opp_svs_l1>;
 247                 };
 248             };
 249         };
 250
 251         mdss_dsi_phy: phy@ae94400 {
 252             compatible = "qcom,sc7280-dsi-phy-7nm";
 253             reg = <0x0ae94400 0x200>,
 254                   <0x0ae94600 0x280>,
 255                   <0x0ae94900 0x280>;
 256             reg-names = "dsi_phy",
 257                         "dsi_phy_lane",
 258                         "dsi_pll";
 259
 260             #clock-cells = <1>;
 261             #phy-cells = <0>;
 262
 263             clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
 264                      <&rpmhcc RPMH_CXO_CLK>;
 265             clock-names = "iface", "ref";
 266
 267             vdds-supply = <&vreg_dsi_supply>;
 268         };
 269
 270         edp@aea0000 {
 271             compatible = "qcom,sc7280-edp";
 272             pinctrl-names = "default";
 273             pinctrl-0 = <&edp_hot_plug_det>;
 274
 275             reg = <0xaea0000 0x200>,
 276                   <0xaea0200 0x200>,
 277                   <0xaea0400 0xc00>,
 278                   <0xaea1000 0x400>;
 279
 280             interrupt-parent = <&mdss>;
 281             interrupts = <14>;
 282
 283             clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
 284                      <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>,
 285                      <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>,
 286                      <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>,
 287                      <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>;
 288             clock-names = "core_iface",
 289                           "core_aux",
 290                           "ctrl_link",
 291                           "ctrl_link_iface",
 292                           "stream_pixel";
 293             assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
 294                               <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>;
 295             assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
 296
 297             phys = <&mdss_edp_phy>;
 298             phy-names = "dp";
 299
 300             operating-points-v2 = <&edp_opp_table>;
 301             power-domains = <&rpmhpd SC7280_CX>;
 302
 303             ports {
 304                 #address-cells = <1>;
 305                 #size-cells = <0>;
 306
 307                 port@0 {
 308                     reg = <0>;
 309                     edp_in: endpoint {
 310                         remote-endpoint = <&dpu_intf5_out>;
 311                     };
 312                 };
 313
 314                 port@1 {
 315                     reg = <1>;
 316                     mdss_edp_out: endpoint { };
 317                 };
 318             };
 319
 320             edp_opp_table: opp-table {
 321                 compatible = "operating-points-v2";
 322
 323                 opp-160000000 {
 324                     opp-hz = /bits/ 64 <160000000>;
 325                     required-opps = <&rpmhpd_opp_low_svs>;
 326                 };
 327
 328                 opp-270000000 {
 329                     opp-hz = /bits/ 64 <270000000>;
 330                     required-opps = <&rpmhpd_opp_svs>;
 331                 };
 332
 333                 opp-540000000 {
 334                     opp-hz = /bits/ 64 <540000000>;
 335                     required-opps = <&rpmhpd_opp_nom>;
 336                 };
 337
 338                 opp-810000000 {
 339                     opp-hz = /bits/ 64 <810000000>;
 340                     required-opps = <&rpmhpd_opp_nom>;
 341                 };
 342             };
 343         };
 344
 345         mdss_edp_phy: phy@aec2a00 {
 346             compatible = "qcom,sc7280-edp-phy";
 347
 348             reg = <0xaec2a00 0x19c>,
 349                   <0xaec2200 0xa0>,
 350                   <0xaec2600 0xa0>,
 351                   <0xaec2000 0x1c0>;
 352
 353             clocks = <&rpmhcc RPMH_CXO_CLK>,
 354                      <&gcc GCC_EDP_CLKREF_EN>;
 355             clock-names = "aux",
 356                           "cfg_ahb";
 357
 358             #clock-cells = <1>;
 359             #phy-cells = <0>;
 360         };
 361
 362         displayport-controller@ae90000 {
 363             compatible = "qcom,sc7280-dp";
 364
 365             reg = <0xae90000 0x200>,
 366                   <0xae90200 0x200>,
 367                   <0xae90400 0xc00>,
 368                   <0xae91000 0x400>,
 369                   <0xae91400 0x400>;
 370
 371             interrupt-parent = <&mdss>;
 372             interrupts = <12>;
 373
 374             clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
 375                      <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
 376                      <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
 377                      <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
 378                      <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
 379             clock-names = "core_iface",
 380                           "core_aux",
 381                           "ctrl_link",
 382                           "ctrl_link_iface",
 383                           "stream_pixel";
 384             assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
 385                               <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
 386             assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
 387             phys = <&dp_phy>;
 388             phy-names = "dp";
 389
 390             operating-points-v2 = <&dp_opp_table>;
 391             power-domains = <&rpmhpd SC7280_CX>;
 392
 393             #sound-dai-cells = <0>;
 394
 395             ports {
 396                 #address-cells = <1>;
 397                 #size-cells = <0>;
 398
 399                 port@0 {
 400                     reg = <0>;
 401                     dp_in: endpoint {
 402                         remote-endpoint = <&dpu_intf0_out>;
 403                     };
 404                 };
 405
 406                 port@1 {
 407                     reg = <1>;
 408                     dp_out: endpoint { };
 409                 };
 410             };
 411
 412             dp_opp_table: opp-table {
 413                 compatible = "operating-points-v2";
 414
 415                 opp-160000000 {
 416                     opp-hz = /bits/ 64 <160000000>;
 417                     required-opps = <&rpmhpd_opp_low_svs>;
 418                 };
 419
 420                 opp-270000000 {
 421                     opp-hz = /bits/ 64 <270000000>;
 422                     required-opps = <&rpmhpd_opp_svs>;
 423                 };
 424
 425                 opp-540000000 {
 426                     opp-hz = /bits/ 64 <540000000>;
 427                     required-opps = <&rpmhpd_opp_svs_l1>;
 428                 };
 429
 430                 opp-810000000 {
 431                     opp-hz = /bits/ 64 <810000000>;
 432                     required-opps = <&rpmhpd_opp_nom>;
 433                 };
 434             };
 435         };
 436     };
 437 ...