Bindings/net/stm32-dwmac.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2 # Copyright 2019 BayLibre, SAS
   3 %YAML 1.2
   4 ---
   5 $id: http://devicetree.org/schemas/net/stm32-dwmac.yaml#
   6 $schema: http://devicetree.org/meta-schemas/core.yaml#
   7
   8 title: STMicroelectronics STM32 / MCU DWMAC glue layer controller
   9
  10 maintainers:
  11   - Alexandre Torgue <alexandre.torgue@foss.st.com>
  12   - Christophe Roullier <christophe.roullier@foss.st.com>
  13
  14 description:
  15   This file documents platform glue layer for stmmac.
  16
  17 # We need a select here so we don't match all nodes with 'snps,dwmac'
  18 select:
  19   properties:
  20     compatible:
  21       contains:
  22         enum:
  23           - st,stm32-dwmac
  24           - st,stm32mp1-dwmac
  25   required:
  26     - compatible
  27
  28 allOf:
  29   - $ref: snps,dwmac.yaml#
  30
  31 properties:
  32   compatible:
  33     oneOf:
  34       - items:
  35           - enum:
  36               - st,stm32mp1-dwmac
  37           - const: snps,dwmac-4.20a
  38       - items:
  39           - enum:
  40               - st,stm32-dwmac
  41           - const: snps,dwmac-4.10a
  42       - items:
  43           - enum:
  44               - st,stm32-dwmac
  45           - const: snps,dwmac-3.50a
  46
  47   reg: true
  48
  49   reg-names:
  50     items:
  51       - const: stmmaceth
  52
  53   clocks:
  54     minItems: 3
  55     items:
  56       - description: GMAC main clock
  57       - description: MAC TX clock
  58       - description: MAC RX clock
  59       - description: For MPU family, used for power mode
  60       - description: For MPU family, used for PHY without quartz
  61       - description: PTP clock
  62
  63   clock-names:
  64     minItems: 3
  65     maxItems: 6
  66     contains:
  67       enum:
  68         - stmmaceth
  69         - mac-clk-tx
  70         - mac-clk-rx
  71         - ethstp
  72         - eth-ck
  73         - ptp_ref
  74
  75   st,syscon:
  76     $ref: /schemas/types.yaml#/definitions/phandle-array
  77     items:
  78       - items:
  79           - description: phandle to the syscon node which encompases the glue register
  80           - description: offset of the control register
  81     description:
  82       Should be phandle/offset pair. The phandle to the syscon node which
  83       encompases the glue register, and the offset of the control register
  84
  85   st,eth-clk-sel:
  86     description:
  87       set this property in RGMII PHY when you want to select RCC clock instead of ETH_CLK125.
  88     type: boolean
  89
  90   st,eth-ref-clk-sel:
  91     description:
  92       set this property in RMII mode when you have PHY without crystal 50MHz and want to
  93       select RCC clock instead of ETH_REF_CLK.
  94     type: boolean
  95
  96 required:
  97   - compatible
  98   - clocks
  99   - clock-names
 100   - st,syscon
 101
 102 unevaluatedProperties: false
 103
 104 examples:
 105   - |
 106     #include <dt-bindings/interrupt-controller/arm-gic.h>
 107     #include <dt-bindings/clock/stm32mp1-clks.h>
 108     #include <dt-bindings/reset/stm32mp1-resets.h>
 109     #include <dt-bindings/mfd/stm32h7-rcc.h>
 110     //Example 1
 111      ethernet0: ethernet@5800a000 {
 112            compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
 113            reg = <0x5800a000 0x2000>;
 114            reg-names = "stmmaceth";
 115            interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 116            interrupt-names = "macirq";
 117            clock-names = "stmmaceth",
 118                      "mac-clk-tx",
 119                      "mac-clk-rx",
 120                      "ethstp",
 121                      "eth-ck";
 122            clocks = <&rcc ETHMAC>,
 123                 <&rcc ETHTX>,
 124                 <&rcc ETHRX>,
 125                 <&rcc ETHSTP>,
 126                 <&rcc ETHCK_K>;
 127            st,syscon = <&syscfg 0x4>;
 128            snps,pbl = <2>;
 129            snps,axi-config = <&stmmac_axi_config_0>;
 130            snps,tso;
 131            phy-mode = "rgmii";
 132        };
 133
 134   - |
 135     //Example 2 (MCU example)
 136      ethernet1: ethernet@40028000 {
 137            compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
 138            reg = <0x40028000 0x8000>;
 139            reg-names = "stmmaceth";
 140            interrupts = <0 61 0>, <0 62 0>;
 141            interrupt-names = "macirq", "eth_wake_irq";
 142            clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
 143            clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
 144            st,syscon = <&syscfg 0x4>;
 145            snps,pbl = <8>;
 146            snps,mixed-burst;
 147            phy-mode = "mii";
 148        };
 149
 150   - |
 151     //Example 3
 152      ethernet2: ethernet@40027000 {
 153            compatible = "st,stm32-dwmac", "snps,dwmac-4.10a";
 154            reg = <0x40028000 0x8000>;
 155            reg-names = "stmmaceth";
 156            interrupts = <61>;
 157            interrupt-names = "macirq";
 158            clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
 159            clocks = <&rcc 62>, <&rcc 61>, <&rcc 60>;
 160            st,syscon = <&syscfg 0x4>;
 161            snps,pbl = <8>;
 162            phy-mode = "mii";
 163        };