Bindings/pinctrl/renesas,rzg2l-pinctrl.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Renesas RZ/{G2L,V2L} combined Pin and GPIO controller
   8
   9 maintainers:
  10   - Geert Uytterhoeven <geert+renesas@glider.be>
  11   - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
  12
  13 description:
  14   The Renesas SoCs of the RZ/{G2L,V2L} alike series feature a combined Pin and
  15   GPIO controller.
  16   Pin multiplexing and GPIO configuration is performed on a per-pin basis.
  17   Each port features up to 8 pins, each of them configurable for GPIO function
  18   (port mode) or in alternate function mode.
  19   Up to 8 different alternate function modes exist for each single pin.
  20
  21 properties:
  22   compatible:
  23     oneOf:
  24       - items:
  25           - enum:
  26               - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five
  27               - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
  28               - renesas,r9a08g045-pinctrl # RZ/G3S
  29
  30       - items:
  31           - enum:
  32               - renesas,r9a07g054-pinctrl     # RZ/V2L
  33           - const: renesas,r9a07g044-pinctrl  # RZ/G2{L,LC} fallback for RZ/V2L
  34
  35   reg:
  36     maxItems: 1
  37
  38   gpio-controller: true
  39
  40   '#gpio-cells':
  41     const: 2
  42     description:
  43       The first cell contains the global GPIO port index, constructed using the
  44       RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h> and the
  45       second cell represents consumer flag as mentioned in ../gpio/gpio.txt
  46       E.g. "RZG2L_GPIO(39, 1)" for P39_1.
  47
  48   gpio-ranges:
  49     maxItems: 1
  50
  51   interrupt-controller: true
  52
  53   '#interrupt-cells':
  54     const: 2
  55     description:
  56       The first cell contains the global GPIO port index, constructed using the
  57       RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h> and the
  58       second cell is used to specify the flag.
  59       E.g. "interrupts = <RZG2L_GPIO(43, 0) IRQ_TYPE_EDGE_FALLING>;" if P43_0 is
  60       being used as an interrupt.
  61
  62   clocks:
  63     maxItems: 1
  64
  65   power-domains:
  66     maxItems: 1
  67
  68   resets:
  69     items:
  70       - description: GPIO_RSTN signal
  71       - description: GPIO_PORT_RESETN signal
  72       - description: GPIO_SPARE_RESETN signal
  73
  74 additionalProperties:
  75   anyOf:
  76     - type: object
  77       additionalProperties: false
  78       allOf:
  79         - $ref: pincfg-node.yaml#
  80         - $ref: pinmux-node.yaml#
  81
  82         - if:
  83             properties:
  84               compatible:
  85                 contains:
  86                   enum:
  87                     - renesas,r9a08g045-pinctrl
  88           then:
  89             properties:
  90               drive-strength: false
  91               output-impedance-ohms: false
  92               slew-rate: false
  93           else:
  94             properties:
  95               drive-strength-microamp: false
  96
  97       description:
  98         Pin controller client devices use pin configuration subnodes (children
  99         and grandchildren) for desired pin configuration.
 100         Client device subnodes use below standard properties.
 101
 102       properties:
 103         pinmux:
 104           description:
 105             Values are constructed from GPIO port number, pin number, and
 106             alternate function configuration number using the RZG2L_PORT_PINMUX()
 107             helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h>.
 108         pins: true
 109         drive-strength:
 110           enum: [ 2, 4, 8, 12 ]
 111         drive-strength-microamp:
 112           enum: [ 1900, 2200, 4000, 4400, 4500, 4700, 5200, 5300, 5700,
 113                   5800, 6000, 6050, 6100, 6550, 6800, 7000, 8000, 9000,
 114                   10000 ]
 115         output-impedance-ohms:
 116           enum: [ 33, 50, 66, 100 ]
 117         power-source:
 118           description: I/O voltage in millivolt.
 119           enum: [ 1800, 2500, 3300 ]
 120         slew-rate: true
 121         gpio-hog: true
 122         gpios: true
 123         input-enable: true
 124         output-high: true
 125         output-low: true
 126         line-name: true
 127
 128     - type: object
 129       additionalProperties:
 130         $ref: "#/additionalProperties/anyOf/0"
 131
 132 allOf:
 133   - $ref: pinctrl.yaml#
 134
 135 required:
 136   - compatible
 137   - reg
 138   - gpio-controller
 139   - '#gpio-cells'
 140   - gpio-ranges
 141   - interrupt-controller
 142   - '#interrupt-cells'
 143   - clocks
 144   - power-domains
 145   - resets
 146
 147 examples:
 148   - |
 149     #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
 150     #include <dt-bindings/clock/r9a07g044-cpg.h>
 151
 152     pinctrl: pinctrl@11030000 {
 153             compatible = "renesas,r9a07g044-pinctrl";
 154             reg = <0x11030000 0x10000>;
 155
 156             gpio-controller;
 157             #gpio-cells = <2>;
 158             gpio-ranges = <&pinctrl 0 0 392>;
 159             interrupt-controller;
 160             #interrupt-cells = <2>;
 161             clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
 162             resets = <&cpg R9A07G044_GPIO_RSTN>,
 163                      <&cpg R9A07G044_GPIO_PORT_RESETN>,
 164                      <&cpg R9A07G044_GPIO_SPARE_RESETN>;
 165             power-domains = <&cpg>;
 166
 167             scif0_pins: serial0 {
 168                     pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* Tx */
 169                              <RZG2L_PORT_PINMUX(38, 1, 1)>; /* Rx */
 170             };
 171
 172             i2c1_pins: i2c1 {
 173                     pins = "RIIC1_SDA", "RIIC1_SCL";
 174                     input-enable;
 175             };
 176
 177             sd1-pwr-en-hog {
 178                     gpio-hog;
 179                     gpios = <RZG2L_GPIO(39, 2) 0>;
 180                     output-high;
 181                     line-name = "sd1_pwr_en";
 182             };
 183
 184             sdhi1_pins: sd1 {
 185                     sd1_mux {
 186                             pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>, /* CD */
 187                                      <RZG2L_PORT_PINMUX(19, 1, 1)>; /* WP */
 188                             power-source  = <3300>;
 189                     };
 190
 191                     sd1_data {
 192                             pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
 193                             power-source  = <3300>;
 194                     };
 195
 196                     sd1_ctrl {
 197                             pins = "SD1_CLK", "SD1_CMD";
 198                             power-source  = <3300>;
 199                     };
 200             };
 201     };