5 config CREATE_ARCH_SYMLINK
8 config HAVE_ARCH_IOREMAP
11 config SYS_CACHE_SHIFT_4
14 config SYS_CACHE_SHIFT_5
17 config SYS_CACHE_SHIFT_6
20 config SYS_CACHE_SHIFT_7
29 config SYS_CACHELINE_SIZE
31 default 128 if SYS_CACHE_SHIFT_7
32 default 64 if SYS_CACHE_SHIFT_6
33 default 32 if SYS_CACHE_SHIFT_5
34 default 16 if SYS_CACHE_SHIFT_4
38 config LINKER_LIST_ALIGN
41 default 8 if ARM64 || X86
44 Force the each linker list to be aligned to this boundary. This
45 is required if ll_entry_get() is used, since otherwise the linker
46 may add padding into the table, thus breaking it.
47 See linker_lists.rst for full details.
50 prompt "Architecture select"
54 bool "ARC architecture"
58 select HAVE_PRIVATE_LIBGCC
59 select SUPPORT_OF_CONTROL
60 select SYS_CACHE_SHIFT_7
62 select SYS_BIG_ENDIAN if CPU_BIG_ENDIAN
63 select SYS_LITTLE_ENDIAN if !CPU_BIG_ENDIAN
66 bool "ARM architecture"
67 select ARCH_SUPPORTS_LTO
68 select CREATE_ARCH_SYMLINK
69 select HAVE_PRIVATE_LIBGCC if !ARM64
71 select SUPPORT_OF_CONTROL
74 bool "M68000 architecture"
75 select HAVE_PRIVATE_LIBGCC
76 select USE_PRIVATE_LIBGCC
77 select SYS_BOOT_GET_CMDLINE
78 select SYS_BOOT_GET_KBD
79 select SYS_CACHE_SHIFT_4
80 select SUPPORT_OF_CONTROL
83 bool "MicroBlaze architecture"
84 select SUPPORT_OF_CONTROL
86 imply SPL_REGMAP if SPL
87 imply SPL_TIMER if SPL
92 bool "MIPS architecture"
93 select HAVE_ARCH_IOREMAP
94 select HAVE_PRIVATE_LIBGCC
95 select SUPPORT_OF_CONTROL
96 select SPL_SEPARATE_BSS if SPL
99 bool "Nios II architecture"
104 select SUPPORT_OF_CONTROL
108 bool "PowerPC architecture"
109 select HAVE_PRIVATE_LIBGCC
110 select SUPPORT_OF_CONTROL
111 select SYS_BOOT_GET_CMDLINE
112 select SYS_BOOT_GET_KBD
115 bool "RISC-V architecture"
116 select CREATE_ARCH_SYMLINK
118 select SUPPORT_OF_CONTROL
122 imply SPL_SEPARATE_BSS if SPL
134 imply SPL_LIBCOMMON_SUPPORT
135 imply SPL_LIBGENERIC_SUPPORT
141 select ARCH_SUPPORTS_LTO
142 select BOARD_LATE_INIT
144 select CMD_POWEROFF if CMDLINE
147 select DM_FUZZING_ENGINE
155 select GZIP_COMPRESSED
159 select OF_BOARD_SETUP
162 select SUPPORT_OF_CONTROL
163 select SYSRESET_CMD_POWEROFF if CMD_POWEROFF
164 select SYS_CACHE_SHIFT_4
166 select SUPPORT_EXTENSION_SCAN if CMDLINE
183 imply FUZZING_ENGINE_SANDBOX
190 imply PARTITION_TYPE_GUID
193 imply UDP_FUNCTION_FASTBOOT
207 imply ACPI_PMC_SANDBOX
217 imply GENERATE_ACPI_TABLE
221 imply BOOTSTD_DEFAULTS if BOOTSTD_FULL && CMDLINE
222 imply BOOTMETH_DISTRO if BOOTSTD_FULL && CMDLINE
223 imply CMD_SYSBOOT if BOOTSTD_FULL
226 bool "SuperH architecture"
227 select HAVE_PRIVATE_LIBGCC
228 select SUPPORT_OF_CONTROL
231 bool "x86 architecture"
234 select CREATE_ARCH_SYMLINK
236 select HAVE_ARCH_IOMAP
237 select HAVE_PRIVATE_LIBGCC
241 select SUPPORT_OF_CONTROL
242 select SYS_CACHE_SHIFT_6
244 select USE_PRIVATE_LIBGCC
247 imply HAS_ROM if X86_RESET_VECTOR
250 imply CMD_FPGA_LOADMK
267 imply LAST_STAGE_INIT
273 imply USB_ETHER_SMSC95XX
279 imply ACPIGEN if !QEMU && !EFI_APP
280 imply SYSINFO if GENERATE_SMBIOS_TABLE
281 imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE
284 # Thing to enable for when SPL/TPL are enabled: SPL
287 imply SPL_DRIVERS_MISC
290 imply SPL_LIBCOMMON_SUPPORT
291 imply SPL_LIBGENERIC_SUPPORT
293 imply SPL_SPI_FLASH_SUPPORT
301 imply TPL_DRIVERS_MISC
304 imply TPL_LIBCOMMON_SUPPORT
305 imply TPL_LIBGENERIC_SUPPORT
313 bool "Xtensa architecture"
314 select CREATE_ARCH_SYMLINK
315 select SUPPORT_OF_CONTROL
322 This option should contain the architecture name to build the
323 appropriate arch/<CONFIG_SYS_ARCH> directory.
324 All the architectures should specify this option correctly.
329 This option should contain the CPU name to build the correct
330 arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU> directory.
332 This is optional. For those targets without the CPU directory,
333 leave this option empty.
338 This option should contain the SoC name to build the directory
339 arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU>/<CONFIG_SYS_SOC>.
341 This is optional. For those targets without the SoC directory,
342 leave this option empty.
347 This option should contain the vendor name of the target board.
349 board/<CONFIG_SYS_VENDOR>/common/Makefile exists, the vendor common
350 directory is compiled.
351 If CONFIG_SYS_BOARD is also set, the sources under
352 board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> directory are compiled.
354 This is optional. For those targets without the vendor directory,
355 leave this option empty.
360 This option should contain the name of the target board.
361 If it is set, either board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD>
362 or board/<CONFIG_SYS_BOARD> directory is compiled depending on
363 whether CONFIG_SYS_VENDOR is set or not.
365 This is optional. For those targets without the board directory,
366 leave this option empty.
368 config SYS_CONFIG_NAME
369 string "Board header file" if ARCH_MESON || ARCH_VERSAL || \
370 ARCH_VERSAL_NET || ARCH_ZYNQ || ARCH_ZYNQMP || \
371 ARCH_ZYNQMP_R5 || MICROBLAZE || NIOS2
372 default "meson64" if ARCH_MESON
373 default "microblaze-generic" if MICROBLAZE
374 default "xilinx_versal" if ARCH_VERSAL
375 default "xilinx_versal_net" if ARCH_VERSAL_NET
376 default "xilinx_zynqmp" if ARCH_ZYNQMP
377 default "xilinx_zynqmp_r5" if ARCH_ZYNQMP_R5
378 default "zynq-common" if ARCH_ZYNQ
380 This option should contain the base name of board header file.
381 The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h
382 should be included from include/config.h.
384 config SYS_DISABLE_DCACHE_OPS
387 This option disables dcache flush and dcache invalidation
388 operations. For example, on coherent systems where cache
389 operatios are not required, enable this option to avoid them.
390 Note that, its up to the individual architectures to implement
394 hex "Address for the Internal Memory-Mapped Registers (IMMR) window"
395 depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A
396 default 0xFF000000 if MPC8xx
397 default 0xF0000000 if ARCH_MPC8313
398 default 0xE0000000 if MPC83xx && !ARCH_MPC8313
399 default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
400 default 0xFFE00000 if ARCH_P1010 || ARCH_P1011 || ARCH_P1020 || \
401 ARCH_P1021 || ARCH_P1024 || ARCH_P1025 || \
403 default SYS_CCSRBAR_DEFAULT
405 Address for the Internal Memory-Mapped Registers (IMMR) window used
406 to configure the features of many Freescale / NXP SoCs.
408 config MONITOR_IS_IN_RAM
409 bool "U-Boot is loaded in to RAM by a pre-loader"
410 depends on M68K || NIOS2
412 menu "Skipping low level initialization functions"
413 depends on ARM || MIPS || RISCV
415 config SKIP_LOWLEVEL_INIT
416 bool "Skip calls to certain low level initialization functions"
418 If enabled, then certain low level initializations (like setting up
419 the memory controller) are omitted and/or U-Boot does not relocate
421 Normally this variable MUST NOT be defined. The only exception is
422 when U-Boot is loaded (to RAM) by some other boot loader or by a
423 debugger which performs these initializations itself.
425 config SPL_SKIP_LOWLEVEL_INIT
426 bool "Skip calls to certain low level initialization functions in SPL"
429 If enabled, then certain low level initializations (like setting up
430 the memory controller) are omitted and/or U-Boot does not relocate
432 Normally this variable MUST NOT be defined. The only exception is
433 when U-Boot is loaded (to RAM) by some other boot loader or by a
434 debugger which performs these initializations itself.
436 config TPL_SKIP_LOWLEVEL_INIT
437 bool "Skip calls to certain low level initialization functions in TPL"
438 depends on SPL && ARM
440 If enabled, then certain low level initializations (like setting up
441 the memory controller) are omitted and/or U-Boot does not relocate
443 Normally this variable MUST NOT be defined. The only exception is
444 when U-Boot is loaded (to RAM) by some other boot loader or by a
445 debugger which performs these initializations itself.
447 config SKIP_LOWLEVEL_INIT_ONLY
448 bool "Skip call to lowlevel_init during early boot ONLY"
451 This allows just the call to lowlevel_init() to be skipped. The
452 normal CP15 init (such as enabling the instruction cache) is still
455 config SPL_SKIP_LOWLEVEL_INIT_ONLY
456 bool "Skip call to lowlevel_init during early SPL boot ONLY"
457 depends on SPL && ARM
459 This allows just the call to lowlevel_init() to be skipped. The
460 normal CP15 init (such as enabling the instruction cache) is still
463 config TPL_SKIP_LOWLEVEL_INIT_ONLY
464 bool "Skip call to lowlevel_init during early TPL boot ONLY"
465 depends on TPL && ARM
467 This allows just the call to lowlevel_init() to be skipped. The
468 normal CP15 init (such as enabling the instruction cache) is still
473 config SYS_HAS_NONCACHED_MEMORY
474 bool "Enable reserving a non-cached memory area for drivers"
475 depends on (ARM || MIPS) && (RTL8169 || MEDIATEK_ETH)
477 This is useful for drivers that would otherwise require a lot of
478 explicit cache maintenance. For some drivers it's also impossible to
479 properly maintain the cache. For example if the regions that need to
480 be flushed are not a multiple of the cache-line size, *and* padding
481 cannot be allocated between the regions to align them (i.e. if the
482 HW requires a contiguous array of regions, and the size of each
483 region is not cache-aligned), then a flush of one region may result
484 in overwriting data that hardware has written to another region in
485 the same cache-line. This can happen for example in network drivers
486 where descriptors for buffers are typically smaller than the CPU
487 cache-line (e.g. 16 bytes vs. 32 or 64 bytes).
489 config SYS_NONCACHED_MEMORY
490 hex "Size in bytes of the non-cached memory area"
491 depends on SYS_HAS_NONCACHED_MEMORY
494 Size of non-cached memory area. This area of memory will be typically
495 located right below the malloc() area and mapped uncached in the MMU.
497 source "arch/arc/Kconfig"
498 source "arch/arm/Kconfig"
499 source "arch/m68k/Kconfig"
500 source "arch/microblaze/Kconfig"
501 source "arch/mips/Kconfig"
502 source "arch/nios2/Kconfig"
503 source "arch/powerpc/Kconfig"
504 source "arch/sandbox/Kconfig"
505 source "arch/sh/Kconfig"
506 source "arch/x86/Kconfig"
507 source "arch/xtensa/Kconfig"
508 source "arch/riscv/Kconfig"
510 if ARM || M68K || PPC
512 source "arch/Kconfig.nxp"
516 source "board/keymile/Kconfig"
518 if MIPS || MICROBLAZE
521 prompt "Endianness selection"
523 Some MIPS boards can be configured for either little or big endian
524 byte order. These modes require different U-Boot images. In general there
525 is one preferred byteorder for a particular system but some systems are
526 just as commonly used in the one or the other endianness.
528 config SYS_BIG_ENDIAN
530 depends on (SUPPORTS_BIG_ENDIAN && MIPS) || MICROBLAZE
532 config SYS_LITTLE_ENDIAN
534 depends on (SUPPORTS_LITTLE_ENDIAN && MIPS) || MICROBLAZE