arch/Kconfig

   1 config ARCH_MAP_SYSMEM
   2         depends on SANDBOX
   3         def_bool y
   4
   5 config CREATE_ARCH_SYMLINK
   6         bool
   7
   8 config HAVE_ARCH_IOREMAP
   9         bool
  10
  11 config SYS_CACHE_SHIFT_4
  12         bool
  13
  14 config SYS_CACHE_SHIFT_5
  15         bool
  16
  17 config SYS_CACHE_SHIFT_6
  18         bool
  19
  20 config SYS_CACHE_SHIFT_7
  21         bool
  22
  23 config SYS_CACHELINE_SIZE
  24         int
  25         default 128 if SYS_CACHE_SHIFT_7
  26         default 64 if SYS_CACHE_SHIFT_6
  27         default 32 if SYS_CACHE_SHIFT_5
  28         default 16 if SYS_CACHE_SHIFT_4
  29         # Fall-back for MIPS
  30         default 32 if MIPS
  31
  32 config LINKER_LIST_ALIGN
  33         int
  34         default 32 if SANDBOX
  35         default 8 if ARM64 || X86
  36         default 4
  37         help
  38           Force the each linker list to be aligned to this boundary. This
  39           is required if ll_entry_get() is used, since otherwise the linker
  40           may add padding into the table, thus breaking it.
  41           See linker_lists.rst for full details.
  42
  43 choice
  44         prompt "Architecture select"
  45         default SANDBOX
  46
  47 config ARC
  48         bool "ARC architecture"
  49         select ARC_TIMER
  50         select CLK
  51         select DM
  52         select HAVE_PRIVATE_LIBGCC
  53         select SUPPORT_OF_CONTROL
  54         select SYS_CACHE_SHIFT_7
  55         select TIMER
  56         select SYS_BIG_ENDIAN if CPU_BIG_ENDIAN
  57         select SYS_LITTLE_ENDIAN if !CPU_BIG_ENDIAN
  58
  59 config ARM
  60         bool "ARM architecture"
  61         select ARCH_SUPPORTS_LTO
  62         select CREATE_ARCH_SYMLINK
  63         select HAVE_PRIVATE_LIBGCC if !ARM64
  64         select SUPPORT_ACPI
  65         select SUPPORT_OF_CONTROL
  66
  67 config M68K
  68         bool "M68000 architecture"
  69         select HAVE_PRIVATE_LIBGCC
  70         select USE_PRIVATE_LIBGCC
  71         select SYS_BOOT_GET_CMDLINE
  72         select SYS_BOOT_GET_KBD
  73         select SYS_CACHE_SHIFT_4
  74         select SUPPORT_OF_CONTROL
  75
  76 config MICROBLAZE
  77         bool "MicroBlaze architecture"
  78         select SUPPORT_OF_CONTROL
  79         imply CMD_TIMER
  80         imply SPL_REGMAP if SPL
  81         imply SPL_TIMER if SPL
  82         imply TIMER
  83         imply XILINX_TIMER
  84
  85 config MIPS
  86         bool "MIPS architecture"
  87         select HAVE_ARCH_IOREMAP
  88         select HAVE_PRIVATE_LIBGCC
  89         select SUPPORT_OF_CONTROL
  90         select SPL_SEPARATE_BSS if SPL
  91
  92 config NIOS2
  93         bool "Nios II architecture"
  94         select CPU
  95         select DM
  96         select DM_EVENT
  97         select OF_CONTROL
  98         select SUPPORT_OF_CONTROL
  99         imply CMD_DM
 100
 101 config PPC
 102         bool "PowerPC architecture"
 103         select HAVE_PRIVATE_LIBGCC
 104         select SUPPORT_OF_CONTROL
 105         select SYS_BOOT_GET_CMDLINE
 106         select SYS_BOOT_GET_KBD
 107
 108 config RISCV
 109         bool "RISC-V architecture"
 110         select CREATE_ARCH_SYMLINK
 111         select SUPPORT_OF_CONTROL
 112         select OF_CONTROL
 113         select DM
 114         select DM_EVENT
 115         imply SPL_SEPARATE_BSS if SPL
 116         imply DM_SERIAL
 117         imply DM_MMC
 118         imply DM_SPI
 119         imply DM_SPI_FLASH
 120         imply BLK
 121         imply CLK
 122         imply MTD
 123         imply TIMER
 124         imply CMD_DM
 125         imply SPL_DM
 126         imply SPL_OF_CONTROL
 127         imply SPL_LIBCOMMON_SUPPORT
 128         imply SPL_LIBGENERIC_SUPPORT
 129         imply SPL_SERIAL
 130         imply SPL_TIMER
 131
 132 config SANDBOX
 133         bool "Sandbox"
 134         select ARCH_SUPPORTS_LTO
 135         select BOARD_LATE_INIT
 136         select BZIP2
 137         select CMD_POWEROFF if CMDLINE
 138         select DM
 139         select DM_EVENT
 140         select DM_FUZZING_ENGINE
 141         select DM_GPIO
 142         select DM_I2C
 143         select DM_KEYBOARD
 144         select DM_MMC
 145         select DM_SERIAL
 146         select DM_SPI
 147         select DM_SPI_FLASH
 148         select GZIP_COMPRESSED
 149         select IO_TRACE
 150         select LZO
 151         select OF_BOARD_SETUP
 152         select PCI_ENDPOINT
 153         select SPI
 154         select SUPPORT_OF_CONTROL
 155         select SYSRESET_CMD_POWEROFF if CMD_POWEROFF
 156         select SYS_CACHE_SHIFT_4
 157         select IRQ
 158         select SUPPORT_EXTENSION_SCAN if CMDLINE
 159         select SUPPORT_ACPI
 160         imply BITREVERSE
 161         select BLOBLIST
 162         imply LTO
 163         imply CMD_DM
 164         imply CMD_EXCEPTION
 165         imply CMD_GETTIME
 166         imply CMD_HASH
 167         imply CMD_IO
 168         imply CMD_IOTRACE
 169         imply CMD_LZMADEC
 170         imply CMD_SF
 171         imply CMD_SF_TEST
 172         imply CRC32_VERIFY
 173         imply FAT_WRITE
 174         imply FIRMWARE
 175         imply FUZZING_ENGINE_SANDBOX
 176         imply HASH_VERIFY
 177         imply LZMA
 178         imply TEE
 179         imply AVB_VERIFY
 180         imply LIBAVB
 181         imply CMD_AVB
 182         imply PARTITION_TYPE_GUID
 183         imply SCP03
 184         imply CMD_SCP03
 185         imply UDP_FUNCTION_FASTBOOT
 186         imply VIRTIO_MMIO
 187         imply VIRTIO_PCI
 188         imply VIRTIO_SANDBOX
 189         imply VIRTIO_BLK
 190         imply VIRTIO_NET
 191         imply DM_SOUND
 192         imply PCI_SANDBOX_EP
 193         imply PCH
 194         imply PHYLIB
 195         imply DM_MDIO
 196         imply DM_MDIO_MUX
 197         imply ACPI
 198         imply ACPI_PMC
 199         imply ACPI_PMC_SANDBOX
 200         imply CMD_PMC
 201         imply CMD_CLONE
 202         imply SILENT_CONSOLE
 203         imply BOOTARGS_SUBST
 204         imply PHY_FIXED
 205         imply DM_DSA
 206         imply CMD_EXTENSION
 207         imply KEYBOARD
 208         imply PHYSMEM
 209         imply GENERATE_ACPI_TABLE
 210         imply BINMAN
 211         imply CMD_MBR
 212         imply CMD_MMC
 213         imply BOOTSTD_DEFAULTS if BOOTSTD_FULL && CMDLINE
 214         imply BOOTMETH_DISTRO if BOOTSTD_FULL && CMDLINE
 215         imply CMD_SYSBOOT if BOOTSTD_FULL
 216
 217 config SH
 218         bool "SuperH architecture"
 219         select HAVE_PRIVATE_LIBGCC
 220         select SUPPORT_OF_CONTROL
 221
 222 config X86
 223         bool "x86 architecture"
 224         select SUPPORT_SPL
 225         select SUPPORT_TPL
 226         select CREATE_ARCH_SYMLINK
 227         select DM
 228         select HAVE_ARCH_IOMAP
 229         select HAVE_PRIVATE_LIBGCC
 230         select OF_CONTROL
 231         select PCI
 232         select SUPPORT_ACPI
 233         select SUPPORT_OF_CONTROL
 234         select SYS_CACHE_SHIFT_6
 235         select TIMER
 236         select USE_PRIVATE_LIBGCC
 237         select X86_TSC_TIMER
 238         select IRQ
 239         imply HAS_ROM if X86_RESET_VECTOR
 240         imply BLK
 241         imply CMD_DM
 242         imply CMD_FPGA_LOADMK
 243         imply CMD_GETTIME
 244         imply CMD_IO
 245         imply CMD_IRQ
 246         imply CMD_PCI
 247         imply CMD_SF
 248         imply CMD_SF_TEST
 249         imply DM_GPIO
 250         imply DM_KEYBOARD
 251         imply DM_MMC
 252         imply DM_RTC
 253         imply SCSI
 254         imply DM_SERIAL
 255         imply DM_SPI
 256         imply DM_SPI_FLASH
 257         imply DM_USB
 258         imply LAST_STAGE_INIT
 259         imply VIDEO
 260         imply SYSRESET
 261         imply SPL_SYSRESET
 262         imply SYSRESET_X86
 263         imply USB_ETHER_ASIX
 264         imply USB_ETHER_SMSC95XX
 265         imply USB_HOST_ETHER
 266         imply PCH
 267         imply PHYSMEM
 268         imply RTC_MC146818
 269         imply ACPI
 270         imply ACPIGEN if !QEMU && !EFI_APP
 271         imply SYSINFO if GENERATE_SMBIOS_TABLE
 272         imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE
 273         imply TIMESTAMP
 274
 275         # Thing to enable for when SPL/TPL are enabled: SPL
 276         imply SPL_DM
 277         imply SPL_OF_LIBFDT
 278         imply SPL_DRIVERS_MISC
 279         imply SPL_GPIO
 280         imply SPL_PINCTRL
 281         imply SPL_LIBCOMMON_SUPPORT
 282         imply SPL_LIBGENERIC_SUPPORT
 283         imply SPL_SERIAL
 284         imply SPL_SPI_FLASH_SUPPORT
 285         imply SPL_SPI
 286         imply SPL_OF_CONTROL
 287         imply SPL_TIMER
 288         imply SPL_REGMAP
 289         imply SPL_SYSCON
 290         # TPL
 291         imply TPL_DM
 292         imply TPL_DRIVERS_MISC
 293         imply TPL_GPIO
 294         imply TPL_PINCTRL
 295         imply TPL_LIBCOMMON_SUPPORT
 296         imply TPL_LIBGENERIC_SUPPORT
 297         imply TPL_SERIAL
 298         imply TPL_OF_CONTROL
 299         imply TPL_TIMER
 300         imply TPL_REGMAP
 301         imply TPL_SYSCON
 302
 303 config XTENSA
 304         bool "Xtensa architecture"
 305         select CREATE_ARCH_SYMLINK
 306         select SUPPORT_OF_CONTROL
 307
 308 endchoice
 309
 310 config SYS_ARCH
 311         string
 312         help
 313           This option should contain the architecture name to build the
 314           appropriate arch/<CONFIG_SYS_ARCH> directory.
 315           All the architectures should specify this option correctly.
 316
 317 config SYS_CPU
 318         string
 319         help
 320           This option should contain the CPU name to build the correct
 321           arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU> directory.
 322
 323           This is optional.  For those targets without the CPU directory,
 324           leave this option empty.
 325
 326 config SYS_SOC
 327         string
 328         help
 329           This option should contain the SoC name to build the directory
 330           arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU>/<CONFIG_SYS_SOC>.
 331
 332           This is optional.  For those targets without the SoC directory,
 333           leave this option empty.
 334
 335 config SYS_VENDOR
 336         string
 337         help
 338           This option should contain the vendor name of the target board.
 339           If it is set and
 340           board/<CONFIG_SYS_VENDOR>/common/Makefile exists, the vendor common
 341           directory is compiled.
 342           If CONFIG_SYS_BOARD is also set, the sources under
 343           board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> directory are compiled.
 344
 345           This is optional.  For those targets without the vendor directory,
 346           leave this option empty.
 347
 348 config SYS_BOARD
 349         string
 350         help
 351           This option should contain the name of the target board.
 352           If it is set, either board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD>
 353           or board/<CONFIG_SYS_BOARD> directory is compiled depending on
 354           whether CONFIG_SYS_VENDOR is set or not.
 355
 356           This is optional.  For those targets without the board directory,
 357           leave this option empty.
 358
 359 config SYS_CONFIG_NAME
 360         string
 361         help
 362           This option should contain the base name of board header file.
 363           The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h
 364           should be included from include/config.h.
 365
 366 config SYS_DISABLE_DCACHE_OPS
 367         bool
 368         help
 369          This option disables dcache flush and dcache invalidation
 370          operations. For example, on coherent systems where cache
 371          operatios are not required, enable this option to avoid them.
 372          Note that, its up to the individual architectures to implement
 373          this functionality.
 374
 375 config SYS_IMMR
 376         hex "Address for the Internal Memory-Mapped Registers (IMMR) window"
 377         depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A
 378         default 0xFF000000 if MPC8xx
 379         default 0xF0000000 if ARCH_MPC8313
 380         default 0xE0000000 if MPC83xx && !ARCH_MPC8313
 381         default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
 382         default 0xFFE00000 if ARCH_P1010 || ARCH_P1011 || ARCH_P1020 || \
 383                               ARCH_P1021 || ARCH_P1024 || ARCH_P1025 || \
 384                               ARCH_P2020
 385         default SYS_CCSRBAR_DEFAULT
 386         help
 387           Address for the Internal Memory-Mapped Registers (IMMR) window used
 388           to configure the features of many Freescale / NXP SoCs.
 389
 390 config MONITOR_IS_IN_RAM
 391         bool "U-Boot is loaded in to RAM by a pre-loader"
 392         depends on M68K || NIOS2
 393
 394 menu "Skipping low level initialization functions"
 395         depends on ARM || MIPS || RISCV
 396
 397 config SKIP_LOWLEVEL_INIT
 398         bool "Skip calls to certain low level initialization functions"
 399         help
 400           If enabled, then certain low level initializations (like setting up
 401           the memory controller) are omitted and/or U-Boot does not relocate
 402           itself into RAM.
 403           Normally this variable MUST NOT be defined. The only exception is
 404           when U-Boot is loaded (to RAM) by some other boot loader or by a
 405           debugger which performs these initializations itself.
 406
 407 config SPL_SKIP_LOWLEVEL_INIT
 408         bool "Skip calls to certain low level initialization functions in SPL"
 409         depends on SPL
 410         help
 411           If enabled, then certain low level initializations (like setting up
 412           the memory controller) are omitted and/or U-Boot does not relocate
 413           itself into RAM.
 414           Normally this variable MUST NOT be defined. The only exception is
 415           when U-Boot is loaded (to RAM) by some other boot loader or by a
 416           debugger which performs these initializations itself.
 417
 418 config TPL_SKIP_LOWLEVEL_INIT
 419         bool "Skip calls to certain low level initialization functions in TPL"
 420         depends on SPL && ARM
 421         help
 422           If enabled, then certain low level initializations (like setting up
 423           the memory controller) are omitted and/or U-Boot does not relocate
 424           itself into RAM.
 425           Normally this variable MUST NOT be defined. The only exception is
 426           when U-Boot is loaded (to RAM) by some other boot loader or by a
 427           debugger which performs these initializations itself.
 428
 429 config SKIP_LOWLEVEL_INIT_ONLY
 430         bool "Skip call to lowlevel_init during early boot ONLY"
 431         depends on ARM
 432         help
 433           This allows just the call to lowlevel_init() to be skipped. The
 434           normal CP15 init (such as enabling the instruction cache) is still
 435           performed.
 436
 437 config SPL_SKIP_LOWLEVEL_INIT_ONLY
 438         bool "Skip call to lowlevel_init during early SPL boot ONLY"
 439         depends on SPL && ARM
 440         help
 441           This allows just the call to lowlevel_init() to be skipped. The
 442           normal CP15 init (such as enabling the instruction cache) is still
 443           performed.
 444
 445 config TPL_SKIP_LOWLEVEL_INIT_ONLY
 446         bool "Skip call to lowlevel_init during early TPL boot ONLY"
 447         depends on TPL && ARM
 448         help
 449           This allows just the call to lowlevel_init() to be skipped. The
 450           normal CP15 init (such as enabling the instruction cache) is still
 451           performed.
 452
 453 endmenu
 454
 455 config SYS_HAS_NONCACHED_MEMORY
 456         bool "Enable reserving a non-cached memory area for drivers"
 457         depends on (ARM || MIPS) && (RTL8169 || MEDIATEK_ETH)
 458         help
 459           This is useful for drivers that would otherwise require a lot of
 460           explicit cache maintenance. For some drivers it's also impossible to
 461           properly maintain the cache. For example if the regions that need to
 462           be flushed are not a multiple of the cache-line size, *and* padding
 463           cannot be allocated between the regions to align them (i.e.  if the
 464           HW requires a contiguous array of regions, and the size of each
 465           region is not cache-aligned), then a flush of one region may result
 466           in overwriting data that hardware has written to another region in
 467           the same cache-line. This can happen for example in network drivers
 468           where descriptors for buffers are typically smaller than the CPU
 469           cache-line (e.g.  16 bytes vs. 32 or 64 bytes).
 470
 471 config SYS_NONCACHED_MEMORY
 472         hex "Size in bytes of the non-cached memory area"
 473         depends on SYS_HAS_NONCACHED_MEMORY
 474         default 0x100000
 475         help
 476           Size of non-cached memory area. This area of memory will be typically
 477           located right below the malloc() area and mapped uncached in the MMU.
 478
 479 source "arch/arc/Kconfig"
 480 source "arch/arm/Kconfig"
 481 source "arch/m68k/Kconfig"
 482 source "arch/microblaze/Kconfig"
 483 source "arch/mips/Kconfig"
 484 source "arch/nios2/Kconfig"
 485 source "arch/powerpc/Kconfig"
 486 source "arch/sandbox/Kconfig"
 487 source "arch/sh/Kconfig"
 488 source "arch/x86/Kconfig"
 489 source "arch/xtensa/Kconfig"
 490 source "arch/riscv/Kconfig"
 491
 492 if ARM || M68K || PPC
 493
 494 source "arch/Kconfig.nxp"
 495
 496 endif
 497
 498 source "board/keymile/Kconfig"
 499
 500 if MIPS || MICROBLAZE
 501
 502 choice
 503         prompt "Endianness selection"
 504         help
 505           Some MIPS boards can be configured for either little or big endian
 506           byte order. These modes require different U-Boot images. In general there
 507           is one preferred byteorder for a particular system but some systems are
 508           just as commonly used in the one or the other endianness.
 509
 510 config SYS_BIG_ENDIAN
 511         bool "Big endian"
 512         depends on (SUPPORTS_BIG_ENDIAN && MIPS) || MICROBLAZE
 513
 514 config SYS_LITTLE_ENDIAN
 515         bool "Little endian"
 516         depends on (SUPPORTS_LITTLE_ENDIAN && MIPS) || MICROBLAZE
 517
 518 endchoice
 519
 520 endif