arch/arm/cpu/armv8/fsl-layerscape/Kconfig

   1 config ARCH_LS1012A
   2         bool
   3         select ARMV8_SET_SMPEN
   4         select ARM_ERRATA_855873 if !TFABOOT
   5         select FSL_LAYERSCAPE
   6         select FSL_LSCH2
   7         select SYS_FSL_SRDS_1
   8         select SYS_HAS_SERDES
   9         select SYS_FSL_DDR_BE
  10         select SYS_FSL_MMDC
  11         select SYS_FSL_ERRATUM_A010315
  12         select SYS_FSL_ERRATUM_A009798
  13         select SYS_FSL_ERRATUM_A008997
  14         select SYS_FSL_ERRATUM_A009007
  15         select SYS_FSL_ERRATUM_A009008
  16         select ARCH_EARLY_INIT_R
  17         select BOARD_EARLY_INIT_F
  18         select SYS_I2C_MXC
  19         select SYS_I2C_MXC_I2C1
  20         select SYS_I2C_MXC_I2C2
  21         imply PANIC_HANG
  22
  23 config ARCH_LS1028A
  24         bool
  25         select ARMV8_SET_SMPEN
  26         select FSL_LSCH3
  27         select NXP_LSCH3_2
  28         select SYS_FSL_HAS_CCI400
  29         select SYS_FSL_SRDS_1
  30         select SYS_HAS_SERDES
  31         select SYS_FSL_DDR
  32         select SYS_FSL_DDR_LE
  33         select SYS_FSL_DDR_VER_50
  34         select SYS_FSL_HAS_DDR3
  35         select SYS_FSL_HAS_DDR4
  36         select SYS_FSL_HAS_SEC
  37         select SYS_FSL_SEC_COMPAT_5
  38         select SYS_FSL_SEC_LE
  39         select FSL_TZASC_1
  40         select ARCH_EARLY_INIT_R
  41         select BOARD_EARLY_INIT_F
  42         select SYS_I2C_MXC
  43         select SYS_FSL_ERRATUM_A008997
  44         select SYS_FSL_ERRATUM_A009007
  45         select SYS_FSL_ERRATUM_A008514 if !TFABOOT
  46         select SYS_FSL_ERRATUM_A009663 if !TFABOOT
  47         select SYS_FSL_ERRATUM_A009942 if !TFABOOT
  48         imply PANIC_HANG
  49
  50 config ARCH_LS1043A
  51         bool
  52         select ARMV8_SET_SMPEN
  53         select ARM_ERRATA_855873 if !TFABOOT
  54         select FSL_LAYERSCAPE
  55         select FSL_LSCH2
  56         select SYS_FSL_SRDS_1
  57         select SYS_HAS_SERDES
  58         select SYS_FSL_DDR
  59         select SYS_FSL_DDR_BE
  60         select SYS_FSL_DDR_VER_50
  61         select SYS_FSL_ERRATUM_A008850 if !TFABOOT
  62         select SYS_FSL_ERRATUM_A008997
  63         select SYS_FSL_ERRATUM_A009007
  64         select SYS_FSL_ERRATUM_A009008
  65         select SYS_FSL_ERRATUM_A009660 if !TFABOOT
  66         select SYS_FSL_ERRATUM_A009663 if !TFABOOT
  67         select SYS_FSL_ERRATUM_A009798
  68         select SYS_FSL_ERRATUM_A009929
  69         select SYS_FSL_ERRATUM_A009942 if !TFABOOT
  70         select SYS_FSL_ERRATUM_A010315
  71         select SYS_FSL_ERRATUM_A010539
  72         select SYS_FSL_HAS_DDR3
  73         select SYS_FSL_HAS_DDR4
  74         select ARCH_EARLY_INIT_R
  75         select BOARD_EARLY_INIT_F
  76         select SYS_I2C_MXC
  77         select SYS_I2C_MXC_I2C1
  78         select SYS_I2C_MXC_I2C2
  79         select SYS_I2C_MXC_I2C3
  80         select SYS_I2C_MXC_I2C4
  81         imply CMD_PCI
  82
  83 config ARCH_LS1046A
  84         bool
  85         select ARMV8_SET_SMPEN
  86         select FSL_LAYERSCAPE
  87         select FSL_LSCH2
  88         select SYS_FSL_SRDS_1
  89         select SYS_HAS_SERDES
  90         select SYS_FSL_DDR
  91         select SYS_FSL_DDR_BE
  92         select SYS_FSL_DDR_VER_50
  93         select SYS_FSL_ERRATUM_A008336 if !TFABOOT
  94         select SYS_FSL_ERRATUM_A008511 if !TFABOOT
  95         select SYS_FSL_ERRATUM_A008850 if !TFABOOT
  96         select SYS_FSL_ERRATUM_A008997
  97         select SYS_FSL_ERRATUM_A009007
  98         select SYS_FSL_ERRATUM_A009008
  99         select SYS_FSL_ERRATUM_A009798
 100         select SYS_FSL_ERRATUM_A009801
 101         select SYS_FSL_ERRATUM_A009803 if !TFABOOT
 102         select SYS_FSL_ERRATUM_A009942 if !TFABOOT
 103         select SYS_FSL_ERRATUM_A010165 if !TFABOOT
 104         select SYS_FSL_ERRATUM_A010539
 105         select SYS_FSL_HAS_DDR4
 106         select SYS_FSL_SRDS_2
 107         select ARCH_EARLY_INIT_R
 108         select BOARD_EARLY_INIT_F
 109         select SYS_I2C_MXC
 110         select SYS_I2C_MXC_I2C1
 111         select SYS_I2C_MXC_I2C2
 112         select SYS_I2C_MXC_I2C3
 113         select SYS_I2C_MXC_I2C4
 114         imply SCSI
 115         imply SCSI_AHCI
 116
 117 config ARCH_LS1088A
 118         bool
 119         select ARMV8_SET_SMPEN
 120         select ARM_ERRATA_855873 if !TFABOOT
 121         select FSL_LAYERSCAPE
 122         select FSL_LSCH3
 123         select SYS_FSL_SRDS_1
 124         select SYS_HAS_SERDES
 125         select SYS_FSL_DDR
 126         select SYS_FSL_DDR_LE
 127         select SYS_FSL_DDR_VER_50
 128         select SYS_FSL_EC1
 129         select SYS_FSL_EC2
 130         select SYS_FSL_ERRATUM_A009803 if !TFABOOT
 131         select SYS_FSL_ERRATUM_A009942 if !TFABOOT
 132         select SYS_FSL_ERRATUM_A010165 if !TFABOOT
 133         select SYS_FSL_ERRATUM_A008511 if !TFABOOT
 134         select SYS_FSL_ERRATUM_A008850 if !TFABOOT
 135         select SYS_FSL_ERRATUM_A009007
 136         select SYS_FSL_HAS_CCI400
 137         select SYS_FSL_HAS_DDR4
 138         select SYS_FSL_HAS_RGMII
 139         select SYS_FSL_HAS_SEC
 140         select SYS_FSL_SEC_COMPAT_5
 141         select SYS_FSL_SEC_LE
 142         select SYS_FSL_SRDS_1
 143         select SYS_FSL_SRDS_2
 144         select FSL_TZASC_1
 145         select FSL_TZASC_400
 146         select FSL_TZPC_BP147
 147         select ARCH_EARLY_INIT_R
 148         select BOARD_EARLY_INIT_F
 149         select SYS_I2C_MXC
 150         select SYS_I2C_MXC_I2C1
 151         select SYS_I2C_MXC_I2C2
 152         select SYS_I2C_MXC_I2C3
 153         select SYS_I2C_MXC_I2C4
 154         imply SCSI
 155         imply PANIC_HANG
 156
 157 config ARCH_LS2080A
 158         bool
 159         select ARMV8_SET_SMPEN
 160         select ARM_ERRATA_826974
 161         select ARM_ERRATA_828024
 162         select ARM_ERRATA_829520
 163         select ARM_ERRATA_833471
 164         select FSL_LAYERSCAPE
 165         select FSL_LSCH3
 166         select SYS_FSL_SRDS_1
 167         select SYS_HAS_SERDES
 168         select SYS_FSL_DDR
 169         select SYS_FSL_DDR_LE
 170         select SYS_FSL_DDR_VER_50
 171         select SYS_FSL_HAS_CCN504
 172         select SYS_FSL_HAS_DP_DDR
 173         select SYS_FSL_HAS_SEC
 174         select SYS_FSL_HAS_DDR4
 175         select SYS_FSL_SEC_COMPAT_5
 176         select SYS_FSL_SEC_LE
 177         select SYS_FSL_SRDS_2
 178         select FSL_TZASC_1
 179         select FSL_TZASC_2
 180         select FSL_TZASC_400
 181         select FSL_TZPC_BP147
 182         select SYS_FSL_ERRATUM_A008336 if !TFABOOT
 183         select SYS_FSL_ERRATUM_A008511 if !TFABOOT
 184         select SYS_FSL_ERRATUM_A008514 if !TFABOOT
 185         select SYS_FSL_ERRATUM_A008585
 186         select SYS_FSL_ERRATUM_A008997
 187         select SYS_FSL_ERRATUM_A009007
 188         select SYS_FSL_ERRATUM_A009008
 189         select SYS_FSL_ERRATUM_A009635
 190         select SYS_FSL_ERRATUM_A009663 if !TFABOOT
 191         select SYS_FSL_ERRATUM_A009798
 192         select SYS_FSL_ERRATUM_A009801
 193         select SYS_FSL_ERRATUM_A009803 if !TFABOOT
 194         select SYS_FSL_ERRATUM_A009942 if !TFABOOT
 195         select SYS_FSL_ERRATUM_A010165 if !TFABOOT
 196         select SYS_FSL_ERRATUM_A009203
 197         select ARCH_EARLY_INIT_R
 198         select BOARD_EARLY_INIT_F
 199         select SYS_I2C_MXC
 200         select SYS_I2C_MXC_I2C1 if !TFABOOT
 201         select SYS_I2C_MXC_I2C2 if !TFABOOT
 202         select SYS_I2C_MXC_I2C3 if !TFABOOT
 203         select SYS_I2C_MXC_I2C4 if !TFABOOT
 204         imply DISTRO_DEFAULTS
 205         imply PANIC_HANG
 206
 207 config ARCH_LX2160A
 208         bool
 209         select ARMV8_SET_SMPEN
 210         select FSL_LSCH3
 211         select NXP_LSCH3_2
 212         select SYS_HAS_SERDES
 213         select SYS_FSL_SRDS_1
 214         select SYS_FSL_SRDS_2
 215         select SYS_NXP_SRDS_3
 216         select SYS_FSL_DDR
 217         select SYS_FSL_DDR_LE
 218         select SYS_FSL_DDR_VER_50
 219         select SYS_FSL_EC1
 220         select SYS_FSL_EC2
 221         select SYS_FSL_HAS_RGMII
 222         select SYS_FSL_HAS_SEC
 223         select SYS_FSL_HAS_CCN508
 224         select SYS_FSL_HAS_DDR4
 225         select SYS_FSL_SEC_COMPAT_5
 226         select SYS_FSL_SEC_LE
 227         select ARCH_EARLY_INIT_R
 228         select BOARD_EARLY_INIT_F
 229         select SYS_I2C_MXC
 230         imply DISTRO_DEFAULTS
 231         imply PANIC_HANG
 232         imply SCSI
 233         imply SCSI_AHCI
 234
 235 config FSL_LSCH2
 236         bool
 237         select SYS_FSL_HAS_CCI400
 238         select SYS_FSL_HAS_SEC
 239         select SYS_FSL_SEC_COMPAT_5
 240         select SYS_FSL_SEC_BE
 241
 242 config FSL_LSCH3
 243         bool
 244
 245 config NXP_LSCH3_2
 246         bool
 247
 248 config FSL_MC_ENET
 249         bool "Management Complex network"
 250         depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A
 251         default y
 252         select RESV_RAM
 253         help
 254           Enable Management Complex (MC) network
 255
 256 menu "Layerscape architecture"
 257         depends on FSL_LSCH2 || FSL_LSCH3
 258
 259 config FSL_LAYERSCAPE
 260         bool
 261
 262 config FSL_PCIE_COMPAT
 263         string "PCIe compatible of Kernel DT"
 264         depends on PCIE_LAYERSCAPE || PCIE_LAYERSCAPE_GEN4
 265         default "fsl,ls1012a-pcie" if ARCH_LS1012A
 266         default "fsl,ls1028a-pcie" if ARCH_LS1028A
 267         default "fsl,ls1043a-pcie" if ARCH_LS1043A
 268         default "fsl,ls1046a-pcie" if ARCH_LS1046A
 269         default "fsl,ls2080a-pcie" if ARCH_LS2080A
 270         default "fsl,ls1088a-pcie" if ARCH_LS1088A
 271         default "fsl,lx2160a-pcie" if ARCH_LX2160A
 272         help
 273           This compatible is used to find pci controller node in Kernel DT
 274           to complete fixup.
 275
 276 config HAS_FEATURE_GIC64K_ALIGN
 277         bool
 278         default y if ARCH_LS1043A
 279
 280 config HAS_FEATURE_ENHANCED_MSI
 281         bool
 282         default y if ARCH_LS1043A
 283
 284 menu "Layerscape PPA"
 285 config FSL_LS_PPA
 286         bool "FSL Layerscape PPA firmware support"
 287         depends on !ARMV8_PSCI
 288         select ARMV8_SEC_FIRMWARE_SUPPORT
 289         select SEC_FIRMWARE_ARMV8_PSCI
 290         select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
 291         help
 292           The FSL Primary Protected Application (PPA) is a software component
 293           which is loaded during boot stage, and then remains resident in RAM
 294           and runs in the TrustZone after boot.
 295           Say y to enable it.
 296
 297 config SPL_FSL_LS_PPA
 298         bool "FSL Layerscape PPA firmware support for SPL build"
 299         depends on !ARMV8_PSCI
 300         select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
 301         select SEC_FIRMWARE_ARMV8_PSCI
 302         select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
 303         help
 304           The FSL Primary Protected Application (PPA) is a software component
 305           which is loaded during boot stage, and then remains resident in RAM
 306           and runs in the TrustZone after boot. This is to load PPA during SPL
 307           stage instead of the RAM version of U-Boot. Once PPA is initialized,
 308           the rest of U-Boot (including RAM version) runs at EL2.
 309 choice
 310         prompt "FSL Layerscape PPA firmware loading-media select"
 311         depends on FSL_LS_PPA
 312         default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
 313         default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
 314         default SYS_LS_PPA_FW_IN_XIP
 315
 316 config SYS_LS_PPA_FW_IN_XIP
 317         bool "XIP"
 318         help
 319           Say Y here if the PPA firmware locate at XIP flash, such
 320           as NOR or QSPI flash.
 321
 322 config SYS_LS_PPA_FW_IN_MMC
 323         bool "eMMC or SD Card"
 324         help
 325           Say Y here if the PPA firmware locate at eMMC/SD card.
 326
 327 config SYS_LS_PPA_FW_IN_NAND
 328         bool "NAND"
 329         help
 330           Say Y here if the PPA firmware locate at NAND flash.
 331
 332 endchoice
 333
 334 config LS_PPA_ESBC_HDR_SIZE
 335         hex "Length of PPA ESBC header"
 336         depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
 337         default 0x2000
 338         help
 339           Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
 340           NAND to memory to validate PPA image.
 341
 342 endmenu
 343
 344 config SYS_FSL_ERRATUM_A008997
 345         bool "Workaround for USB PHY erratum A008997"
 346
 347 config SYS_FSL_ERRATUM_A009007
 348         bool
 349         help
 350           Workaround for USB PHY erratum A009007
 351
 352 config SYS_FSL_ERRATUM_A009008
 353         bool "Workaround for USB PHY erratum A009008"
 354
 355 config SYS_FSL_ERRATUM_A009798
 356         bool "Workaround for USB PHY erratum A009798"
 357
 358 config SYS_FSL_ERRATUM_A010315
 359         bool "Workaround for PCIe erratum A010315"
 360
 361 config SYS_FSL_ERRATUM_A010539
 362         bool "Workaround for PIN MUX erratum A010539"
 363
 364 config MAX_CPUS
 365         int "Maximum number of CPUs permitted for Layerscape"
 366         default 2 if ARCH_LS1028A
 367         default 4 if ARCH_LS1043A
 368         default 4 if ARCH_LS1046A
 369         default 16 if ARCH_LS2080A
 370         default 8 if ARCH_LS1088A
 371         default 16 if ARCH_LX2160A
 372         default 1
 373         help
 374           Set this number to the maximum number of possible CPUs in the SoC.
 375           SoCs may have multiple clusters with each cluster may have multiple
 376           ports. If some ports are reserved but higher ports are used for
 377           cores, count the reserved ports. This will allocate enough memory
 378           in spin table to properly handle all cores.
 379
 380 config EMC2305
 381         bool "Fan controller"
 382         help
 383          Enable the EMC2305 fan controller for configuration of fan
 384          speed.
 385
 386 config SECURE_BOOT
 387         bool "Secure Boot"
 388         help
 389                 Enable Freescale Secure Boot feature
 390
 391 config QSPI_AHB_INIT
 392         bool "Init the QSPI AHB bus"
 393         help
 394           The default setting for QSPI AHB bus just support 3bytes addressing.
 395           But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
 396           bus for those flashes to support the full QSPI flash size.
 397
 398 config SYS_CCI400_OFFSET
 399         hex "Offset for CCI400 base"
 400         depends on SYS_FSL_HAS_CCI400
 401         default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A
 402         default 0x180000 if FSL_LSCH2
 403         help
 404           Offset for CCI400 base
 405           CCI400 base addr = CCSRBAR + CCI400_OFFSET
 406
 407 config SYS_FSL_IFC_BANK_COUNT
 408         int "Maximum banks of Integrated flash controller"
 409         depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
 410         default 4 if ARCH_LS1043A
 411         default 4 if ARCH_LS1046A
 412         default 8 if ARCH_LS2080A || ARCH_LS1088A
 413
 414 config SYS_FSL_HAS_CCI400
 415         bool
 416
 417 config SYS_FSL_HAS_CCN504
 418         bool
 419
 420 config SYS_FSL_HAS_CCN508
 421         bool
 422
 423 config SYS_FSL_HAS_DP_DDR
 424         bool
 425
 426 config SYS_FSL_SRDS_1
 427         bool
 428
 429 config SYS_FSL_SRDS_2
 430         bool
 431
 432 config SYS_NXP_SRDS_3
 433         bool
 434
 435 config SYS_HAS_SERDES
 436         bool
 437
 438 config FSL_TZASC_1
 439         bool
 440
 441 config FSL_TZASC_2
 442         bool
 443
 444 config FSL_TZASC_400
 445         bool
 446
 447 config FSL_TZPC_BP147
 448         bool
 449 endmenu
 450
 451 menu "Layerscape clock tree configuration"
 452         depends on FSL_LSCH2 || FSL_LSCH3
 453
 454 config SYS_FSL_CLK
 455         bool "Enable clock tree initialization"
 456         default y
 457
 458 config CLUSTER_CLK_FREQ
 459         int "Reference clock of core cluster"
 460         depends on ARCH_LS1012A
 461         default 100000000
 462         help
 463           This number is the reference clock frequency of core PLL.
 464           For most platforms, the core PLL and Platform PLL have the same
 465           reference clock, but for some platforms, LS1012A for instance,
 466           they are provided sepatately.
 467
 468 config SYS_FSL_PCLK_DIV
 469         int "Platform clock divider"
 470         default 1 if ARCH_LS1028A
 471         default 1 if ARCH_LS1043A
 472         default 1 if ARCH_LS1046A
 473         default 1 if ARCH_LS1088A
 474         default 2
 475         help
 476           This is the divider that is used to derive Platform clock from
 477           Platform PLL, in another word:
 478                 Platform_clk = Platform_PLL_freq / this_divider
 479
 480 config SYS_FSL_DSPI_CLK_DIV
 481         int "DSPI clock divider"
 482         default 1 if ARCH_LS1043A
 483         default 2
 484         help
 485           This is the divider that is used to derive DSPI clock from Platform
 486           clock, in another word DSPI_clk = Platform_clk / this_divider.
 487
 488 config SYS_FSL_DUART_CLK_DIV
 489         int "DUART clock divider"
 490         default 1 if ARCH_LS1043A
 491         default 4 if ARCH_LX2160A
 492         default 2
 493         help
 494           This is the divider that is used to derive DUART clock from Platform
 495           clock, in another word DUART_clk = Platform_clk / this_divider.
 496
 497 config SYS_FSL_I2C_CLK_DIV
 498         int "I2C clock divider"
 499         default 1 if ARCH_LS1043A
 500         default 2
 501         help
 502           This is the divider that is used to derive I2C clock from Platform
 503           clock, in another word I2C_clk = Platform_clk / this_divider.
 504
 505 config SYS_FSL_IFC_CLK_DIV
 506         int "IFC clock divider"
 507         default 1 if ARCH_LS1043A
 508         default 2
 509         help
 510           This is the divider that is used to derive IFC clock from Platform
 511           clock, in another word IFC_clk = Platform_clk / this_divider.
 512
 513 config SYS_FSL_LPUART_CLK_DIV
 514         int "LPUART clock divider"
 515         default 1 if ARCH_LS1043A
 516         default 2
 517         help
 518           This is the divider that is used to derive LPUART clock from Platform
 519           clock, in another word LPUART_clk = Platform_clk / this_divider.
 520
 521 config SYS_FSL_SDHC_CLK_DIV
 522         int "SDHC clock divider"
 523         default 1 if ARCH_LS1043A
 524         default 1 if ARCH_LS1012A
 525         default 2
 526         help
 527           This is the divider that is used to derive SDHC clock from Platform
 528           clock, in another word SDHC_clk = Platform_clk / this_divider.
 529
 530 config SYS_FSL_QMAN_CLK_DIV
 531         int "QMAN clock divider"
 532         default 1 if ARCH_LS1043A
 533         default 2
 534         help
 535           This is the divider that is used to derive QMAN clock from Platform
 536           clock, in another word QMAN_clk = Platform_clk / this_divider.
 537 endmenu
 538
 539 config RESV_RAM
 540         bool
 541         help
 542           Reserve memory from the top, tracked by gd->arch.resv_ram. This
 543           reserved RAM can be used by special driver that resides in memory
 544           after U-Boot exits. It's up to implementation to allocate and allow
 545           access to this reserved memory. For example, the reserved RAM can
 546           be at the high end of physical memory. The reserve RAM may be
 547           excluded from memory bank(s) passed to OS, or marked as reserved.
 548
 549 config SYS_FSL_EC1
 550         bool
 551         help
 552           Ethernet controller 1, this is connected to
 553           MAC17 for LX2160A or to MAC3 for other SoCs
 554           Provides DPAA2 capabilities
 555
 556 config SYS_FSL_EC2
 557         bool
 558         help
 559           Ethernet controller 2, this is connected to
 560           MAC18 for LX2160A or to MAC4 for other SoCs
 561           Provides DPAA2 capabilities
 562
 563 config SYS_FSL_ERRATUM_A008336
 564         bool
 565
 566 config SYS_FSL_ERRATUM_A008514
 567         bool
 568
 569 config SYS_FSL_ERRATUM_A008585
 570         bool
 571
 572 config SYS_FSL_ERRATUM_A008850
 573         bool
 574
 575 config SYS_FSL_ERRATUM_A009203
 576         bool
 577
 578 config SYS_FSL_ERRATUM_A009635
 579         bool
 580
 581 config SYS_FSL_ERRATUM_A009660
 582         bool
 583
 584 config SYS_FSL_ERRATUM_A009929
 585         bool
 586
 587
 588 config SYS_FSL_HAS_RGMII
 589         bool
 590         depends on SYS_FSL_EC1 || SYS_FSL_EC2
 591
 592
 593 config SYS_MC_RSV_MEM_ALIGN
 594         hex "Management Complex reserved memory alignment"
 595         depends on RESV_RAM
 596         default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A
 597         help
 598           Reserved memory needs to be aligned for MC to use. Default value
 599           is 512MB.
 600
 601 config SPL_LDSCRIPT
 602         default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
 603
 604 config HAS_FSL_XHCI_USB
 605         bool
 606         default y if ARCH_LS1043A || ARCH_LS1046A
 607         help
 608           For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
 609           pins, select it when the pins are assigned to USB.