arch/arm/cpu/armv8/hisilicon/pinmux.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015 Linaro.
   4  * Peter Griffin <peter.griffin@linaro.org>
   5  */
   6
   7 #include <common.h>
   8 #include <fdtdec.h>
   9 #include <asm/gpio.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/pinmux.h>
  12
  13 struct hi6220_pinmux0_regs *pmx0 =
  14         (struct hi6220_pinmux0_regs *)HI6220_PINMUX0_BASE;
  15
  16 struct hi6220_pinmux1_regs *pmx1 =
  17         (struct hi6220_pinmux1_regs *)HI6220_PINMUX1_BASE;
  18
  19 static void hi6220_uart_config(int peripheral)
  20 {
  21         switch (peripheral) {
  22         case PERIPH_ID_UART0:
  23                 writel(MUX_M0, &pmx0->iomg[48]); /* UART0_RXD */
  24                 writel(MUX_M0, &pmx0->iomg[49]); /* UART0_TXD */
  25
  26                 writel(DRIVE1_02MA | PULL_UP, &pmx1->iocfg[49]); /* UART0_RXD */
  27                 writel(DRIVE1_02MA | PULL_UP, &pmx1->iocfg[50]); /* UART0_TXD */
  28                 break;
  29
  30         case PERIPH_ID_UART1:
  31                 writel(MUX_M0, &pmx0->iomg[50]); /* UART1_CTS_N */
  32                 writel(MUX_M0, &pmx0->iomg[51]); /* UART1_RTS_N */
  33                 writel(MUX_M0, &pmx0->iomg[52]); /* UART1_RXD */
  34                 writel(MUX_M0, &pmx0->iomg[53]); /* UART1_TXD */
  35
  36                 writel(DRIVE1_02MA | PULL_UP, &pmx1->iocfg[51]); /*UART1_CTS_N*/
  37                 writel(DRIVE1_02MA | PULL_UP, &pmx1->iocfg[53]); /* UART1_RXD */
  38                 writel(DRIVE1_02MA, &pmx1->iocfg[52]); /* UART1_RTS_N */
  39                 writel(DRIVE1_02MA, &pmx1->iocfg[54]); /* UART1_TXD */
  40                 break;
  41
  42         case PERIPH_ID_UART2:
  43                 writel(MUX_M0, &pmx0->iomg[54]); /* UART2_CTS_N */
  44                 writel(MUX_M0, &pmx0->iomg[55]); /* UART2_RTS_N */
  45                 writel(MUX_M0, &pmx0->iomg[56]); /* UART2_RXD */
  46                 writel(MUX_M0, &pmx0->iomg[57]); /* UART2_TXD */
  47
  48                 writel(DRIVE1_02MA, &pmx1->iocfg[55]); /* UART2_CTS_N */
  49                 writel(DRIVE1_02MA, &pmx1->iocfg[56]); /* UART2_RTS_N */
  50                 writel(DRIVE1_02MA, &pmx1->iocfg[57]); /* UART2_RXD */
  51                 writel(DRIVE1_02MA, &pmx1->iocfg[58]); /* UART2_TXD */
  52                 break;
  53
  54         case PERIPH_ID_UART3:
  55                 writel(MUX_M1, &pmx0->iomg[96]); /* UART3_CTS_N */
  56                 writel(MUX_M1, &pmx0->iomg[97]); /* UART3_RTS_N */
  57                 writel(MUX_M1, &pmx0->iomg[98]); /* UART3_RXD */
  58                 writel(MUX_M1, &pmx0->iomg[99]); /* UART3_TXD */
  59
  60                 /* UART3_TXD */
  61                 writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[100]);
  62                 /* UART3_RTS_N */
  63                 writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[101]);
  64                 /* UART3_RXD */
  65                 writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[102]);
  66                 /* UART3_TXD */
  67                 writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[103]);
  68                 break;
  69
  70         case PERIPH_ID_UART4:
  71                 writel(MUX_M1, &pmx0->iomg[116]); /* UART4_CTS_N */
  72                 writel(MUX_M1, &pmx0->iomg[117]); /* UART4_RTS_N */
  73                 writel(MUX_M1, &pmx0->iomg[118]); /* UART4_RXD */
  74                 writel(MUX_M1, &pmx0->iomg[119]); /* UART4_TXD */
  75
  76                 /* UART4_CTS_N */
  77                 writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[120]);
  78                 /* UART4_RTS_N */
  79                 writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[121]);
  80                 /* UART4_RXD */
  81                 writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[122]);
  82                 /* UART4_TXD */
  83                 writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[123]);
  84                 break;
  85         case PERIPH_ID_UART5:
  86                 writel(MUX_M1, &pmx0->iomg[114]); /* UART5_RXD */
  87                 writel(MUX_M1, &pmx0->iomg[115]); /* UART5_TXD */
  88
  89                 /* UART5_RXD */
  90                 writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[118]);
  91                 /* UART5_TXD */
  92                 writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[119]);
  93
  94                 break;
  95
  96         default:
  97                 debug("%s: invalid peripheral %d", __func__, peripheral);
  98                 return;
  99         }
 100 }
 101
 102 static int hi6220_mmc_config(int peripheral)
 103 {
 104         u32 tmp;
 105
 106         switch (peripheral) {
 107         case PERIPH_ID_SDMMC0:
 108
 109                 /* eMMC pinmux config */
 110                 writel(MUX_M0, &pmx0->iomg[64]); /* EMMC_CLK */
 111                 writel(MUX_M0, &pmx0->iomg[65]); /* EMMC_CMD */
 112                 writel(MUX_M0, &pmx0->iomg[66]); /* EMMC_DATA0 */
 113                 writel(MUX_M0, &pmx0->iomg[67]); /* EMMC_DATA1 */
 114                 writel(MUX_M0, &pmx0->iomg[68]); /* EMMC_DATA2 */
 115                 writel(MUX_M0, &pmx0->iomg[69]); /* EMMC_DATA3 */
 116                 writel(MUX_M0, &pmx0->iomg[70]); /* EMMC_DATA4 */
 117                 writel(MUX_M0, &pmx0->iomg[71]); /* EMMC_DATA5 */
 118                 writel(MUX_M0, &pmx0->iomg[72]); /* EMMC_DATA6 */
 119                 writel(MUX_M0, &pmx0->iomg[73]); /* EMMC_DATA7 */
 120
 121                 /*eMMC configure up/down/drive */
 122                 writel(DRIVE1_08MA, &pmx1->iocfg[65]); /* EMMC_CLK */
 123
 124                 tmp = DRIVE1_04MA | PULL_UP;
 125                 writel(tmp, &pmx1->iocfg[65]); /* EMMC_CMD */
 126                 writel(tmp, &pmx1->iocfg[66]); /* EMMC_DATA0 */
 127                 writel(tmp, &pmx1->iocfg[67]); /* EMMC_DATA1 */
 128                 writel(tmp, &pmx1->iocfg[68]); /* EMMC_DATA2 */
 129                 writel(tmp, &pmx1->iocfg[69]); /* EMMC_DATA3 */
 130                 writel(tmp, &pmx1->iocfg[70]); /* EMMC_DATA4 */
 131                 writel(tmp, &pmx1->iocfg[71]); /* EMMC_DATA5 */
 132                 writel(tmp, &pmx1->iocfg[72]); /* EMMC_DATA6 */
 133                 writel(tmp, &pmx1->iocfg[73]); /* EMMC_DATA7 */
 134
 135                 writel(DRIVE1_04MA, &pmx1->iocfg[73]); /* EMMC_RST_N */
 136                 break;
 137
 138         case PERIPH_ID_SDMMC1:
 139
 140                 writel(MUX_M0, &pmx0->iomg[3]); /* SD_CLK */
 141                 writel(MUX_M0, &pmx0->iomg[4]); /* SD_CMD */
 142                 writel(MUX_M0, &pmx0->iomg[5]); /* SD_DATA0 */
 143                 writel(MUX_M0, &pmx0->iomg[6]); /* SD_DATA1 */
 144                 writel(MUX_M0, &pmx0->iomg[7]); /* SD_DATA2 */
 145                 writel(MUX_M0, &pmx0->iomg[8]); /* SD_DATA3 */
 146
 147                 writel(DRIVE1_10MA | BIT(2), &pmx1->iocfg[3]); /*SD_CLK*/
 148                 writel(DRIVE1_08MA | BIT(2), &pmx1->iocfg[4]); /*SD_CMD*/
 149                 writel(DRIVE1_08MA | BIT(2), &pmx1->iocfg[5]); /*SD_DATA0*/
 150                 writel(DRIVE1_08MA | BIT(2), &pmx1->iocfg[6]); /*SD_DATA1*/
 151                 writel(DRIVE1_08MA | BIT(2), &pmx1->iocfg[7]); /*SD_DATA2*/
 152                 writel(DRIVE1_08MA | BIT(2), &pmx1->iocfg[8]); /*SD_DATA3*/
 153                 break;
 154
 155         default:
 156                 debug("%s: invalid peripheral %d", __func__, peripheral);
 157                 return -1;
 158         }
 159
 160         return 0;
 161 }
 162
 163 int hi6220_pinmux_config(int peripheral)
 164 {
 165         switch (peripheral) {
 166         case PERIPH_ID_UART0:
 167         case PERIPH_ID_UART1:
 168         case PERIPH_ID_UART2:
 169         case PERIPH_ID_UART3:
 170                 hi6220_uart_config(peripheral);
 171                 break;
 172         case PERIPH_ID_SDMMC0:
 173         case PERIPH_ID_SDMMC1:
 174                 return hi6220_mmc_config(peripheral);
 175         default:
 176                 debug("%s: invalid peripheral %d", __func__, peripheral);
 177                 return -1;
 178         }
 179
 180         return 0;
 181 }
 182
 183