arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2020 Gateworks Corporation
   4  */
   5
   6 #include "imx8mm-venice-u-boot.dtsi"
   7
   8 &gpio1 {
   9         uart1_rs422 {
  10                 gpio-hog;
  11                 output-high;
  12                 gpios = <0 GPIO_ACTIVE_HIGH>;
  13                 line-name = "uart1_rs422#";
  14         };
  15
  16         uart1rs485 {
  17                 gpio-hog;
  18                 output-high;
  19                 gpios = <3 GPIO_ACTIVE_HIGH>;
  20                 line-name = "uart1_rs485#";
  21         };
  22
  23         uart1rs232 {
  24                 gpio-hog;
  25                 output-high;
  26                 gpios = <5 GPIO_ACTIVE_HIGH>;
  27                 line-name = "uart1_rs232#";
  28         };
  29
  30         dig1in {
  31                 gpio-hog;
  32                 input;
  33                 gpios = <6 GPIO_ACTIVE_HIGH>;
  34                 line-name = "dig1_in";
  35         };
  36
  37         dig1out {
  38                 gpio-hog;
  39                 output-low;
  40                 gpios = <7 GPIO_ACTIVE_HIGH>;
  41                 line-name = "dig1_out";
  42         };
  43 };
  44
  45 &gpio4 {
  46         uart3_rs232 {
  47                 gpio-hog;
  48                 output-high;
  49                 gpios = <6 GPIO_ACTIVE_HIGH>;
  50                 line-name = "uart3_rs232#";
  51         };
  52
  53         uart3_rs422 {
  54                 gpio-hog;
  55                 output-high;
  56                 gpios = <7 GPIO_ACTIVE_HIGH>;
  57                 line-name = "uart3_rs422#";
  58         };
  59
  60         uart3_rs485 {
  61                 gpio-hog;
  62                 output-high;
  63                 gpios = <8 GPIO_ACTIVE_HIGH>;
  64                 line-name = "uart3_rs485#";
  65         };
  66
  67         uart4_rs485 {
  68                 gpio-hog;
  69                 output-high;
  70                 gpios = <27 GPIO_ACTIVE_HIGH>;
  71                 line-name = "uart4_rs485#";
  72         };
  73
  74         sim1det {
  75                 gpio-hog;
  76                 input;
  77                 gpios = <29 GPIO_ACTIVE_HIGH>;
  78                 line-name = "sim1_det";
  79         };
  80
  81         sim2det {
  82                 gpio-hog;
  83                 input;
  84                 gpios = <30 GPIO_ACTIVE_HIGH>;
  85                 line-name = "sim2_det";
  86         };
  87 };
  88
  89 &gpio5 {
  90         dig2out {
  91                 gpio-hog;
  92                 output-low;
  93                 gpios = <3 GPIO_ACTIVE_HIGH>;
  94                 line-name = "dig2_out";
  95         };
  96
  97         dig2in {
  98                 gpio-hog;
  99                 input;
 100                 gpios = <4 GPIO_ACTIVE_HIGH>;
 101                 line-name = "dig2_in";
 102         };
 103
 104         sim2sel {
 105                 gpio-hog;
 106                 output-low;
 107                 gpios = <5 GPIO_ACTIVE_HIGH>;
 108                 line-name = "sim2_sel";
 109         };
 110
 111         uart4_rs232 {
 112                 gpio-hog;
 113                 output-high;
 114                 gpios = <10 GPIO_ACTIVE_HIGH>;
 115                 line-name = "uart4_rs232#";
 116         };
 117
 118         uart4_rs422 {
 119                 gpio-hog;
 120                 output-high;
 121                 gpios = <13 GPIO_ACTIVE_HIGH>;
 122                 line-name = "uart4_rs422#";
 123         };
 124 };
 125
 126 &fec1 {
 127         phy-reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
 128         phy-reset-duration = <1>;
 129         phy-reset-post-delay = <1>;
 130 };
 131
 132 &switch {
 133         ports {
 134                 #address-cells = <1>;
 135                 #size-cells = <0>;
 136
 137                 lan1: port@0 {
 138                         phy-handle = <&sw_phy0>;
 139                 };
 140
 141                 lan2: port@1 {
 142                         phy-handle = <&sw_phy1>;
 143                 };
 144
 145                 lan3: port@2 {
 146                         phy-handle = <&sw_phy2>;
 147                 };
 148
 149                 lan4: port@3 {
 150                         phy-handle = <&sw_phy3>;
 151                 };
 152         };
 153
 154         mdios {
 155                 #address-cells = <1>;
 156                 #size-cells = <0>;
 157
 158                 mdio@0 {
 159                         reg = <0>;
 160                         compatible = "microchip,ksz-mdio";
 161                         #address-cells = <1>;
 162                         #size-cells = <0>;
 163
 164                         sw_phy0: ethernet-phy@0 {
 165                                 reg = <0x0>;
 166                         };
 167
 168                         sw_phy1: ethernet-phy@1 {
 169                                 reg = <0x1>;
 170                         };
 171
 172                         sw_phy2: ethernet-phy@2 {
 173                                 reg = <0x2>;
 174                         };
 175
 176                         sw_phy3: ethernet-phy@3 {
 177                                 reg = <0x3>;
 178                         };
 179                 };
 180         };
 181 };
 182
 183 &pinctrl_fec1 {
 184         bootph-pre-ram;
 185 };
 186
 187 &{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} {
 188         bootph-pre-ram;
 189 };
 190
 191 &{/soc@0/bus@30800000/i2c@30a30000/pmic@4b/regulators} {
 192         bootph-pre-ram;
 193 };
 194
 195 &pinctrl_pmic {
 196         bootph-pre-ram;
 197 };