arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com
   4  * Author: Matt McKee <mmckee@phytec.com>
   5  *
   6  * Copyright (C) 2022 - 2024 PHYTEC Messtechnik GmbH
   7  * Author: Wadim Egorov <w.egorov@phytec.de>
   8  *
   9  * Product homepage:
  10  * https://www.phytec.com/product/phycore-am64x
  11  */
  12
  13 #include "k3-am642-phycore-som-binman.dtsi"
  14
  15 / {
  16         chosen {
  17                 stdout-path = "serial2:115200n8";
  18                 tick-timer = &main_timer0;
  19         };
  20
  21         memory@80000000 {
  22                 bootph-all;
  23         };
  24 };
  25
  26 &cbass_main {
  27         bootph-all;
  28 };
  29
  30 &dmsc {
  31         bootph-all;
  32 };
  33
  34 &dmss {
  35         bootph-all;
  36 };
  37
  38 &k3_clks {
  39         bootph-all;
  40 };
  41
  42 &k3_pds {
  43         bootph-all;
  44 };
  45
  46 &k3_reset {
  47         bootph-all;
  48 };
  49
  50 &main_bcdma {
  51         bootph-all;
  52         reg = <0x00 0x485c0100 0x00 0x100>,
  53               <0x00 0x4c000000 0x00 0x20000>,
  54               <0x00 0x4a820000 0x00 0x20000>,
  55               <0x00 0x4aa40000 0x00 0x20000>,
  56               <0x00 0x4bc00000 0x00 0x100000>,
  57               <0x00 0x48600000 0x00 0x8000>,
  58               <0x00 0x484a4000 0x00 0x2000>,
  59               <0x00 0x484c2000 0x00 0x2000>;
  60         reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
  61                     "cfg", "tchan", "rchan";
  62 };
  63
  64 &main_conf {
  65         bootph-all;
  66         chipid@14 {
  67                 bootph-all;
  68         };
  69 };
  70
  71 &main_gpio0 {
  72         bootph-all;
  73 };
  74
  75 &main_mmc1_pins_default {
  76         bootph-all;
  77 };
  78
  79 &main_pktdma {
  80         bootph-all;
  81         reg = <0x00 0x485c0000 0x00 0x100>,
  82               <0x00 0x4a800000 0x00 0x20000>,
  83               <0x00 0x4aa00000 0x00 0x40000>,
  84               <0x00 0x4b800000 0x00 0x400000>,
  85               <0x00 0x485e0000 0x00 0x20000>,
  86               <0x00 0x484a0000 0x00 0x4000>,
  87               <0x00 0x484c0000 0x00 0x2000>,
  88               <0x00 0x48430000 0x00 0x4000>;
  89         reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", "cfg",
  90                     "tchan", "rchan", "rflow";
  91 };
  92
  93 &main_pmx0 {
  94         bootph-all;
  95 };
  96
  97 &main_timer0 {
  98         bootph-all;
  99         clock-frequency = <200000000>;
 100 };
 101
 102 &main_uart0 {
 103         bootph-all;
 104 };
 105
 106 &main_uart0_pins_default {
 107         bootph-all;
 108 };
 109
 110 &main_usb0_pins_default {
 111         bootph-all;
 112 };
 113
 114 &ospi0 {
 115         bootph-all;
 116         flash@0 {
 117                 bootph-all;
 118         };
 119 };
 120
 121 &ospi0_pins_default {
 122         bootph-all;
 123 };
 124
 125 &sdhci0 {
 126         bootph-all;
 127 };
 128
 129 &sdhci1 {
 130         bootph-all;
 131 };
 132
 133 &secure_proxy_main {
 134         bootph-all;
 135 };
 136
 137 &usbss0 {
 138         bootph-all;
 139 };
 140
 141 &usb0 {
 142         bootph-all;
 143 };