arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
   4  */
   5
   6 #include "k3-j721e-binman.dtsi"
   7
   8 &cbass_main {
   9         bootph-all;
  10 };
  11
  12 &main_navss {
  13         bootph-all;
  14 };
  15
  16 &cbass_mcu_wakeup {
  17         bootph-all;
  18
  19         chipid@43000014 {
  20                 bootph-all;
  21         };
  22 };
  23
  24 &mcu_navss {
  25         bootph-all;
  26 };
  27
  28 &mcu_ringacc {
  29         bootph-all;
  30 };
  31
  32 &mcu_udmap {
  33         reg =   <0x0 0x285c0000 0x0 0x100>,
  34                 <0x0 0x284c0000 0x0 0x4000>,
  35                 <0x0 0x2a800000 0x0 0x40000>,
  36                 <0x0 0x284a0000 0x0 0x4000>,
  37                 <0x0 0x2aa00000 0x0 0x40000>,
  38                 <0x0 0x28400000 0x0 0x2000>;
  39         reg-names = "gcfg", "rchan", "rchanrt", "tchan",
  40                     "tchanrt", "rflow";
  41         bootph-all;
  42 };
  43
  44 &secure_proxy_main {
  45         bootph-all;
  46 };
  47
  48 &dmsc {
  49         bootph-all;
  50 };
  51
  52 &k3_pds {
  53         bootph-all;
  54 };
  55
  56 &k3_clks {
  57         bootph-all;
  58 };
  59
  60 &k3_reset {
  61         bootph-all;
  62 };
  63
  64 &wkup_pmx0 {
  65         bootph-all;
  66 };
  67
  68 &main_pmx0 {
  69         bootph-all;
  70 };
  71
  72 &main_uart0 {
  73         bootph-all;
  74 };
  75
  76 &mcu_uart0 {
  77         bootph-all;
  78 };
  79
  80 &main_sdhci0 {
  81         bootph-all;
  82 };
  83
  84 &main_sdhci1 {
  85         bootph-all;
  86 };
  87
  88 &main_uart0_pins_default {
  89         bootph-all;
  90 };
  91
  92 &serdes_ln_ctrl {
  93         bootph-all;
  94 };
  95
  96 &usb_serdes_mux {
  97         bootph-all;
  98 };
  99
 100 &main_usbss0_pins_default {
 101         bootph-all;
 102 };
 103
 104 &usbss0 {
 105         bootph-all;
 106 };
 107
 108 &usb0 {
 109         dr_mode = "peripheral";
 110         bootph-all;
 111 };
 112
 113 &main_mmc1_pins_default {
 114         bootph-all;
 115 };
 116
 117 &wkup_i2c0_pins_default {
 118         bootph-all;
 119 };
 120
 121 &wkup_uart0 {
 122         bootph-all;
 123         status = "okay";
 124 };
 125
 126 &wkup_i2c0 {
 127         bootph-all;
 128         status = "okay";
 129 };
 130
 131 &main_i2c0 {
 132         bootph-all;
 133 };
 134
 135 &main_i2c0_pins_default {
 136         bootph-all;
 137 };
 138
 139 &main_esm {
 140         bootph-all;
 141 };
 142
 143 &exp2 {
 144         bootph-all;
 145 };
 146
 147 &mcu_fss0_ospi0_pins_default {
 148         bootph-all;
 149 };
 150
 151 &fss {
 152         bootph-all;
 153 };
 154
 155 &wkup_gpio0 {
 156         bootph-all;
 157 };
 158
 159 &ospi0 {
 160         bootph-all;
 161
 162         flash@0 {
 163                 bootph-all;
 164         };
 165 };
 166
 167 &ospi1 {
 168         bootph-all;
 169
 170         flash@0 {
 171                 bootph-all;
 172         };
 173 };
 174
 175 &mcu_fss0_hpb0_pins_default {
 176         bootph-all;
 177 };
 178
 179 &wkup_gpio_pins_default {
 180         bootph-all;
 181 };
 182
 183 &mcu_fss0_ospi1_pins_default {
 184         bootph-all;
 185 };