arch/arm/dts/sun50i-h6.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ or MIT)
   2 /*
   3  * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/sun50i-h6-ccu.h>
   8 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
   9 #include <dt-bindings/clock/sun8i-de2.h>
  10 #include <dt-bindings/clock/sun8i-tcon-top.h>
  11 #include <dt-bindings/reset/sun50i-h6-ccu.h>
  12 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
  13 #include <dt-bindings/reset/sun8i-de2.h>
  14
  15 / {
  16         interrupt-parent = <&gic>;
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         cpus {
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23
  24                 cpu0: cpu@0 {
  25                         compatible = "arm,cortex-a53";
  26                         device_type = "cpu";
  27                         reg = <0>;
  28                         enable-method = "psci";
  29                 };
  30
  31                 cpu1: cpu@1 {
  32                         compatible = "arm,cortex-a53";
  33                         device_type = "cpu";
  34                         reg = <1>;
  35                         enable-method = "psci";
  36                 };
  37
  38                 cpu2: cpu@2 {
  39                         compatible = "arm,cortex-a53";
  40                         device_type = "cpu";
  41                         reg = <2>;
  42                         enable-method = "psci";
  43                 };
  44
  45                 cpu3: cpu@3 {
  46                         compatible = "arm,cortex-a53";
  47                         device_type = "cpu";
  48                         reg = <3>;
  49                         enable-method = "psci";
  50                 };
  51         };
  52
  53         de: display-engine {
  54                 compatible = "allwinner,sun50i-h6-display-engine";
  55                 allwinner,pipelines = <&mixer0>;
  56                 status = "disabled";
  57         };
  58
  59         iosc: internal-osc-clk {
  60                 #clock-cells = <0>;
  61                 compatible = "fixed-clock";
  62                 clock-frequency = <16000000>;
  63                 clock-accuracy = <300000000>;
  64                 clock-output-names = "iosc";
  65         };
  66
  67         osc24M: osc24M_clk {
  68                 #clock-cells = <0>;
  69                 compatible = "fixed-clock";
  70                 clock-frequency = <24000000>;
  71                 clock-output-names = "osc24M";
  72         };
  73
  74         osc32k: osc32k_clk {
  75                 #clock-cells = <0>;
  76                 compatible = "fixed-clock";
  77                 clock-frequency = <32768>;
  78                 clock-output-names = "osc32k";
  79         };
  80
  81         psci {
  82                 compatible = "arm,psci-0.2";
  83                 method = "smc";
  84         };
  85
  86         timer {
  87                 compatible = "arm,armv8-timer";
  88                 interrupts = <GIC_PPI 13
  89                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  90                              <GIC_PPI 14
  91                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  92                              <GIC_PPI 11
  93                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  94                              <GIC_PPI 10
  95                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  96         };
  97
  98         soc {
  99                 compatible = "simple-bus";
 100                 #address-cells = <1>;
 101                 #size-cells = <1>;
 102                 ranges;
 103
 104                 display-engine@1000000 {
 105                         compatible = "allwinner,sun50i-h6-de3",
 106                                      "allwinner,sun50i-a64-de2";
 107                         reg = <0x1000000 0x400000>;
 108                         allwinner,sram = <&de2_sram 1>;
 109                         #address-cells = <1>;
 110                         #size-cells = <1>;
 111                         ranges = <0 0x1000000 0x400000>;
 112
 113                         display_clocks: clock@0 {
 114                                 compatible = "allwinner,sun50i-h6-de3-clk";
 115                                 reg = <0x0 0x10000>;
 116                                 clocks = <&ccu CLK_DE>,
 117                                          <&ccu CLK_BUS_DE>;
 118                                 clock-names = "mod",
 119                                               "bus";
 120                                 resets = <&ccu RST_BUS_DE>;
 121                                 #clock-cells = <1>;
 122                                 #reset-cells = <1>;
 123                         };
 124
 125                         mixer0: mixer@100000 {
 126                                 compatible = "allwinner,sun50i-h6-de3-mixer-0";
 127                                 reg = <0x100000 0x100000>;
 128                                 clocks = <&display_clocks CLK_BUS_MIXER0>,
 129                                          <&display_clocks CLK_MIXER0>;
 130                                 clock-names = "bus",
 131                                               "mod";
 132                                 resets = <&display_clocks RST_MIXER0>;
 133
 134                                 ports {
 135                                         #address-cells = <1>;
 136                                         #size-cells = <0>;
 137
 138                                         mixer0_out: port@1 {
 139                                                 reg = <1>;
 140
 141                                                 mixer0_out_tcon_top_mixer0: endpoint {
 142                                                         remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
 143                                                 };
 144                                         };
 145                                 };
 146                         };
 147                 };
 148
 149                 video-codec@1c0e000 {
 150                         compatible = "allwinner,sun50i-h6-video-engine";
 151                         reg = <0x01c0e000 0x2000>;
 152                         clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
 153                                  <&ccu CLK_MBUS_VE>;
 154                         clock-names = "ahb", "mod", "ram";
 155                         resets = <&ccu RST_BUS_VE>;
 156                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 157                         allwinner,sram = <&ve_sram 1>;
 158                 };
 159
 160                 syscon: syscon@3000000 {
 161                         compatible = "allwinner,sun50i-h6-system-control",
 162                                      "allwinner,sun50i-a64-system-control";
 163                         reg = <0x03000000 0x1000>;
 164                         #address-cells = <1>;
 165                         #size-cells = <1>;
 166                         ranges;
 167
 168                         sram_c: sram@28000 {
 169                                 compatible = "mmio-sram";
 170                                 reg = <0x00028000 0x1e000>;
 171                                 #address-cells = <1>;
 172                                 #size-cells = <1>;
 173                                 ranges = <0 0x00028000 0x1e000>;
 174
 175                                 de2_sram: sram-section@0 {
 176                                         compatible = "allwinner,sun50i-h6-sram-c",
 177                                                      "allwinner,sun50i-a64-sram-c";
 178                                         reg = <0x0000 0x1e000>;
 179                                 };
 180                         };
 181
 182                         sram_c1: sram@1a00000 {
 183                                 compatible = "mmio-sram";
 184                                 reg = <0x01a00000 0x200000>;
 185                                 #address-cells = <1>;
 186                                 #size-cells = <1>;
 187                                 ranges = <0 0x01a00000 0x200000>;
 188
 189                                 ve_sram: sram-section@0 {
 190                                         compatible = "allwinner,sun50i-h6-sram-c1",
 191                                                      "allwinner,sun4i-a10-sram-c1";
 192                                         reg = <0x000000 0x200000>;
 193                                 };
 194                         };
 195                 };
 196
 197                 ccu: clock@3001000 {
 198                         compatible = "allwinner,sun50i-h6-ccu";
 199                         reg = <0x03001000 0x1000>;
 200                         clocks = <&osc24M>, <&osc32k>, <&iosc>;
 201                         clock-names = "hosc", "losc", "iosc";
 202                         #clock-cells = <1>;
 203                         #reset-cells = <1>;
 204                 };
 205
 206                 sid: sid@3006000 {
 207                         compatible = "allwinner,sun50i-h6-sid";
 208                         reg = <0x03006000 0x400>;
 209                 };
 210
 211                 pio: pinctrl@300b000 {
 212                         compatible = "allwinner,sun50i-h6-pinctrl";
 213                         reg = <0x0300b000 0x400>;
 214                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 215                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 216                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 217                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 218                         clocks = <&ccu CLK_APB1>, <&osc24M>, <&osc32k>;
 219                         clock-names = "apb", "hosc", "losc";
 220                         gpio-controller;
 221                         #gpio-cells = <3>;
 222                         interrupt-controller;
 223                         #interrupt-cells = <3>;
 224
 225                         ext_rgmii_pins: rgmii-pins {
 226                                 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
 227                                        "PD5", "PD7", "PD8", "PD9", "PD10",
 228                                        "PD11", "PD12", "PD13", "PD19", "PD20";
 229                                 function = "emac";
 230                                 drive-strength = <40>;
 231                         };
 232
 233                         hdmi_pins: hdmi-pins {
 234                                 pins = "PH8", "PH9", "PH10";
 235                                 function = "hdmi";
 236                         };
 237
 238                         mmc0_pins: mmc0-pins {
 239                                 pins = "PF0", "PF1", "PF2", "PF3",
 240                                        "PF4", "PF5";
 241                                 function = "mmc0";
 242                                 drive-strength = <30>;
 243                                 bias-pull-up;
 244                         };
 245
 246                         mmc2_pins: mmc2-pins {
 247                                 pins = "PC1", "PC4", "PC5", "PC6",
 248                                        "PC7", "PC8", "PC9", "PC10",
 249                                        "PC11", "PC12", "PC13", "PC14";
 250                                 function = "mmc2";
 251                                 drive-strength = <30>;
 252                                 bias-pull-up;
 253                         };
 254
 255                         uart0_ph_pins: uart0-ph-pins {
 256                                 pins = "PH0", "PH1";
 257                                 function = "uart0";
 258                         };
 259                 };
 260
 261                 gic: interrupt-controller@3021000 {
 262                         compatible = "arm,gic-400";
 263                         reg = <0x03021000 0x1000>,
 264                               <0x03022000 0x2000>,
 265                               <0x03024000 0x2000>,
 266                               <0x03026000 0x2000>;
 267                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 268                         interrupt-controller;
 269                         #interrupt-cells = <3>;
 270                 };
 271
 272                 mmc0: mmc@4020000 {
 273                         compatible = "allwinner,sun50i-h6-mmc",
 274                                      "allwinner,sun50i-a64-mmc";
 275                         reg = <0x04020000 0x1000>;
 276                         clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
 277                         clock-names = "ahb", "mmc";
 278                         resets = <&ccu RST_BUS_MMC0>;
 279                         reset-names = "ahb";
 280                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 281                         pinctrl-names = "default";
 282                         pinctrl-0 = <&mmc0_pins>;
 283                         status = "disabled";
 284                         #address-cells = <1>;
 285                         #size-cells = <0>;
 286                 };
 287
 288                 mmc1: mmc@4021000 {
 289                         compatible = "allwinner,sun50i-h6-mmc",
 290                                      "allwinner,sun50i-a64-mmc";
 291                         reg = <0x04021000 0x1000>;
 292                         clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
 293                         clock-names = "ahb", "mmc";
 294                         resets = <&ccu RST_BUS_MMC1>;
 295                         reset-names = "ahb";
 296                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 297                         status = "disabled";
 298                         #address-cells = <1>;
 299                         #size-cells = <0>;
 300                 };
 301
 302                 mmc2: mmc@4022000 {
 303                         compatible = "allwinner,sun50i-h6-emmc",
 304                                      "allwinner,sun50i-a64-emmc";
 305                         reg = <0x04022000 0x1000>;
 306                         clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
 307                         clock-names = "ahb", "mmc";
 308                         resets = <&ccu RST_BUS_MMC2>;
 309                         reset-names = "ahb";
 310                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 311                         pinctrl-names = "default";
 312                         pinctrl-0 = <&mmc2_pins>;
 313                         status = "disabled";
 314                         #address-cells = <1>;
 315                         #size-cells = <0>;
 316                 };
 317
 318                 uart0: serial@5000000 {
 319                         compatible = "snps,dw-apb-uart";
 320                         reg = <0x05000000 0x400>;
 321                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 322                         reg-shift = <2>;
 323                         reg-io-width = <4>;
 324                         clocks = <&ccu CLK_BUS_UART0>;
 325                         resets = <&ccu RST_BUS_UART0>;
 326                         status = "disabled";
 327                 };
 328
 329                 uart1: serial@5000400 {
 330                         compatible = "snps,dw-apb-uart";
 331                         reg = <0x05000400 0x400>;
 332                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 333                         reg-shift = <2>;
 334                         reg-io-width = <4>;
 335                         clocks = <&ccu CLK_BUS_UART1>;
 336                         resets = <&ccu RST_BUS_UART1>;
 337                         status = "disabled";
 338                 };
 339
 340                 uart2: serial@5000800 {
 341                         compatible = "snps,dw-apb-uart";
 342                         reg = <0x05000800 0x400>;
 343                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 344                         reg-shift = <2>;
 345                         reg-io-width = <4>;
 346                         clocks = <&ccu CLK_BUS_UART2>;
 347                         resets = <&ccu RST_BUS_UART2>;
 348                         status = "disabled";
 349                 };
 350
 351                 uart3: serial@5000c00 {
 352                         compatible = "snps,dw-apb-uart";
 353                         reg = <0x05000c00 0x400>;
 354                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 355                         reg-shift = <2>;
 356                         reg-io-width = <4>;
 357                         clocks = <&ccu CLK_BUS_UART3>;
 358                         resets = <&ccu RST_BUS_UART3>;
 359                         status = "disabled";
 360                 };
 361
 362                 emac: ethernet@5020000 {
 363                         compatible = "allwinner,sun50i-h6-emac",
 364                                      "allwinner,sun50i-a64-emac";
 365                         syscon = <&syscon>;
 366                         reg = <0x05020000 0x10000>;
 367                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 368                         interrupt-names = "macirq";
 369                         resets = <&ccu RST_BUS_EMAC>;
 370                         reset-names = "stmmaceth";
 371                         clocks = <&ccu CLK_BUS_EMAC>;
 372                         clock-names = "stmmaceth";
 373                         status = "disabled";
 374
 375                         mdio: mdio {
 376                                 compatible = "snps,dwmac-mdio";
 377                                 #address-cells = <1>;
 378                                 #size-cells = <0>;
 379                         };
 380                 };
 381
 382                 usb2otg: usb@5100000 {
 383                         compatible = "allwinner,sun50i-h6-musb",
 384                                      "allwinner,sun8i-a33-musb";
 385                         reg = <0x05100000 0x0400>;
 386                         clocks = <&ccu CLK_BUS_OTG>;
 387                         resets = <&ccu RST_BUS_OTG>;
 388                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 389                         interrupt-names = "mc";
 390                         phys = <&usb2phy 0>;
 391                         phy-names = "usb";
 392                         extcon = <&usb2phy 0>;
 393                         status = "disabled";
 394                 };
 395
 396                 usb2phy: phy@5100400 {
 397                         compatible = "allwinner,sun50i-h6-usb-phy";
 398                         reg = <0x05100400 0x24>,
 399                               <0x05101800 0x4>,
 400                               <0x05311800 0x4>;
 401                         reg-names = "phy_ctrl",
 402                                     "pmu0",
 403                                     "pmu3";
 404                         clocks = <&ccu CLK_USB_PHY0>,
 405                                  <&ccu CLK_USB_PHY3>;
 406                         clock-names = "usb0_phy",
 407                                       "usb3_phy";
 408                         resets = <&ccu RST_USB_PHY0>,
 409                                  <&ccu RST_USB_PHY3>;
 410                         reset-names = "usb0_reset",
 411                                       "usb3_reset";
 412                         status = "disabled";
 413                         #phy-cells = <1>;
 414                 };
 415
 416                 ehci0: usb@5101000 {
 417                         compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
 418                         reg = <0x05101000 0x100>;
 419                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 420                         clocks = <&ccu CLK_BUS_OHCI0>,
 421                                  <&ccu CLK_BUS_EHCI0>,
 422                                  <&ccu CLK_USB_OHCI0>;
 423                         resets = <&ccu RST_BUS_OHCI0>,
 424                                  <&ccu RST_BUS_EHCI0>;
 425                         status = "disabled";
 426                 };
 427
 428                 ohci0: usb@5101400 {
 429                         compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
 430                         reg = <0x05101400 0x100>;
 431                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 432                         clocks = <&ccu CLK_BUS_OHCI0>,
 433                                  <&ccu CLK_USB_OHCI0>;
 434                         resets = <&ccu RST_BUS_OHCI0>;
 435                         status = "disabled";
 436                 };
 437
 438                 ehci3: usb@5311000 {
 439                         compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
 440                         reg = <0x05311000 0x100>;
 441                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 442                         clocks = <&ccu CLK_BUS_OHCI3>,
 443                                  <&ccu CLK_BUS_EHCI3>,
 444                                  <&ccu CLK_USB_OHCI3>;
 445                         resets = <&ccu RST_BUS_OHCI3>,
 446                                  <&ccu RST_BUS_EHCI3>;
 447                         phys = <&usb2phy 3>;
 448                         phy-names = "usb";
 449                         status = "disabled";
 450                 };
 451
 452                 ohci3: usb@5311400 {
 453                         compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
 454                         reg = <0x05311400 0x100>;
 455                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 456                         clocks = <&ccu CLK_BUS_OHCI3>,
 457                                  <&ccu CLK_USB_OHCI3>;
 458                         resets = <&ccu RST_BUS_OHCI3>;
 459                         phys = <&usb2phy 3>;
 460                         phy-names = "usb";
 461                         status = "disabled";
 462                 };
 463
 464                 hdmi: hdmi@6000000 {
 465                         compatible = "allwinner,sun50i-h6-dw-hdmi";
 466                         reg = <0x06000000 0x10000>;
 467                         reg-io-width = <1>;
 468                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 469                         clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
 470                                  <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>,
 471                                  <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>;
 472                         clock-names = "iahb", "isfr", "tmds", "cec", "hdcp",
 473                                       "hdcp-bus";
 474                         resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>;
 475                         reset-names = "ctrl", "hdcp";
 476                         phys = <&hdmi_phy>;
 477                         phy-names = "hdmi-phy";
 478                         pinctrl-names = "default";
 479                         pinctrl-0 = <&hdmi_pins>;
 480                         status = "disabled";
 481
 482                         ports {
 483                                 #address-cells = <1>;
 484                                 #size-cells = <0>;
 485
 486                                 hdmi_in: port@0 {
 487                                         reg = <0>;
 488
 489                                         hdmi_in_tcon_top: endpoint {
 490                                                 remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
 491                                         };
 492                                 };
 493
 494                                 hdmi_out: port@1 {
 495                                         reg = <1>;
 496                                 };
 497                         };
 498                 };
 499
 500                 hdmi_phy: hdmi-phy@6010000 {
 501                         compatible = "allwinner,sun50i-h6-hdmi-phy";
 502                         reg = <0x06010000 0x10000>;
 503                         clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
 504                         clock-names = "bus", "mod";
 505                         resets = <&ccu RST_BUS_HDMI>;
 506                         reset-names = "phy";
 507                         #phy-cells = <0>;
 508                 };
 509
 510                 tcon_top: tcon-top@6510000 {
 511                         compatible = "allwinner,sun50i-h6-tcon-top";
 512                         reg = <0x06510000 0x1000>;
 513                         clocks = <&ccu CLK_BUS_TCON_TOP>,
 514                                  <&ccu CLK_TCON_TV0>;
 515                         clock-names = "bus",
 516                                       "tcon-tv0";
 517                         clock-output-names = "tcon-top-tv0";
 518                         resets = <&ccu RST_BUS_TCON_TOP>;
 519                         reset-names = "rst";
 520                         #clock-cells = <1>;
 521
 522                         ports {
 523                                 #address-cells = <1>;
 524                                 #size-cells = <0>;
 525
 526                                 tcon_top_mixer0_in: port@0 {
 527                                         #address-cells = <1>;
 528                                         #size-cells = <0>;
 529                                         reg = <0>;
 530
 531                                         tcon_top_mixer0_in_mixer0: endpoint@0 {
 532                                                 reg = <0>;
 533                                                 remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
 534                                         };
 535                                 };
 536
 537                                 tcon_top_mixer0_out: port@1 {
 538                                         #address-cells = <1>;
 539                                         #size-cells = <0>;
 540                                         reg = <1>;
 541
 542                                         tcon_top_mixer0_out_tcon_tv: endpoint@2 {
 543                                                 reg = <2>;
 544                                                 remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>;
 545                                         };
 546                                 };
 547
 548                                 tcon_top_hdmi_in: port@4 {
 549                                         #address-cells = <1>;
 550                                         #size-cells = <0>;
 551                                         reg = <4>;
 552
 553                                         tcon_top_hdmi_in_tcon_tv: endpoint@0 {
 554                                                 reg = <0>;
 555                                                 remote-endpoint = <&tcon_tv_out_tcon_top>;
 556                                         };
 557                                 };
 558
 559                                 tcon_top_hdmi_out: port@5 {
 560                                         reg = <5>;
 561
 562                                         tcon_top_hdmi_out_hdmi: endpoint {
 563                                                 remote-endpoint = <&hdmi_in_tcon_top>;
 564                                         };
 565                                 };
 566                         };
 567                 };
 568
 569                 tcon_tv: lcd-controller@6515000 {
 570                         compatible = "allwinner,sun50i-h6-tcon-tv",
 571                                      "allwinner,sun8i-r40-tcon-tv";
 572                         reg = <0x06515000 0x1000>;
 573                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 574                         clocks = <&ccu CLK_BUS_TCON_TV0>,
 575                                  <&tcon_top CLK_TCON_TOP_TV0>;
 576                         clock-names = "ahb",
 577                                       "tcon-ch1";
 578                         resets = <&ccu RST_BUS_TCON_TV0>;
 579                         reset-names = "lcd";
 580
 581                         ports {
 582                                 #address-cells = <1>;
 583                                 #size-cells = <0>;
 584
 585                                 tcon_tv_in: port@0 {
 586                                         reg = <0>;
 587
 588                                         tcon_tv_in_tcon_top_mixer0: endpoint {
 589                                                 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>;
 590                                         };
 591                                 };
 592
 593                                 tcon_tv_out: port@1 {
 594                                         #address-cells = <1>;
 595                                         #size-cells = <0>;
 596                                         reg = <1>;
 597
 598                                         tcon_tv_out_tcon_top: endpoint@1 {
 599                                                 reg = <1>;
 600                                                 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>;
 601                                         };
 602                                 };
 603                         };
 604                 };
 605
 606                 r_ccu: clock@7010000 {
 607                         compatible = "allwinner,sun50i-h6-r-ccu";
 608                         reg = <0x07010000 0x400>;
 609                         clocks = <&osc24M>, <&osc32k>, <&iosc>,
 610                                  <&ccu CLK_PLL_PERIPH0>;
 611                         clock-names = "hosc", "losc", "iosc", "pll-periph";
 612                         #clock-cells = <1>;
 613                         #reset-cells = <1>;
 614                 };
 615
 616                 r_intc: interrupt-controller@7021000 {
 617                         compatible = "allwinner,sun50i-h6-r-intc",
 618                                      "allwinner,sun6i-a31-r-intc";
 619                         interrupt-controller;
 620                         #interrupt-cells = <2>;
 621                         reg = <0x07021000 0x400>;
 622                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 623                 };
 624
 625                 r_pio: pinctrl@7022000 {
 626                         compatible = "allwinner,sun50i-h6-r-pinctrl";
 627                         reg = <0x07022000 0x400>;
 628                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 629                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 630                         clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&osc32k>;
 631                         clock-names = "apb", "hosc", "losc";
 632                         gpio-controller;
 633                         #gpio-cells = <3>;
 634                         interrupt-controller;
 635                         #interrupt-cells = <3>;
 636
 637                         r_i2c_pins: r-i2c-pins {
 638                                 pins = "PL0", "PL1";
 639                                 function = "s_i2c";
 640                         };
 641                 };
 642
 643                 r_i2c: i2c@7081400 {
 644                         compatible = "allwinner,sun6i-a31-i2c";
 645                         reg = <0x07081400 0x400>;
 646                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 647                         clocks = <&r_ccu CLK_R_APB2_I2C>;
 648                         resets = <&r_ccu RST_R_APB2_I2C>;
 649                         pinctrl-names = "default";
 650                         pinctrl-0 = <&r_i2c_pins>;
 651                         status = "disabled";
 652                         #address-cells = <1>;
 653                         #size-cells = <0>;
 654                 };
 655         };
 656 };