1 // SPDX-License-Identifier: GPL-2.0+
3 * J721E: SoC specific initialization
5 * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
6 * David Huang <d-huang@ti.com>
13 #include <asm/armv7_mpu.h>
14 #include <asm/arch/hardware.h>
15 #include "sysfw-loader.h"
17 #include <linux/soc/ti/ti_sci_protocol.h>
19 #include <dm/uclass-internal.h>
20 #include <dm/pinctrl.h>
23 #include <remoteproc.h>
25 struct fwl_data cbass_hc_cfg0_fwls
[] = {
26 { "PCIE0_CFG", 2577, 7 },
27 { "EMMC8SS0_CFG", 2579, 4 },
28 { "USB3SS0_CORE", 2580, 4 },
29 { "USB3SS1_CORE", 2581, 1 },
30 }, cbass_hc2_fwls
[] = {
31 { "PCIE0", 2547, 24 },
32 { "HC2_WIZ16B8M4CT2", 2552, 1 },
33 }, cbass_rc_cfg0_fwls
[] = {
34 { "EMMCSD4SS0_CFG", 2400, 4 },
35 }, infra_cbass0_fwls
[] = {
37 { "PLL_CTRL0", 6, 1 },
38 { "PLL_MMR0", 8, 26 },
39 { "CTRL_MMR0", 9, 16 },
41 }, mcu_cbass0_fwls
[] = {
42 { "MCU_R5FSS0_CORE0", 1024, 4 },
43 { "MCU_R5FSS0_CORE0_CFG", 1025, 3 },
44 { "MCU_R5FSS0_CORE1", 1028, 4 },
45 { "MCU_R5FSS0_CORE1_CFG", 1029, 1 },
46 { "MCU_FSS0_CFG", 1032, 12 },
47 { "MCU_FSS0_S1", 1033, 8 },
48 { "MCU_FSS0_S0", 1036, 8 },
49 { "MCU_PSROM49152X32", 1048, 1 },
50 { "MCU_MSRAM128KX64", 1050, 8 },
51 { "MCU_MSRAM128KX64_CFG", 1051, 1 },
52 { "MCU_TIMER0", 1056, 1 },
53 { "MCU_TIMER9", 1065, 1 },
54 { "MCU_USART0", 1120, 1 },
55 { "MCU_I2C0", 1152, 1 },
56 { "MCU_CTRL_MMR0", 1200, 8 },
57 { "MCU_PLL_MMR0", 1201, 3 },
58 { "MCU_CPSW0", 1220, 2 },
59 }, wkup_cbass0_fwls
[] = {
60 { "WKUP_PSC0", 129, 1 },
61 { "WKUP_PLL_CTRL0", 130, 1 },
62 { "WKUP_CTRL_MMR0", 131, 16 },
63 { "WKUP_GPIO0", 132, 1 },
64 { "WKUP_I2C0", 144, 1 },
65 { "WKUP_USART0", 160, 1 },
66 }, navss_cbass0_fwls
[] = {
67 { "NACSS_VIRT0", 6253, 1 },
70 static void ctrl_mmr_unlock(void)
72 /* Unlock all WKUP_CTRL_MMR0 module registers */
73 mmr_unlock(WKUP_CTRL_MMR0_BASE
, 0);
74 mmr_unlock(WKUP_CTRL_MMR0_BASE
, 1);
75 mmr_unlock(WKUP_CTRL_MMR0_BASE
, 2);
76 mmr_unlock(WKUP_CTRL_MMR0_BASE
, 3);
77 mmr_unlock(WKUP_CTRL_MMR0_BASE
, 4);
78 mmr_unlock(WKUP_CTRL_MMR0_BASE
, 6);
79 mmr_unlock(WKUP_CTRL_MMR0_BASE
, 7);
81 /* Unlock all MCU_CTRL_MMR0 module registers */
82 mmr_unlock(MCU_CTRL_MMR0_BASE
, 0);
83 mmr_unlock(MCU_CTRL_MMR0_BASE
, 1);
84 mmr_unlock(MCU_CTRL_MMR0_BASE
, 2);
85 mmr_unlock(MCU_CTRL_MMR0_BASE
, 3);
86 mmr_unlock(MCU_CTRL_MMR0_BASE
, 4);
88 /* Unlock all CTRL_MMR0 module registers */
89 mmr_unlock(CTRL_MMR0_BASE
, 0);
90 mmr_unlock(CTRL_MMR0_BASE
, 1);
91 mmr_unlock(CTRL_MMR0_BASE
, 2);
92 mmr_unlock(CTRL_MMR0_BASE
, 3);
93 mmr_unlock(CTRL_MMR0_BASE
, 5);
94 mmr_unlock(CTRL_MMR0_BASE
, 7);
97 void k3_mmc_stop_clock(void)
99 if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW
)) {
100 if (spl_boot_device() == BOOT_DEVICE_MMC1
) {
101 struct mmc
*mmc
= find_mmc_device(0);
106 mmc
->saved_clock
= mmc
->clock
;
107 mmc_set_clock(mmc
, 0, true);
112 void k3_mmc_restart_clock(void)
114 if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW
)) {
115 if (spl_boot_device() == BOOT_DEVICE_MMC1
) {
116 struct mmc
*mmc
= find_mmc_device(0);
121 mmc_set_clock(mmc
, mmc
->saved_clock
, false);
127 * This uninitialized global variable would normal end up in the .bss section,
128 * but the .bss is cleared between writing and reading this variable, so move
129 * it to the .data section.
131 u32 bootindex
__attribute__((section(".data")));
132 static struct rom_extended_boot_data bootdata
__section(".data");
134 static void store_boot_info_from_rom(void)
136 bootindex
= *(u32
*)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX
);
137 memcpy(&bootdata
, (uintptr_t *)ROM_EXTENDED_BOOT_DATA_INFO
,
138 sizeof(struct rom_extended_boot_data
));
141 void k3_spl_init(void)
146 * Cannot delay this further as there is a chance that
147 * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
149 store_boot_info_from_rom();
151 /* Make all control module registers accessible */
154 if (IS_ENABLED(CONFIG_CPU_V7R
)) {
155 disable_linefill_optimization();
156 setup_k3_mpu_regions();
162 /* Prepare console output */
163 preloader_console_init();
165 if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW
)) {
167 * Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue
168 * regardless of the result of pinctrl. Do this without probing the
169 * device, but instead by searching the device that would request the
170 * given sequence number if probed. The UART will be used by the system
171 * firmware (SYSFW) image for various purposes and SYSFW depends on us
172 * to initialize its pin settings.
174 ret
= uclass_find_device_by_seq(UCLASS_SERIAL
, 0, &dev
);
176 pinctrl_select_state(dev
, "default");
179 * Load, start up, and configure system controller firmware. Provide
180 * the U-Boot console init function to the SYSFW post-PM configuration
181 * callback hook, effectively switching on (or over) the console
184 k3_sysfw_loader(is_rom_loaded_sysfw(&bootdata
),
185 k3_mmc_stop_clock
, k3_mmc_restart_clock
);
187 if (IS_ENABLED(CONFIG_SPL_CLK_K3
)) {
189 * Force probe of clk_k3 driver here to ensure basic default clock
190 * configuration is always done for enabling PM services.
192 ret
= uclass_get_device_by_driver(UCLASS_CLK
,
193 DM_DRIVER_GET(ti_clk
),
196 panic("Failed to initialize clk-k3!\n");
199 remove_fwl_configs(cbass_hc_cfg0_fwls
, ARRAY_SIZE(cbass_hc_cfg0_fwls
));
200 remove_fwl_configs(cbass_hc2_fwls
, ARRAY_SIZE(cbass_hc2_fwls
));
201 remove_fwl_configs(cbass_rc_cfg0_fwls
, ARRAY_SIZE(cbass_rc_cfg0_fwls
));
202 remove_fwl_configs(infra_cbass0_fwls
, ARRAY_SIZE(infra_cbass0_fwls
));
203 remove_fwl_configs(mcu_cbass0_fwls
, ARRAY_SIZE(mcu_cbass0_fwls
));
204 remove_fwl_configs(wkup_cbass0_fwls
, ARRAY_SIZE(wkup_cbass0_fwls
));
205 remove_fwl_configs(navss_cbass0_fwls
, ARRAY_SIZE(navss_cbass0_fwls
));
208 /* Output System Firmware version info */
209 k3_sysfw_print_ver();
212 bool check_rom_loaded_sysfw(void)
214 return is_rom_loaded_sysfw(&bootdata
);
217 void k3_mem_init(void)
222 if (IS_ENABLED(CONFIG_K3_J721E_DDRSS
)) {
223 ret
= uclass_get_device_by_name(UCLASS_MISC
, "msmc", &dev
);
225 panic("Probe of msmc failed: %d\n", ret
);
227 ret
= uclass_get_device(UCLASS_RAM
, 0, &dev
);
229 panic("DRAM 0 init failed: %d\n", ret
);
231 ret
= uclass_next_device_err(&dev
);
233 panic("DRAM 1 init failed: %d\n", ret
);
238 /* Support for the various EVM / SK families */
239 #if defined(CONFIG_SPL_OF_LIST) && defined(CONFIG_TI_I2C_BOARD_DETECT)
240 void do_dt_magic(void)
242 int ret
, rescan
, mmc_dev
= -1;
243 static struct mmc
*mmc
;
248 * Board detection has been done.
249 * Let us see if another dtb wouldn't be a better match
252 if (IS_ENABLED(CONFIG_CPU_V7R
)) {
253 ret
= fdtdec_resetup(&rescan
);
254 if (!ret
&& rescan
) {
256 dm_init_and_scan(true);
261 * Because of multi DTB configuration, the MMC device has
262 * to be re-initialized after reconfiguring FDT inorder to
263 * boot from MMC. Do this when boot mode is MMC and ROM has
266 switch (spl_boot_device()) {
267 case BOOT_DEVICE_MMC1
:
270 case BOOT_DEVICE_MMC2
:
271 case BOOT_DEVICE_MMC2_2
:
276 if (mmc_dev
> 0 && !check_rom_loaded_sysfw()) {
277 ret
= mmc_init_device(mmc_dev
);
279 mmc
= find_mmc_device(mmc_dev
);
283 printf("mmc init failed with error: %d\n", ret
);
290 #ifdef CONFIG_SPL_BUILD
291 void board_init_f(ulong dummy
)
294 #if defined(CONFIG_SPL_OF_LIST) && defined(CONFIG_TI_I2C_BOARD_DETECT)
301 u32
spl_mmc_boot_mode(struct mmc
*mmc
, const u32 boot_device
)
303 switch (boot_device
) {
304 case BOOT_DEVICE_MMC1
:
305 return MMCSD_MODE_EMMCBOOT
;
306 case BOOT_DEVICE_MMC2
:
307 return MMCSD_MODE_FS
;
309 return MMCSD_MODE_RAW
;
313 static u32
__get_backup_bootmedia(u32 main_devstat
)
315 u32 bkup_boot
= (main_devstat
& MAIN_DEVSTAT_BKUP_BOOTMODE_MASK
) >>
316 MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT
;
319 case BACKUP_BOOT_DEVICE_USB
:
320 return BOOT_DEVICE_DFU
;
321 case BACKUP_BOOT_DEVICE_UART
:
322 return BOOT_DEVICE_UART
;
323 case BACKUP_BOOT_DEVICE_ETHERNET
:
324 return BOOT_DEVICE_ETHERNET
;
325 case BACKUP_BOOT_DEVICE_MMC2
:
327 u32 port
= (main_devstat
& MAIN_DEVSTAT_BKUP_MMC_PORT_MASK
) >>
328 MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT
;
330 return BOOT_DEVICE_MMC1
;
331 return BOOT_DEVICE_MMC2
;
333 case BACKUP_BOOT_DEVICE_SPI
:
334 return BOOT_DEVICE_SPI
;
335 case BACKUP_BOOT_DEVICE_I2C
:
336 return BOOT_DEVICE_I2C
;
339 return BOOT_DEVICE_RAM
;
342 static u32
__get_primary_bootmedia(u32 main_devstat
, u32 wkup_devstat
)
344 u32 bootmode
= (wkup_devstat
& WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK
) >>
345 WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT
;
347 bootmode
|= (main_devstat
& MAIN_DEVSTAT_BOOT_MODE_B_MASK
) <<
350 if (bootmode
== BOOT_DEVICE_OSPI
|| bootmode
== BOOT_DEVICE_QSPI
||
351 bootmode
== BOOT_DEVICE_XSPI
)
352 bootmode
= BOOT_DEVICE_SPI
;
354 if (bootmode
== BOOT_DEVICE_MMC2
) {
355 u32 port
= (main_devstat
&
356 MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK
) >>
357 MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT
;
359 bootmode
= BOOT_DEVICE_MMC1
;
365 u32
spl_boot_device(void)
367 u32 wkup_devstat
= readl(CTRLMMR_WKUP_DEVSTAT
);
370 if (wkup_devstat
& WKUP_DEVSTAT_MCU_OMLY_MASK
) {
371 printf("ERROR: MCU only boot is not yet supported\n");
372 return BOOT_DEVICE_RAM
;
375 /* MAIN CTRL MMR can only be read if MCU ONLY is 0 */
376 main_devstat
= readl(CTRLMMR_MAIN_DEVSTAT
);
378 if (bootindex
== K3_PRIMARY_BOOTMODE
)
379 return __get_primary_bootmedia(main_devstat
, wkup_devstat
);
381 return __get_backup_bootmedia(main_devstat
);