arch/arm/mach-sunxi/Kconfig

   1 if ARCH_SUNXI
   2
   3 config SPL_LDSCRIPT
   4         default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
   5
   6 config IDENT_STRING
   7         default " Allwinner Technology"
   8
   9 config DRAM_SUN4I
  10         bool
  11         help
  12           Select this dram controller driver for Sun4/5/7i platforms,
  13           like A10/A13/A20.
  14
  15 config DRAM_SUN6I
  16         bool
  17         help
  18           Select this dram controller driver for Sun6i platforms,
  19           like A31/A31s.
  20
  21 config DRAM_SUN8I_A23
  22         bool
  23         help
  24           Select this dram controller driver for Sun8i platforms,
  25           for A23 SOC.
  26
  27 config DRAM_SUN8I_A33
  28         bool
  29         help
  30           Select this dram controller driver for Sun8i platforms,
  31           for A33 SOC.
  32
  33 config DRAM_SUN8I_A83T
  34         bool
  35         help
  36           Select this dram controller driver for Sun8i platforms,
  37           for A83T SOC.
  38
  39 config DRAM_SUN9I
  40         bool
  41         help
  42           Select this dram controller driver for Sun9i platforms,
  43           like A80.
  44
  45 config DRAM_SUN50I_H6
  46         bool
  47         help
  48           Select this dram controller driver for some sun50i platforms,
  49           like H6.
  50
  51 config SUN6I_P2WI
  52         bool "Allwinner sun6i internal P2WI controller"
  53         help
  54           If you say yes to this option, support will be included for the
  55           P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi
  56           SOCs.
  57           The P2WI looks like an SMBus controller (which supports only byte
  58           accesses), except that it only supports one slave device.
  59           This interface is used to connect to specific PMIC devices (like the
  60           AXP221).
  61
  62 config SUN6I_PRCM
  63         bool
  64         help
  65           Support for the PRCM (Power/Reset/Clock Management) unit available
  66           in A31 SoC.
  67
  68 config AXP_PMIC_BUS
  69         bool "Sunxi AXP PMIC bus access helpers"
  70         help
  71           Select this PMIC bus access helpers for Sunxi platform PRCM or other
  72           AXP family PMIC devices.
  73
  74 config SUN8I_RSB
  75         bool "Allwinner sunXi Reduced Serial Bus Driver"
  76         help
  77           Say y here to enable support for Allwinner's Reduced Serial Bus
  78           (RSB) support. This controller is responsible for communicating
  79           with various RSB based devices, such as AXP223, AXP8XX PMICs,
  80           and AC100/AC200 ICs.
  81
  82 config SUNXI_SRAM_ADDRESS
  83         hex
  84         default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
  85         default 0x20000 if MACH_SUN50I_H6
  86         default 0x0
  87         ---help---
  88         Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
  89         with the first SRAM region being located at address 0.
  90         Some newer SoCs map the boot ROM at address 0 instead and move the
  91         SRAM to a different address.
  92
  93 config SUNXI_A64_TIMER_ERRATUM
  94         bool
  95
  96 # Note only one of these may be selected at a time! But hidden choices are
  97 # not supported by Kconfig
  98 config SUNXI_GEN_SUN4I
  99         bool
 100         ---help---
 101         Select this for sunxi SoCs which have resets and clocks set up
 102         as the original A10 (mach-sun4i).
 103
 104 config SUNXI_GEN_SUN6I
 105         bool
 106         ---help---
 107         Select this for sunxi SoCs which have sun6i like periphery, like
 108         separate ahb reset control registers, custom pmic bus, new style
 109         watchdog, etc.
 110
 111 config SUNXI_DRAM_DW
 112         bool
 113         ---help---
 114         Select this for sunxi SoCs which uses a DRAM controller like the
 115         DesignWare controller used in H3, mainly SoCs after H3, which do
 116         not have official open-source DRAM initialization code, but can
 117         use modified H3 DRAM initialization code.
 118
 119 if SUNXI_DRAM_DW
 120 config SUNXI_DRAM_DW_16BIT
 121         bool
 122         ---help---
 123         Select this for sunxi SoCs with DesignWare DRAM controller and
 124         have only 16-bit memory buswidth.
 125
 126 config SUNXI_DRAM_DW_32BIT
 127         bool
 128         ---help---
 129         Select this for sunxi SoCs with DesignWare DRAM controller with
 130         32-bit memory buswidth.
 131 endif
 132
 133 config MACH_SUNXI_H3_H5
 134         bool
 135         select DM_I2C
 136         select PHY_SUN4I_USB
 137         select SUNXI_DE2
 138         select SUNXI_DRAM_DW
 139         select SUNXI_DRAM_DW_32BIT
 140         select SUNXI_GEN_SUN6I
 141         select SUPPORT_SPL
 142
 143 # TODO: try out A80's 8GiB DRAM space
 144 config SUNXI_DRAM_MAX_SIZE
 145         hex
 146         default 0xC0000000 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6
 147         default 0x80000000
 148
 149 choice
 150         prompt "Sunxi SoC Variant"
 151         optional
 152
 153 config MACH_SUN4I
 154         bool "sun4i (Allwinner A10)"
 155         select CPU_V7A
 156         select ARM_CORTEX_CPU_IS_UP
 157         select DM_MMC if MMC
 158         select DM_SCSI if SCSI
 159         select PHY_SUN4I_USB
 160         select DRAM_SUN4I
 161         select SUNXI_GEN_SUN4I
 162         select SUPPORT_SPL
 163
 164 config MACH_SUN5I
 165         bool "sun5i (Allwinner A13)"
 166         select CPU_V7A
 167         select ARM_CORTEX_CPU_IS_UP
 168         select DM_MMC if MMC
 169         select DRAM_SUN4I
 170         select PHY_SUN4I_USB
 171         select SUNXI_GEN_SUN4I
 172         select SUPPORT_SPL
 173         imply CONS_INDEX_2 if !DM_SERIAL
 174
 175 config MACH_SUN6I
 176         bool "sun6i (Allwinner A31)"
 177         select CPU_V7A
 178         select CPU_V7_HAS_NONSEC
 179         select CPU_V7_HAS_VIRT
 180         select ARCH_SUPPORT_PSCI
 181         select DM_MMC if MMC
 182         select DRAM_SUN6I
 183         select PHY_SUN4I_USB
 184         select SUN6I_P2WI
 185         select SUN6I_PRCM
 186         select SUNXI_GEN_SUN6I
 187         select SUPPORT_SPL
 188         select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 189
 190 config MACH_SUN7I
 191         bool "sun7i (Allwinner A20)"
 192         select CPU_V7A
 193         select CPU_V7_HAS_NONSEC
 194         select CPU_V7_HAS_VIRT
 195         select ARCH_SUPPORT_PSCI
 196         select DRAM_SUN4I
 197         select PHY_SUN4I_USB
 198         select SUNXI_GEN_SUN4I
 199         select SUPPORT_SPL
 200         select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 201
 202 config MACH_SUN8I_A23
 203         bool "sun8i (Allwinner A23)"
 204         select CPU_V7A
 205         select CPU_V7_HAS_NONSEC
 206         select CPU_V7_HAS_VIRT
 207         select ARCH_SUPPORT_PSCI
 208         select DM_MMC if MMC
 209         select DRAM_SUN8I_A23
 210         select PHY_SUN4I_USB
 211         select SUNXI_GEN_SUN6I
 212         select SUPPORT_SPL
 213         select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 214         imply CONS_INDEX_5 if !DM_SERIAL
 215
 216 config MACH_SUN8I_A33
 217         bool "sun8i (Allwinner A33)"
 218         select CPU_V7A
 219         select CPU_V7_HAS_NONSEC
 220         select CPU_V7_HAS_VIRT
 221         select ARCH_SUPPORT_PSCI
 222         select DM_MMC if MMC
 223         select DRAM_SUN8I_A33
 224         select PHY_SUN4I_USB
 225         select SUNXI_GEN_SUN6I
 226         select SUPPORT_SPL
 227         select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 228         imply CONS_INDEX_5 if !DM_SERIAL
 229
 230 config MACH_SUN8I_A83T
 231         bool "sun8i (Allwinner A83T)"
 232         select CPU_V7A
 233         select DM_MMC if MMC
 234         select DRAM_SUN8I_A83T
 235         select PHY_SUN4I_USB
 236         select SUNXI_GEN_SUN6I
 237         select MMC_SUNXI_HAS_NEW_MODE
 238         select MMC_SUNXI_HAS_MODE_SWITCH
 239         select SUPPORT_SPL
 240
 241 config MACH_SUN8I_H3
 242         bool "sun8i (Allwinner H3)"
 243         select CPU_V7A
 244         select CPU_V7_HAS_NONSEC
 245         select CPU_V7_HAS_VIRT
 246         select ARCH_SUPPORT_PSCI
 247         select MACH_SUNXI_H3_H5
 248         select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 249         select DM_MMC if MMC
 250
 251 config MACH_SUN8I_R40
 252         bool "sun8i (Allwinner R40)"
 253         select CPU_V7A
 254         select CPU_V7_HAS_NONSEC
 255         select CPU_V7_HAS_VIRT
 256         select ARCH_SUPPORT_PSCI
 257         select SUNXI_GEN_SUN6I
 258         select SUPPORT_SPL
 259         select SUNXI_DRAM_DW
 260         select SUNXI_DRAM_DW_32BIT
 261
 262 config MACH_SUN8I_V3S
 263         bool "sun8i (Allwinner V3s)"
 264         select CPU_V7A
 265         select CPU_V7_HAS_NONSEC
 266         select CPU_V7_HAS_VIRT
 267         select ARCH_SUPPORT_PSCI
 268         select DM_MMC if MMC
 269         select SUNXI_GEN_SUN6I
 270         select SUNXI_DRAM_DW
 271         select SUNXI_DRAM_DW_16BIT
 272         select SUPPORT_SPL
 273         select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 274
 275 config MACH_SUN9I
 276         bool "sun9i (Allwinner A80)"
 277         select CPU_V7A
 278         select DRAM_SUN9I
 279         select SUN6I_PRCM
 280         select SUNXI_GEN_SUN6I
 281         select SUN8I_RSB
 282         select SUPPORT_SPL
 283         select DM_MMC if MMC
 284
 285 config MACH_SUN50I
 286         bool "sun50i (Allwinner A64)"
 287         select ARM64
 288         select DM_I2C
 289         select DM_MMC if MMC
 290         select PHY_SUN4I_USB
 291         select SUN6I_PRCM
 292         select SUNXI_DE2
 293         select SUNXI_GEN_SUN6I
 294         select MMC_SUNXI_HAS_NEW_MODE
 295         select SUPPORT_SPL
 296         select SUNXI_DRAM_DW
 297         select SUNXI_DRAM_DW_32BIT
 298         select FIT
 299         select SPL_LOAD_FIT
 300         select SUNXI_A64_TIMER_ERRATUM
 301
 302 config MACH_SUN50I_H5
 303         bool "sun50i (Allwinner H5)"
 304         select ARM64
 305         select MACH_SUNXI_H3_H5
 306         select DM_MMC if MMC
 307         select FIT
 308         select SPL_LOAD_FIT
 309
 310 config MACH_SUN50I_H6
 311         bool "sun50i (Allwinner H6)"
 312         select ARM64
 313         select SUPPORT_SPL
 314         select DM_MMC if MMC
 315         select FIT
 316         select SPL_LOAD_FIT
 317         select DRAM_SUN50I_H6
 318
 319 endchoice
 320
 321 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
 322 config MACH_SUN8I
 323         bool
 324         select SUN8I_RSB
 325         select SUN6I_PRCM
 326         default y if MACH_SUN8I_A23
 327         default y if MACH_SUN8I_A33
 328         default y if MACH_SUN8I_A83T
 329         default y if MACH_SUNXI_H3_H5
 330         default y if MACH_SUN8I_R40
 331         default y if MACH_SUN8I_V3S
 332
 333 config RESERVE_ALLWINNER_BOOT0_HEADER
 334         bool "reserve space for Allwinner boot0 header"
 335         select ENABLE_ARM_SOC_BOOT0_HOOK
 336         ---help---
 337         Prepend a 1536 byte (empty) header to the U-Boot image file, to be
 338         filled with magic values post build. The Allwinner provided boot0
 339         blob relies on this information to load and execute U-Boot.
 340         Only needed on 64-bit Allwinner boards so far when using boot0.
 341
 342 config ARM_BOOT_HOOK_RMR
 343         bool
 344         depends on ARM64
 345         default y
 346         select ENABLE_ARM_SOC_BOOT0_HOOK
 347         ---help---
 348         Insert some ARM32 code at the very beginning of the U-Boot binary
 349         which uses an RMR register write to bring the core into AArch64 mode.
 350         The very first instruction acts as a switch, since it's carefully
 351         chosen to be a NOP in one mode and a branch in the other, so the
 352         code would only be executed if not already in AArch64.
 353         This allows both the SPL and the U-Boot proper to be entered in
 354         either mode and switch to AArch64 if needed.
 355
 356 if SUNXI_DRAM_DW
 357 config SUNXI_DRAM_DDR3
 358         bool
 359
 360 config SUNXI_DRAM_DDR2
 361         bool
 362
 363 config SUNXI_DRAM_LPDDR3
 364         bool
 365
 366 choice
 367         prompt "DRAM Type and Timing"
 368         default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
 369         default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
 370
 371 config SUNXI_DRAM_DDR3_1333
 372         bool "DDR3 1333"
 373         select SUNXI_DRAM_DDR3
 374         depends on !MACH_SUN8I_V3S
 375         ---help---
 376         This option is the original only supported memory type, which suits
 377         many H3/H5/A64 boards available now.
 378
 379 config SUNXI_DRAM_LPDDR3_STOCK
 380         bool "LPDDR3 with Allwinner stock configuration"
 381         select SUNXI_DRAM_LPDDR3
 382         ---help---
 383         This option is the LPDDR3 timing used by the stock boot0 by
 384         Allwinner.
 385
 386 config SUNXI_DRAM_DDR2_V3S
 387         bool "DDR2 found in V3s chip"
 388         select SUNXI_DRAM_DDR2
 389         depends on MACH_SUN8I_V3S
 390         ---help---
 391         This option is only for the DDR2 memory chip which is co-packaged in
 392         Allwinner V3s SoC.
 393
 394 endchoice
 395 endif
 396
 397 config DRAM_TYPE
 398         int "sunxi dram type"
 399         depends on MACH_SUN8I_A83T
 400         default 3
 401         ---help---
 402         Set the dram type, 3: DDR3, 7: LPDDR3
 403
 404 config DRAM_CLK
 405         int "sunxi dram clock speed"
 406         default 792 if MACH_SUN9I
 407         default 648 if MACH_SUN8I_R40
 408         default 312 if MACH_SUN6I || MACH_SUN8I
 409         default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
 410                        MACH_SUN8I_V3S
 411         default 672 if MACH_SUN50I
 412         default 744 if MACH_SUN50I_H6
 413         ---help---
 414         Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
 415         must be a multiple of 24. For the sun9i (A80), the tested values
 416         (for DDR3-1600) are 312 to 792.
 417
 418 if MACH_SUN5I || MACH_SUN7I
 419 config DRAM_MBUS_CLK
 420         int "sunxi mbus clock speed"
 421         default 300
 422         ---help---
 423         Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
 424
 425 endif
 426
 427 config DRAM_ZQ
 428         int "sunxi dram zq value"
 429         default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || \
 430                        MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_A83T
 431         default 127 if MACH_SUN7I
 432         default 14779 if MACH_SUN8I_V3S
 433         default 3881979 if MACH_SUNXI_H3_H5 || MACH_SUN8I_R40 || MACH_SUN50I_H6
 434         default 4145117 if MACH_SUN9I
 435         default 3881915 if MACH_SUN50I
 436         ---help---
 437         Set the dram zq value.
 438
 439 config DRAM_ODT_EN
 440         bool "sunxi dram odt enable"
 441         default y if MACH_SUN8I_A23
 442         default y if MACH_SUNXI_H3_H5
 443         default y if MACH_SUN8I_R40
 444         default y if MACH_SUN50I
 445         default y if MACH_SUN50I_H6
 446         ---help---
 447         Select this to enable dram odt (on die termination).
 448
 449 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
 450 config DRAM_EMR1
 451         int "sunxi dram emr1 value"
 452         default 0 if MACH_SUN4I
 453         default 4 if MACH_SUN5I || MACH_SUN7I
 454         ---help---
 455         Set the dram controller emr1 value.
 456
 457 config DRAM_TPR3
 458         hex "sunxi dram tpr3 value"
 459         default 0
 460         ---help---
 461         Set the dram controller tpr3 parameter. This parameter configures
 462         the delay on the command lane and also phase shifts, which are
 463         applied for sampling incoming read data. The default value 0
 464         means that no phase/delay adjustments are necessary. Properly
 465         configuring this parameter increases reliability at high DRAM
 466         clock speeds.
 467
 468 config DRAM_DQS_GATING_DELAY
 469         hex "sunxi dram dqs_gating_delay value"
 470         default 0
 471         ---help---
 472         Set the dram controller dqs_gating_delay parmeter. Each byte
 473         encodes the DQS gating delay for each byte lane. The delay
 474         granularity is 1/4 cycle. For example, the value 0x05060606
 475         means that the delay is 5 quarter-cycles for one lane (1.25
 476         cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
 477         The default value 0 means autodetection. The results of hardware
 478         autodetection are not very reliable and depend on the chip
 479         temperature (sometimes producing different results on cold start
 480         and warm reboot). But the accuracy of hardware autodetection
 481         is usually good enough, unless running at really high DRAM
 482         clocks speeds (up to 600MHz). If unsure, keep as 0.
 483
 484 choice
 485         prompt "sunxi dram timings"
 486         default DRAM_TIMINGS_VENDOR_MAGIC
 487         ---help---
 488         Select the timings of the DDR3 chips.
 489
 490 config DRAM_TIMINGS_VENDOR_MAGIC
 491         bool "Magic vendor timings from Android"
 492         ---help---
 493         The same DRAM timings as in the Allwinner boot0 bootloader.
 494
 495 config DRAM_TIMINGS_DDR3_1066F_1333H
 496         bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
 497         ---help---
 498         Use the timings of the standard JEDEC DDR3-1066F speed bin for
 499         DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
 500         for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
 501         used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
 502         or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
 503         that down binning to DDR3-1066F is supported (because DDR3-1066F
 504         uses a bit faster timings than DDR3-1333H).
 505
 506 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
 507         bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
 508         ---help---
 509         Use the timings of the slowest possible JEDEC speed bin for the
 510         selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
 511         DDR3-800E, DDR3-1066G or DDR3-1333J.
 512
 513 endchoice
 514
 515 endif
 516
 517 if MACH_SUN8I_A23
 518 config DRAM_ODT_CORRECTION
 519         int "sunxi dram odt correction value"
 520         default 0
 521         ---help---
 522         Set the dram odt correction value (range -255 - 255). In allwinner
 523         fex files, this option is found in bits 8-15 of the u32 odt_en variable
 524         in the [dram] section. When bit 31 of the odt_en variable is set
 525         then the correction is negative. Usually the value for this is 0.
 526 endif
 527
 528 config SYS_CLK_FREQ
 529         default 1008000000 if MACH_SUN4I
 530         default 1008000000 if MACH_SUN5I
 531         default 1008000000 if MACH_SUN6I
 532         default 912000000 if MACH_SUN7I
 533         default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
 534         default 1008000000 if MACH_SUN8I
 535         default 1008000000 if MACH_SUN9I
 536         default 888000000 if MACH_SUN50I_H6
 537
 538 config SYS_CONFIG_NAME
 539         default "sun4i" if MACH_SUN4I
 540         default "sun5i" if MACH_SUN5I
 541         default "sun6i" if MACH_SUN6I
 542         default "sun7i" if MACH_SUN7I
 543         default "sun8i" if MACH_SUN8I
 544         default "sun9i" if MACH_SUN9I
 545         default "sun50i" if MACH_SUN50I
 546         default "sun50i" if MACH_SUN50I_H6
 547
 548 config SYS_BOARD
 549         default "sunxi"
 550
 551 config SYS_SOC
 552         default "sunxi"
 553
 554 config UART0_PORT_F
 555         bool "UART0 on MicroSD breakout board"
 556         default n
 557         ---help---
 558         Repurpose the SD card slot for getting access to the UART0 serial
 559         console. Primarily useful only for low level u-boot debugging on
 560         tablets, where normal UART0 is difficult to access and requires
 561         device disassembly and/or soldering. As the SD card can't be used
 562         at the same time, the system can be only booted in the FEL mode.
 563         Only enable this if you really know what you are doing.
 564
 565 config OLD_SUNXI_KERNEL_COMPAT
 566         bool "Enable workarounds for booting old kernels"
 567         default n
 568         ---help---
 569         Set this to enable various workarounds for old kernels, this results in
 570         sub-optimal settings for newer kernels, only enable if needed.
 571
 572 config MACPWR
 573         string "MAC power pin"
 574         default ""
 575         help
 576           Set the pin used to power the MAC. This takes a string in the format
 577           understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 578
 579 config MMC0_CD_PIN
 580         string "Card detect pin for mmc0"
 581         default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
 582         default ""
 583         ---help---
 584         Set the card detect pin for mmc0, leave empty to not use cd. This
 585         takes a string in the format understood by sunxi_name_to_gpio, e.g.
 586         PH1 for pin 1 of port H.
 587
 588 config MMC1_CD_PIN
 589         string "Card detect pin for mmc1"
 590         default ""
 591         ---help---
 592         See MMC0_CD_PIN help text.
 593
 594 config MMC2_CD_PIN
 595         string "Card detect pin for mmc2"
 596         default ""
 597         ---help---
 598         See MMC0_CD_PIN help text.
 599
 600 config MMC3_CD_PIN
 601         string "Card detect pin for mmc3"
 602         default ""
 603         ---help---
 604         See MMC0_CD_PIN help text.
 605
 606 config MMC1_PINS
 607         string "Pins for mmc1"
 608         default ""
 609         ---help---
 610         Set the pins used for mmc1, when applicable. This takes a string in the
 611         format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
 612
 613 config MMC2_PINS
 614         string "Pins for mmc2"
 615         default ""
 616         ---help---
 617         See MMC1_PINS help text.
 618
 619 config MMC3_PINS
 620         string "Pins for mmc3"
 621         default ""
 622         ---help---
 623         See MMC1_PINS help text.
 624
 625 config MMC_SUNXI_SLOT_EXTRA
 626         int "mmc extra slot number"
 627         default -1
 628         ---help---
 629         sunxi builds always enable mmc0, some boards also have a second sdcard
 630         slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
 631         support for this.
 632
 633 config INITIAL_USB_SCAN_DELAY
 634         int "delay initial usb scan by x ms to allow builtin devices to init"
 635         default 0
 636         ---help---
 637         Some boards have on board usb devices which need longer than the
 638         USB spec's 1 second to connect from board powerup. Set this config
 639         option to a non 0 value to add an extra delay before the first usb
 640         bus scan.
 641
 642 config USB0_VBUS_PIN
 643         string "Vbus enable pin for usb0 (otg)"
 644         default ""
 645         ---help---
 646         Set the Vbus enable pin for usb0 (otg). This takes a string in the
 647         format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 648
 649 config USB0_VBUS_DET
 650         string "Vbus detect pin for usb0 (otg)"
 651         default ""
 652         ---help---
 653         Set the Vbus detect pin for usb0 (otg). This takes a string in the
 654         format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 655
 656 config USB0_ID_DET
 657         string "ID detect pin for usb0 (otg)"
 658         default ""
 659         ---help---
 660         Set the ID detect pin for usb0 (otg). This takes a string in the
 661         format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 662
 663 config USB1_VBUS_PIN
 664         string "Vbus enable pin for usb1 (ehci0)"
 665         default "PH6" if MACH_SUN4I || MACH_SUN7I
 666         default "PH27" if MACH_SUN6I
 667         ---help---
 668         Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
 669         a string in the format understood by sunxi_name_to_gpio, e.g.
 670         PH1 for pin 1 of port H.
 671
 672 config USB2_VBUS_PIN
 673         string "Vbus enable pin for usb2 (ehci1)"
 674         default "PH3" if MACH_SUN4I || MACH_SUN7I
 675         default "PH24" if MACH_SUN6I
 676         ---help---
 677         See USB1_VBUS_PIN help text.
 678
 679 config USB3_VBUS_PIN
 680         string "Vbus enable pin for usb3 (ehci2)"
 681         default ""
 682         ---help---
 683         See USB1_VBUS_PIN help text.
 684
 685 config I2C0_ENABLE
 686         bool "Enable I2C/TWI controller 0"
 687         default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
 688         default n if MACH_SUN6I || MACH_SUN8I
 689         select CMD_I2C
 690         ---help---
 691         This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
 692         its clock and setting up the bus. This is especially useful on devices
 693         with slaves connected to the bus or with pins exposed through e.g. an
 694         expansion port/header.
 695
 696 config I2C1_ENABLE
 697         bool "Enable I2C/TWI controller 1"
 698         default n
 699         select CMD_I2C
 700         ---help---
 701         See I2C0_ENABLE help text.
 702
 703 config I2C2_ENABLE
 704         bool "Enable I2C/TWI controller 2"
 705         default n
 706         select CMD_I2C
 707         ---help---
 708         See I2C0_ENABLE help text.
 709
 710 if MACH_SUN6I || MACH_SUN7I
 711 config I2C3_ENABLE
 712         bool "Enable I2C/TWI controller 3"
 713         default n
 714         select CMD_I2C
 715         ---help---
 716         See I2C0_ENABLE help text.
 717 endif
 718
 719 if SUNXI_GEN_SUN6I
 720 config R_I2C_ENABLE
 721         bool "Enable the PRCM I2C/TWI controller"
 722         # This is used for the pmic on H3
 723         default y if SY8106A_POWER
 724         select CMD_I2C
 725         ---help---
 726         Set this to y to enable the I2C controller which is part of the PRCM.
 727 endif
 728
 729 if MACH_SUN7I
 730 config I2C4_ENABLE
 731         bool "Enable I2C/TWI controller 4"
 732         default n
 733         select CMD_I2C
 734         ---help---
 735         See I2C0_ENABLE help text.
 736 endif
 737
 738 config AXP_GPIO
 739         bool "Enable support for gpio-s on axp PMICs"
 740         default n
 741         ---help---
 742         Say Y here to enable support for the gpio pins of the axp PMIC ICs.
 743
 744 config VIDEO_SUNXI
 745         bool "Enable graphical uboot console on HDMI, LCD or VGA"
 746         depends on !MACH_SUN8I_A83T
 747         depends on !MACH_SUNXI_H3_H5
 748         depends on !MACH_SUN8I_R40
 749         depends on !MACH_SUN8I_V3S
 750         depends on !MACH_SUN9I
 751         depends on !MACH_SUN50I
 752         depends on !MACH_SUN50I_H6
 753         select VIDEO
 754         imply VIDEO_DT_SIMPLEFB
 755         default y
 756         ---help---
 757         Say Y here to add support for using a cfb console on the HDMI, LCD
 758         or VGA output found on most sunxi devices. See doc/README.video for
 759         info on how to select the video output and mode.
 760
 761 config VIDEO_HDMI
 762         bool "HDMI output support"
 763         depends on VIDEO_SUNXI && !MACH_SUN8I
 764         default y
 765         ---help---
 766         Say Y here to add support for outputting video over HDMI.
 767
 768 config VIDEO_VGA
 769         bool "VGA output support"
 770         depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
 771         default n
 772         ---help---
 773         Say Y here to add support for outputting video over VGA.
 774
 775 config VIDEO_VGA_VIA_LCD
 776         bool "VGA via LCD controller support"
 777         depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
 778         default n
 779         ---help---
 780         Say Y here to add support for external DACs connected to the parallel
 781         LCD interface driving a VGA connector, such as found on the
 782         Olimex A13 boards.
 783
 784 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
 785         bool "Force sync active high for VGA via LCD controller support"
 786         depends on VIDEO_VGA_VIA_LCD
 787         default n
 788         ---help---
 789         Say Y here if you've a board which uses opendrain drivers for the vga
 790         hsync and vsync signals. Opendrain drivers cannot generate steep enough
 791         positive edges for a stable video output, so on boards with opendrain
 792         drivers the sync signals must always be active high.
 793
 794 config VIDEO_VGA_EXTERNAL_DAC_EN
 795         string "LCD panel power enable pin"
 796         depends on VIDEO_VGA_VIA_LCD
 797         default ""
 798         ---help---
 799         Set the enable pin for the external VGA DAC. This takes a string in the
 800         format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 801
 802 config VIDEO_COMPOSITE
 803         bool "Composite video output support"
 804         depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
 805         default n
 806         ---help---
 807         Say Y here to add support for outputting composite video.
 808
 809 config VIDEO_LCD_MODE
 810         string "LCD panel timing details"
 811         depends on VIDEO_SUNXI
 812         default ""
 813         ---help---
 814         LCD panel timing details string, leave empty if there is no LCD panel.
 815         This is in drivers/video/videomodes.c: video_get_params() format, e.g.
 816         x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
 817         Also see: http://linux-sunxi.org/LCD
 818
 819 config VIDEO_LCD_DCLK_PHASE
 820         int "LCD panel display clock phase"
 821         depends on VIDEO_SUNXI || DM_VIDEO
 822         default 1
 823         ---help---
 824         Select LCD panel display clock phase shift, range 0-3.
 825
 826 config VIDEO_LCD_POWER
 827         string "LCD panel power enable pin"
 828         depends on VIDEO_SUNXI
 829         default ""
 830         ---help---
 831         Set the power enable pin for the LCD panel. This takes a string in the
 832         format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 833
 834 config VIDEO_LCD_RESET
 835         string "LCD panel reset pin"
 836         depends on VIDEO_SUNXI
 837         default ""
 838         ---help---
 839         Set the reset pin for the LCD panel. This takes a string in the format
 840         understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 841
 842 config VIDEO_LCD_BL_EN
 843         string "LCD panel backlight enable pin"
 844         depends on VIDEO_SUNXI
 845         default ""
 846         ---help---
 847         Set the backlight enable pin for the LCD panel. This takes a string in the
 848         the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
 849         port H.
 850
 851 config VIDEO_LCD_BL_PWM
 852         string "LCD panel backlight pwm pin"
 853         depends on VIDEO_SUNXI
 854         default ""
 855         ---help---
 856         Set the backlight pwm pin for the LCD panel. This takes a string in the
 857         format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 858
 859 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
 860         bool "LCD panel backlight pwm is inverted"
 861         depends on VIDEO_SUNXI
 862         default y
 863         ---help---
 864         Set this if the backlight pwm output is active low.
 865
 866 config VIDEO_LCD_PANEL_I2C
 867         bool "LCD panel needs to be configured via i2c"
 868         depends on VIDEO_SUNXI
 869         default n
 870         select CMD_I2C
 871         ---help---
 872         Say y here if the LCD panel needs to be configured via i2c. This
 873         will add a bitbang i2c controller using gpios to talk to the LCD.
 874
 875 config VIDEO_LCD_PANEL_I2C_SDA
 876         string "LCD panel i2c interface SDA pin"
 877         depends on VIDEO_LCD_PANEL_I2C
 878         default "PG12"
 879         ---help---
 880         Set the SDA pin for the LCD i2c interface. This takes a string in the
 881         format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 882
 883 config VIDEO_LCD_PANEL_I2C_SCL
 884         string "LCD panel i2c interface SCL pin"
 885         depends on VIDEO_LCD_PANEL_I2C
 886         default "PG10"
 887         ---help---
 888         Set the SCL pin for the LCD i2c interface. This takes a string in the
 889         format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 890
 891
 892 # Note only one of these may be selected at a time! But hidden choices are
 893 # not supported by Kconfig
 894 config VIDEO_LCD_IF_PARALLEL
 895         bool
 896
 897 config VIDEO_LCD_IF_LVDS
 898         bool
 899
 900 config SUNXI_DE2
 901         bool
 902         default n
 903
 904 config VIDEO_DE2
 905         bool "Display Engine 2 video driver"
 906         depends on SUNXI_DE2
 907         select DM_VIDEO
 908         select DISPLAY
 909         imply VIDEO_DT_SIMPLEFB
 910         default y
 911         ---help---
 912         Say y here if you want to build DE2 video driver which is present on
 913         newer SoCs. Currently only HDMI output is supported.
 914
 915
 916 choice
 917         prompt "LCD panel support"
 918         depends on VIDEO_SUNXI
 919         ---help---
 920         Select which type of LCD panel to support.
 921
 922 config VIDEO_LCD_PANEL_PARALLEL
 923         bool "Generic parallel interface LCD panel"
 924         select VIDEO_LCD_IF_PARALLEL
 925
 926 config VIDEO_LCD_PANEL_LVDS
 927         bool "Generic lvds interface LCD panel"
 928         select VIDEO_LCD_IF_LVDS
 929
 930 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
 931         bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
 932         select VIDEO_LCD_SSD2828
 933         select VIDEO_LCD_IF_PARALLEL
 934         ---help---
 935         7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
 936
 937 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
 938         bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
 939         select VIDEO_LCD_ANX9804
 940         select VIDEO_LCD_IF_PARALLEL
 941         select VIDEO_LCD_PANEL_I2C
 942         ---help---
 943         Select this for eDP LCD panels with 4 lanes running at 1.62G,
 944         connected via an ANX9804 bridge chip.
 945
 946 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
 947         bool "Hitachi tx18d42vm LCD panel"
 948         select VIDEO_LCD_HITACHI_TX18D42VM
 949         select VIDEO_LCD_IF_LVDS
 950         ---help---
 951         7.85" 1024x768 Hitachi tx18d42vm LCD panel support
 952
 953 config VIDEO_LCD_TL059WV5C0
 954         bool "tl059wv5c0 LCD panel"
 955         select VIDEO_LCD_PANEL_I2C
 956         select VIDEO_LCD_IF_PARALLEL
 957         ---help---
 958         6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
 959         Aigo M60/M608/M606 tablets.
 960
 961 endchoice
 962
 963 config SATAPWR
 964         string "SATA power pin"
 965         default ""
 966         help
 967           Set the pins used to power the SATA. This takes a string in the
 968           format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
 969           port H.
 970
 971 config GMAC_TX_DELAY
 972         int "GMAC Transmit Clock Delay Chain"
 973         default 0
 974         ---help---
 975         Set the GMAC Transmit Clock Delay Chain value.
 976
 977 config SPL_STACK_R_ADDR
 978         default 0x4fe00000 if MACH_SUN4I
 979         default 0x4fe00000 if MACH_SUN5I
 980         default 0x4fe00000 if MACH_SUN6I
 981         default 0x4fe00000 if MACH_SUN7I
 982         default 0x4fe00000 if MACH_SUN8I
 983         default 0x2fe00000 if MACH_SUN9I
 984         default 0x4fe00000 if MACH_SUN50I
 985         default 0x4fe00000 if MACH_SUN50I_H6
 986
 987 config SPL_SPI_SUNXI
 988         bool "Support for SPI Flash on Allwinner SoCs in SPL"
 989         depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
 990         help
 991           Enable support for SPI Flash. This option allows SPL to read from
 992           sunxi SPI Flash. It uses the same method as the boot ROM, so does
 993           not need any extra configuration.
 994
 995 config PINE64_DT_SELECTION
 996         bool "Enable Pine64 device tree selection code"
 997         depends on MACH_SUN50I
 998         help
 999           The original Pine A64 and Pine A64+ are similar but different
1000           boards and can be differed by the DRAM size. Pine A64 has
1001           512MiB DRAM, and Pine A64+ has 1GiB or 2GiB. By selecting this
1002           option, the device tree selection code specific to Pine64 which
1003           utilizes the DRAM size will be enabled.
1004
1005 endif