arch/arm/mach-zynqmp/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2015 - 2016 Xilinx, Inc.
   4  *
   5  * Michal Simek <michal.simek@xilinx.com>
   6  */
   7
   8 #include <common.h>
   9 #include <debug_uart.h>
  10 #include <spl.h>
  11
  12 #include <asm/io.h>
  13 #include <asm/spl.h>
  14 #include <asm/arch/hardware.h>
  15 #include <asm/arch/sys_proto.h>
  16
  17 void board_init_f(ulong dummy)
  18 {
  19         board_early_init_f();
  20         board_early_init_r();
  21
  22 #ifdef CONFIG_DEBUG_UART
  23         /* Uart debug for sure */
  24         debug_uart_init();
  25         puts("Debug uart enabled\n"); /* or printch() */
  26 #endif
  27         /* Delay is required for clocks to be propagated */
  28         udelay(1000000);
  29
  30         /* Clear the BSS */
  31         memset(__bss_start, 0, __bss_end - __bss_start);
  32
  33         /* No need to call timer init - it is empty for ZynqMP */
  34         board_init_r(NULL, 0);
  35 }
  36
  37 static void ps_mode_reset(ulong mode)
  38 {
  39         writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
  40                &crlapb_base->boot_pin_ctrl);
  41         udelay(5);
  42         writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT |
  43                mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
  44                &crlapb_base->boot_pin_ctrl);
  45 }
  46
  47 /*
  48  * Set default PS_MODE1 which is used for USB ULPI phy reset
  49  * Also other resets can be connected to this certain pin
  50  */
  51 #ifndef MODE_RESET
  52 # define MODE_RESET     PS_MODE1
  53 #endif
  54
  55 #ifdef CONFIG_SPL_BOARD_INIT
  56 void spl_board_init(void)
  57 {
  58         preloader_console_init();
  59         ps_mode_reset(MODE_RESET);
  60         board_init();
  61 }
  62 #endif
  63
  64 u32 spl_boot_device(void)
  65 {
  66         u32 reg = 0;
  67         u8 bootmode;
  68
  69 #if defined(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE_ENABLED)
  70         /* Change default boot mode at run-time */
  71         writel(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE << BOOT_MODE_ALT_SHIFT,
  72                &crlapb_base->boot_mode);
  73 #endif
  74
  75         reg = readl(&crlapb_base->boot_mode);
  76         if (reg >> BOOT_MODE_ALT_SHIFT)
  77                 reg >>= BOOT_MODE_ALT_SHIFT;
  78
  79         bootmode = reg & BOOT_MODES_MASK;
  80
  81         switch (bootmode) {
  82         case JTAG_MODE:
  83                 return BOOT_DEVICE_RAM;
  84 #ifdef CONFIG_SPL_MMC_SUPPORT
  85         case SD_MODE1:
  86         case SD1_LSHFT_MODE: /* not working on silicon v1 */
  87 /* if both controllers enabled, then these two are the second controller */
  88 #if defined(SPL_ZYNQMP_TWO_SDHCI)
  89                 return BOOT_DEVICE_MMC2;
  90 /* else, fall through, the one SDHCI controller that is enabled is number 1 */
  91 #endif
  92         case SD_MODE:
  93         case EMMC_MODE:
  94                 return BOOT_DEVICE_MMC1;
  95 #endif
  96 #ifdef CONFIG_SPL_DFU
  97         case USB_MODE:
  98                 return BOOT_DEVICE_DFU;
  99 #endif
 100 #ifdef CONFIG_SPL_SATA_SUPPORT
 101         case SW_SATA_MODE:
 102                 return BOOT_DEVICE_SATA;
 103 #endif
 104 #ifdef CONFIG_SPL_SPI_SUPPORT
 105         case QSPI_MODE_24BIT:
 106         case QSPI_MODE_32BIT:
 107                 return BOOT_DEVICE_SPI;
 108 #endif
 109         default:
 110                 printf("Invalid Boot Mode:0x%x\n", bootmode);
 111                 break;
 112         }
 113
 114         return 0;
 115 }
 116
 117 #ifdef CONFIG_SPL_OS_BOOT
 118 int spl_start_uboot(void)
 119 {
 120         handoff_setup();
 121
 122         return 0;
 123 }
 124 #endif
 125
 126 #ifdef CONFIG_SPL_LOAD_FIT
 127 int board_fit_config_name_match(const char *name)
 128 {
 129         /* Just empty function now - can't decide what to choose */
 130         debug("%s: %s\n", __func__, name);
 131
 132         return 0;
 133 }
 134 #endif