1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2019 Google LLC
8 #include <asm/cpu_common.h>
9 #include <asm/fast_spi.h>
13 * Returns bios_start and fills in size of the BIOS region.
15 static ulong
fast_spi_get_bios_region(struct fast_spi_regs
*regs
,
18 ulong bios_start
, bios_end
;
21 * BIOS_BFPREG provides info about BIOS-Flash Primary Region Base and
22 * Limit. Base and Limit fields are in units of 4K.
24 u32 val
= readl(®s
->bfp
);
26 bios_start
= (val
& SPIBAR_BFPREG_PRB_MASK
) << 12;
27 bios_end
= (((val
& SPIBAR_BFPREG_PRL_MASK
) >>
28 SPIBAR_BFPREG_PRL_SHIFT
) + 1) << 12;
29 *bios_size
= bios_end
- bios_start
;
34 int fast_spi_get_bios_mmap_regs(struct fast_spi_regs
*regs
, ulong
*map_basep
,
35 uint
*map_sizep
, uint
*offsetp
)
39 base
= fast_spi_get_bios_region(regs
, map_sizep
);
40 *map_basep
= (u32
)-*map_sizep
- base
;
46 int fast_spi_get_bios_mmap(pci_dev_t pdev
, ulong
*map_basep
, uint
*map_sizep
,
49 struct fast_spi_regs
*regs
;
52 /* Special case to find mapping without probing the device */
53 pci_x86_read_config(pdev
, PCI_BASE_ADDRESS_0
, &bar
, PCI_SIZE_32
);
54 mmio_base
= bar
& PCI_BASE_ADDRESS_MEM_MASK
;
55 regs
= (struct fast_spi_regs
*)mmio_base
;
57 return fast_spi_get_bios_mmap_regs(regs
, map_basep
, map_sizep
, offsetp
);
60 int fast_spi_early_init(pci_dev_t pdev
, ulong mmio_base
)
62 /* Program Temporary BAR for SPI */
63 pci_x86_write_config(pdev
, PCI_BASE_ADDRESS_0
,
64 mmio_base
| PCI_BASE_ADDRESS_SPACE_MEMORY
,
67 /* Enable Bus Master and MMIO Space */
68 pci_x86_clrset_config(pdev
, PCI_COMMAND
, 0, PCI_COMMAND_MASTER
|
69 PCI_COMMAND_MEMORY
, PCI_SIZE_8
);
72 * Disable the BIOS write protect so write commands are allowed.
73 * Enable Prefetching and caching.
75 pci_x86_clrset_config(pdev
, SPIBAR_BIOS_CONTROL
,
76 SPIBAR_BIOS_CONTROL_EISS
|
77 SPIBAR_BIOS_CONTROL_CACHE_DISABLE
,
78 SPIBAR_BIOS_CONTROL_WPD
|
79 SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE
, PCI_SIZE_8
);