board/freescale/common/qixis.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2011 Freescale Semiconductor
   4  * Author: Shengzhou Liu <Shengzhou.Liu@freescale.com>
   5  *
   6  * This file provides support for the QIXIS of some Freescale reference boards.
   7  */
   8
   9 #include <common.h>
  10 #include <command.h>
  11 #include <asm/io.h>
  12 #include <linux/compiler.h>
  13 #include <linux/time.h>
  14 #include <i2c.h>
  15 #include "qixis.h"
  16
  17 #ifndef QIXIS_LBMAP_BRDCFG_REG
  18 /*
  19  * For consistency with existing platforms
  20  */
  21 #define QIXIS_LBMAP_BRDCFG_REG 0x00
  22 #endif
  23
  24 #ifndef QIXIS_RCFG_CTL_RECONFIG_IDLE
  25 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  26 #endif
  27 #ifndef QIXIS_RCFG_CTL_RECONFIG_START
  28 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  29 #endif
  30
  31 #ifdef CONFIG_SYS_I2C_FPGA_ADDR
  32 u8 qixis_read_i2c(unsigned int reg)
  33 {
  34         return i2c_reg_read(CONFIG_SYS_I2C_FPGA_ADDR, reg);
  35 }
  36
  37 void qixis_write_i2c(unsigned int reg, u8 value)
  38 {
  39         u8 val = value;
  40         i2c_reg_write(CONFIG_SYS_I2C_FPGA_ADDR, reg, val);
  41 }
  42 #endif
  43
  44 #ifdef QIXIS_BASE
  45 u8 qixis_read(unsigned int reg)
  46 {
  47         void *p = (void *)QIXIS_BASE;
  48
  49         return in_8(p + reg);
  50 }
  51
  52 void qixis_write(unsigned int reg, u8 value)
  53 {
  54         void *p = (void *)QIXIS_BASE;
  55
  56         out_8(p + reg, value);
  57 }
  58 #endif
  59
  60 u16 qixis_read_minor(void)
  61 {
  62         u16 minor;
  63
  64         /* this data is in little endian */
  65         QIXIS_WRITE(tagdata, 5);
  66         minor = QIXIS_READ(tagdata);
  67         QIXIS_WRITE(tagdata, 6);
  68         minor += QIXIS_READ(tagdata) << 8;
  69
  70         return minor;
  71 }
  72
  73 char *qixis_read_time(char *result)
  74 {
  75         time_t time = 0;
  76         int i;
  77
  78         /* timestamp is in 32-bit big endian */
  79         for (i = 8; i <= 11; i++) {
  80                 QIXIS_WRITE(tagdata, i);
  81                 time =  (time << 8) + QIXIS_READ(tagdata);
  82         }
  83
  84         return ctime_r(&time, result);
  85 }
  86
  87 char *qixis_read_tag(char *buf)
  88 {
  89         int i;
  90         char tag, *ptr = buf;
  91
  92         for (i = 16; i <= 63; i++) {
  93                 QIXIS_WRITE(tagdata, i);
  94                 tag = QIXIS_READ(tagdata);
  95                 *(ptr++) = tag;
  96                 if (!tag)
  97                         break;
  98         }
  99         if (i > 63)
 100                 *ptr = '\0';
 101
 102         return buf;
 103 }
 104
 105 /*
 106  * return the string of binary of u8 in the format of
 107  * 1010 10_0. The masked bit is filled as underscore.
 108  */
 109 const char *byte_to_binary_mask(u8 val, u8 mask, char *buf)
 110 {
 111         char *ptr;
 112         int i;
 113
 114         ptr = buf;
 115         for (i = 0x80; i > 0x08 ; i >>= 1, ptr++)
 116                 *ptr = (val & i) ? '1' : ((mask & i) ? '_' : '0');
 117         *(ptr++) = ' ';
 118         for (i = 0x08; i > 0 ; i >>= 1, ptr++)
 119                 *ptr = (val & i) ? '1' : ((mask & i) ? '_' : '0');
 120
 121         *ptr = '\0';
 122
 123         return buf;
 124 }
 125
 126 #ifdef QIXIS_RST_FORCE_MEM
 127 void board_assert_mem_reset(void)
 128 {
 129         u8 rst;
 130
 131         rst = QIXIS_READ(rst_frc[0]);
 132         if (!(rst & QIXIS_RST_FORCE_MEM))
 133                 QIXIS_WRITE(rst_frc[0], rst | QIXIS_RST_FORCE_MEM);
 134 }
 135
 136 void board_deassert_mem_reset(void)
 137 {
 138         u8 rst;
 139
 140         rst = QIXIS_READ(rst_frc[0]);
 141         if (rst & QIXIS_RST_FORCE_MEM)
 142                 QIXIS_WRITE(rst_frc[0], rst & ~QIXIS_RST_FORCE_MEM);
 143 }
 144 #endif
 145
 146 #ifndef CONFIG_SPL_BUILD
 147 static void qixis_reset(void)
 148 {
 149         QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET);
 150 }
 151
 152 #ifdef QIXIS_LBMAP_ALTBANK
 153 static void qixis_bank_reset(void)
 154 {
 155         QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
 156         QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
 157 }
 158 #endif
 159
 160 static void __maybe_unused set_lbmap(int lbmap)
 161 {
 162         u8 reg;
 163
 164         reg = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
 165         reg = (reg & ~QIXIS_LBMAP_MASK) | lbmap;
 166         QIXIS_WRITE(brdcfg[QIXIS_LBMAP_BRDCFG_REG], reg);
 167 }
 168
 169 static void __maybe_unused set_rcw_src(int rcw_src)
 170 {
 171 #ifdef CONFIG_NXP_LSCH3_2
 172         QIXIS_WRITE(dutcfg[0], (rcw_src & 0xff));
 173 #else
 174         u8 reg;
 175
 176         reg = QIXIS_READ(dutcfg[1]);
 177         reg = (reg & ~1) | (rcw_src & 1);
 178         QIXIS_WRITE(dutcfg[1], reg);
 179         QIXIS_WRITE(dutcfg[0], (rcw_src >> 1) & 0xff);
 180 #endif
 181 }
 182
 183 static void qixis_dump_regs(void)
 184 {
 185         int i;
 186
 187         printf("id      = %02x\n", QIXIS_READ(id));
 188         printf("arch    = %02x\n", QIXIS_READ(arch));
 189         printf("scver   = %02x\n", QIXIS_READ(scver));
 190         printf("model   = %02x\n", QIXIS_READ(model));
 191         printf("rst_ctl = %02x\n", QIXIS_READ(rst_ctl));
 192         printf("aux     = %02x\n", QIXIS_READ(aux));
 193         for (i = 0; i < 16; i++)
 194                 printf("brdcfg%02d = %02x\n", i, QIXIS_READ(brdcfg[i]));
 195         for (i = 0; i < 16; i++)
 196                 printf("dutcfg%02d = %02x\n", i, QIXIS_READ(dutcfg[i]));
 197         printf("sclk    = %02x%02x%02x\n", QIXIS_READ(sclk[0]),
 198                 QIXIS_READ(sclk[1]), QIXIS_READ(sclk[2]));
 199         printf("dclk    = %02x%02x%02x\n", QIXIS_READ(dclk[0]),
 200                 QIXIS_READ(dclk[1]), QIXIS_READ(dclk[2]));
 201         printf("aux     = %02x\n", QIXIS_READ(aux));
 202         printf("watch   = %02x\n", QIXIS_READ(watch));
 203         printf("ctl_sys = %02x\n", QIXIS_READ(ctl_sys));
 204         printf("rcw_ctl = %02x\n", QIXIS_READ(rcw_ctl));
 205         printf("present = %02x\n", QIXIS_READ(present));
 206         printf("present2 = %02x\n", QIXIS_READ(present2));
 207         printf("clk_spd = %02x\n", QIXIS_READ(clk_spd));
 208         printf("stat_dut = %02x\n", QIXIS_READ(stat_dut));
 209         printf("stat_sys = %02x\n", QIXIS_READ(stat_sys));
 210         printf("stat_alrm = %02x\n", QIXIS_READ(stat_alrm));
 211 }
 212
 213 void __weak qixis_dump_switch(void)
 214 {
 215         puts("Reverse engineering switch is not implemented for this board\n");
 216 }
 217
 218 static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 219 {
 220         int i;
 221
 222         if (argc <= 1) {
 223                 set_lbmap(QIXIS_LBMAP_DFLTBANK);
 224                 qixis_reset();
 225         } else if (strcmp(argv[1], "altbank") == 0) {
 226 #ifdef QIXIS_LBMAP_ALTBANK
 227                 set_lbmap(QIXIS_LBMAP_ALTBANK);
 228                 qixis_bank_reset();
 229 #else
 230                 printf("No Altbank!\n");
 231 #endif
 232         } else if (strcmp(argv[1], "nand") == 0) {
 233 #ifdef QIXIS_LBMAP_NAND
 234                 QIXIS_WRITE(rst_ctl, 0x30);
 235                 QIXIS_WRITE(rcfg_ctl, 0);
 236                 set_lbmap(QIXIS_LBMAP_NAND);
 237                 set_rcw_src(QIXIS_RCW_SRC_NAND);
 238                 QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
 239                 QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
 240 #else
 241                 printf("Not implemented\n");
 242 #endif
 243         } else if (strcmp(argv[1], "sd") == 0) {
 244 #ifdef QIXIS_LBMAP_SD
 245                 QIXIS_WRITE(rst_ctl, 0x30);
 246                 QIXIS_WRITE(rcfg_ctl, 0);
 247 #ifdef NON_EXTENDED_DUTCFG
 248                 QIXIS_WRITE(dutcfg[0], QIXIS_RCW_SRC_SD);
 249 #else
 250                 set_lbmap(QIXIS_LBMAP_SD);
 251                 set_rcw_src(QIXIS_RCW_SRC_SD);
 252 #endif
 253                 QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
 254                 QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
 255 #else
 256                 printf("Not implemented\n");
 257 #endif
 258         } else if (strcmp(argv[1], "ifc") == 0) {
 259 #ifdef QIXIS_LBMAP_IFC
 260                 QIXIS_WRITE(rst_ctl, 0x30);
 261                 QIXIS_WRITE(rcfg_ctl, 0);
 262                 set_lbmap(QIXIS_LBMAP_IFC);
 263                 set_rcw_src(QIXIS_RCW_SRC_IFC);
 264                 QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
 265                 QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
 266 #else
 267                 printf("Not implemented\n");
 268 #endif
 269         } else if (strcmp(argv[1], "emmc") == 0) {
 270 #ifdef QIXIS_LBMAP_EMMC
 271                 QIXIS_WRITE(rst_ctl, 0x30);
 272                 QIXIS_WRITE(rcfg_ctl, 0);
 273                 set_lbmap(QIXIS_LBMAP_EMMC);
 274                 set_rcw_src(QIXIS_RCW_SRC_EMMC);
 275                 QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
 276                 QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
 277 #else
 278                 printf("Not implemented\n");
 279 #endif
 280         } else if (strcmp(argv[1], "sd_qspi") == 0) {
 281 #ifdef QIXIS_LBMAP_SD_QSPI
 282                 QIXIS_WRITE(rst_ctl, 0x30);
 283                 QIXIS_WRITE(rcfg_ctl, 0);
 284                 set_lbmap(QIXIS_LBMAP_SD_QSPI);
 285                 set_rcw_src(QIXIS_RCW_SRC_SD);
 286                 qixis_write_i2c(offsetof(struct qixis, rcfg_ctl),
 287                                 QIXIS_RCFG_CTL_RECONFIG_IDLE);
 288                 qixis_write_i2c(offsetof(struct qixis, rcfg_ctl),
 289                                 QIXIS_RCFG_CTL_RECONFIG_START);
 290 #else
 291                 printf("Not implemented\n");
 292 #endif
 293         } else if (strcmp(argv[1], "qspi") == 0) {
 294 #ifdef QIXIS_LBMAP_QSPI
 295                 QIXIS_WRITE(rst_ctl, 0x30);
 296                 QIXIS_WRITE(rcfg_ctl, 0);
 297                 set_lbmap(QIXIS_LBMAP_QSPI);
 298                 set_rcw_src(QIXIS_RCW_SRC_QSPI);
 299                 qixis_write_i2c(offsetof(struct qixis, rcfg_ctl),
 300                                 QIXIS_RCFG_CTL_RECONFIG_IDLE);
 301                 qixis_write_i2c(offsetof(struct qixis, rcfg_ctl),
 302                                 QIXIS_RCFG_CTL_RECONFIG_START);
 303 #else
 304                 printf("Not implemented\n");
 305 #endif
 306         } else if (strcmp(argv[1], "watchdog") == 0) {
 307                 static char *period[9] = {"2s", "4s", "8s", "16s", "32s",
 308                                           "1min", "2min", "4min", "8min"};
 309                 u8 rcfg = QIXIS_READ(rcfg_ctl);
 310
 311                 if (argv[2] == NULL) {
 312                         printf("qixis watchdog <watchdog_period>\n");
 313                         return 0;
 314                 }
 315                 for (i = 0; i < ARRAY_SIZE(period); i++) {
 316                         if (strcmp(argv[2], period[i]) == 0) {
 317                                 /* disable watchdog */
 318                                 QIXIS_WRITE(rcfg_ctl,
 319                                         rcfg & ~QIXIS_RCFG_CTL_WATCHDOG_ENBLE);
 320                                 QIXIS_WRITE(watch, ((i<<2) - 1));
 321                                 QIXIS_WRITE(rcfg_ctl, rcfg);
 322                                 return 0;
 323                         }
 324                 }
 325         } else if (strcmp(argv[1], "dump") == 0) {
 326                 qixis_dump_regs();
 327                 return 0;
 328         } else if (strcmp(argv[1], "switch") == 0) {
 329                 qixis_dump_switch();
 330                 return 0;
 331         } else {
 332                 printf("Invalid option: %s\n", argv[1]);
 333                 return 1;
 334         }
 335
 336         return 0;
 337 }
 338
 339 U_BOOT_CMD(
 340         qixis_reset, CONFIG_SYS_MAXARGS, 1, qixis_reset_cmd,
 341         "Reset the board using the FPGA sequencer",
 342         "- hard reset to default bank\n"
 343         "qixis_reset altbank - reset to alternate bank\n"
 344         "qixis_reset nand - reset to nand\n"
 345         "qixis_reset sd - reset to sd\n"
 346         "qixis_reset sd_qspi - reset to sd with qspi support\n"
 347         "qixis_reset qspi - reset to qspi\n"
 348         "qixis watchdog <watchdog_period> - set the watchdog period\n"
 349         "       period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n"
 350         "qixis_reset dump - display the QIXIS registers\n"
 351         "qixis_reset switch - display switch\n"
 352         );
 353 #endif