2 * Copyright 2011 Freescale Semiconductor
3 * Author: Shengzhou Liu <Shengzhou.Liu@freescale.com>
5 * SPDX-License-Identifier: GPL-2.0+
7 * This file provides support for the QIXIS of some Freescale reference boards.
13 #include <linux/time.h>
17 #ifdef CONFIG_SYS_I2C_FPGA_ADDR
18 u8
qixis_read_i2c(unsigned int reg
)
20 return i2c_reg_read(CONFIG_SYS_I2C_FPGA_ADDR
, reg
);
23 void qixis_write_i2c(unsigned int reg
, u8 value
)
26 i2c_reg_write(CONFIG_SYS_I2C_FPGA_ADDR
, reg
, val
);
30 u8
qixis_read(unsigned int reg
)
32 void *p
= (void *)QIXIS_BASE
;
37 void qixis_write(unsigned int reg
, u8 value
)
39 void *p
= (void *)QIXIS_BASE
;
41 out_8(p
+ reg
, value
);
44 u16
qixis_read_minor(void)
48 /* this data is in little endian */
49 QIXIS_WRITE(tagdata
, 5);
50 minor
= QIXIS_READ(tagdata
);
51 QIXIS_WRITE(tagdata
, 6);
52 minor
+= QIXIS_READ(tagdata
) << 8;
57 char *qixis_read_time(char *result
)
62 /* timestamp is in 32-bit big endian */
63 for (i
= 8; i
<= 11; i
++) {
64 QIXIS_WRITE(tagdata
, i
);
65 time
= (time
<< 8) + QIXIS_READ(tagdata
);
68 return ctime_r(&time
, result
);
71 char *qixis_read_tag(char *buf
)
76 for (i
= 16; i
<= 63; i
++) {
77 QIXIS_WRITE(tagdata
, i
);
78 tag
= QIXIS_READ(tagdata
);
90 * return the string of binary of u8 in the format of
91 * 1010 10_0. The masked bit is filled as underscore.
93 const char *byte_to_binary_mask(u8 val
, u8 mask
, char *buf
)
99 for (i
= 0x80; i
> 0x08 ; i
>>= 1, ptr
++)
100 *ptr
= (val
& i
) ? '1' : ((mask
& i
) ? '_' : '0');
102 for (i
= 0x08; i
> 0 ; i
>>= 1, ptr
++)
103 *ptr
= (val
& i
) ? '1' : ((mask
& i
) ? '_' : '0');
110 #ifdef QIXIS_RST_FORCE_MEM
111 void board_assert_mem_reset(void)
115 rst
= QIXIS_READ(rst_frc
[0]);
116 if (!(rst
& QIXIS_RST_FORCE_MEM
))
117 QIXIS_WRITE(rst_frc
[0], rst
| QIXIS_RST_FORCE_MEM
);
120 void board_deassert_mem_reset(void)
124 rst
= QIXIS_READ(rst_frc
[0]);
125 if (rst
& QIXIS_RST_FORCE_MEM
)
126 QIXIS_WRITE(rst_frc
[0], rst
& ~QIXIS_RST_FORCE_MEM
);
130 void qixis_reset(void)
132 QIXIS_WRITE(rst_ctl
, QIXIS_RST_CTL_RESET
);
135 void qixis_bank_reset(void)
137 QIXIS_WRITE(rcfg_ctl
, QIXIS_RCFG_CTL_RECONFIG_IDLE
);
138 QIXIS_WRITE(rcfg_ctl
, QIXIS_RCFG_CTL_RECONFIG_START
);
141 static void __maybe_unused
set_lbmap(int lbmap
)
145 reg
= QIXIS_READ(brdcfg
[0]);
146 reg
= (reg
& ~QIXIS_LBMAP_MASK
) | lbmap
;
147 QIXIS_WRITE(brdcfg
[0], reg
);
150 static void __maybe_unused
set_rcw_src(int rcw_src
)
154 reg
= QIXIS_READ(dutcfg
[1]);
155 reg
= (reg
& ~1) | (rcw_src
& 1);
156 QIXIS_WRITE(dutcfg
[1], reg
);
157 QIXIS_WRITE(dutcfg
[0], (rcw_src
>> 1) & 0xff);
160 static void qixis_dump_regs(void)
164 printf("id = %02x\n", QIXIS_READ(id
));
165 printf("arch = %02x\n", QIXIS_READ(arch
));
166 printf("scver = %02x\n", QIXIS_READ(scver
));
167 printf("model = %02x\n", QIXIS_READ(model
));
168 printf("rst_ctl = %02x\n", QIXIS_READ(rst_ctl
));
169 printf("aux = %02x\n", QIXIS_READ(aux
));
170 for (i
= 0; i
< 16; i
++)
171 printf("brdcfg%02d = %02x\n", i
, QIXIS_READ(brdcfg
[i
]));
172 for (i
= 0; i
< 16; i
++)
173 printf("dutcfg%02d = %02x\n", i
, QIXIS_READ(dutcfg
[i
]));
174 printf("sclk = %02x%02x%02x\n", QIXIS_READ(sclk
[0]),
175 QIXIS_READ(sclk
[1]), QIXIS_READ(sclk
[2]));
176 printf("dclk = %02x%02x%02x\n", QIXIS_READ(dclk
[0]),
177 QIXIS_READ(dclk
[1]), QIXIS_READ(dclk
[2]));
178 printf("aux = %02x\n", QIXIS_READ(aux
));
179 printf("watch = %02x\n", QIXIS_READ(watch
));
180 printf("ctl_sys = %02x\n", QIXIS_READ(ctl_sys
));
181 printf("rcw_ctl = %02x\n", QIXIS_READ(rcw_ctl
));
182 printf("present = %02x\n", QIXIS_READ(present
));
183 printf("present2 = %02x\n", QIXIS_READ(present2
));
184 printf("clk_spd = %02x\n", QIXIS_READ(clk_spd
));
185 printf("stat_dut = %02x\n", QIXIS_READ(stat_dut
));
186 printf("stat_sys = %02x\n", QIXIS_READ(stat_sys
));
187 printf("stat_alrm = %02x\n", QIXIS_READ(stat_alrm
));
190 static void __qixis_dump_switch(void)
192 puts("Reverse engineering switch is not implemented for this board\n");
195 void qixis_dump_switch(void)
196 __attribute__((weak
, alias("__qixis_dump_switch")));
198 int qixis_reset_cmd(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char * const argv
[])
203 set_lbmap(QIXIS_LBMAP_DFLTBANK
);
205 } else if (strcmp(argv
[1], "altbank") == 0) {
206 set_lbmap(QIXIS_LBMAP_ALTBANK
);
208 } else if (strcmp(argv
[1], "nand") == 0) {
209 #ifdef QIXIS_LBMAP_NAND
210 QIXIS_WRITE(rst_ctl
, 0x30);
211 QIXIS_WRITE(rcfg_ctl
, 0);
212 set_lbmap(QIXIS_LBMAP_NAND
);
213 set_rcw_src(QIXIS_RCW_SRC_NAND
);
214 QIXIS_WRITE(rcfg_ctl
, 0x20);
215 QIXIS_WRITE(rcfg_ctl
, 0x21);
217 printf("Not implemented\n");
219 } else if (strcmp(argv
[1], "sd") == 0) {
220 #ifdef QIXIS_LBMAP_SD
221 QIXIS_WRITE(rst_ctl
, 0x30);
222 QIXIS_WRITE(rcfg_ctl
, 0);
223 set_lbmap(QIXIS_LBMAP_SD
);
224 set_rcw_src(QIXIS_RCW_SRC_SD
);
225 QIXIS_WRITE(rcfg_ctl
, 0x20);
226 QIXIS_WRITE(rcfg_ctl
, 0x21);
228 printf("Not implemented\n");
230 } else if (strcmp(argv
[1], "sd_qspi") == 0) {
231 #ifdef QIXIS_LBMAP_SD_QSPI
232 QIXIS_WRITE(rst_ctl
, 0x30);
233 QIXIS_WRITE(rcfg_ctl
, 0);
234 set_lbmap(QIXIS_LBMAP_SD_QSPI
);
235 set_rcw_src(QIXIS_RCW_SRC_SD
);
236 qixis_write_i2c(offsetof(struct qixis
, rcfg_ctl
), 0x20);
237 qixis_write_i2c(offsetof(struct qixis
, rcfg_ctl
), 0x21);
239 printf("Not implemented\n");
241 } else if (strcmp(argv
[1], "qspi") == 0) {
242 #ifdef QIXIS_LBMAP_QSPI
243 QIXIS_WRITE(rst_ctl
, 0x30);
244 QIXIS_WRITE(rcfg_ctl
, 0);
245 set_lbmap(QIXIS_LBMAP_QSPI
);
246 set_rcw_src(QIXIS_RCW_SRC_QSPI
);
247 qixis_write_i2c(offsetof(struct qixis
, rcfg_ctl
), 0x20);
248 qixis_write_i2c(offsetof(struct qixis
, rcfg_ctl
), 0x21);
250 printf("Not implemented\n");
252 } else if (strcmp(argv
[1], "watchdog") == 0) {
253 static char *period
[9] = {"2s", "4s", "8s", "16s", "32s",
254 "1min", "2min", "4min", "8min"};
255 u8 rcfg
= QIXIS_READ(rcfg_ctl
);
257 if (argv
[2] == NULL
) {
258 printf("qixis watchdog <watchdog_period>\n");
261 for (i
= 0; i
< ARRAY_SIZE(period
); i
++) {
262 if (strcmp(argv
[2], period
[i
]) == 0) {
263 /* disable watchdog */
264 QIXIS_WRITE(rcfg_ctl
,
265 rcfg
& ~QIXIS_RCFG_CTL_WATCHDOG_ENBLE
);
266 QIXIS_WRITE(watch
, ((i
<<2) - 1));
267 QIXIS_WRITE(rcfg_ctl
, rcfg
);
271 } else if (strcmp(argv
[1], "dump") == 0) {
274 } else if (strcmp(argv
[1], "switch") == 0) {
278 printf("Invalid option: %s\n", argv
[1]);
286 qixis_reset
, CONFIG_SYS_MAXARGS
, 1, qixis_reset_cmd
,
287 "Reset the board using the FPGA sequencer",
288 "- hard reset to default bank\n"
289 "qixis_reset altbank - reset to alternate bank\n"
290 "qixis_reset nand - reset to nand\n"
291 "qixis_reset sd - reset to sd\n"
292 "qixis_reset sd_qspi - reset to sd with qspi support\n"
293 "qixis_reset qspi - reset to qspi\n"
294 "qixis watchdog <watchdog_period> - set the watchdog period\n"
295 " period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n"
296 "qixis_reset dump - display the QIXIS registers\n"
297 "qixis_reset switch - display switch\n"