1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2017-2018 NXP
15 #include <fdt_support.h>
16 #include <linux/libfdt.h>
17 #include <fsl-mc/fsl_mc.h>
18 #include <env_internal.h>
19 #include <asm/arch-fsl-layerscape/soc.h>
20 #include <asm/arch/ppa.h>
22 #include <asm/arch/fsl_serdes.h>
23 #include <asm/arch/soc.h>
25 #include "../common/qixis.h"
26 #include "ls1088a_qixis.h"
27 #include "../common/vid.h"
28 #include <fsl_immap.h>
30 DECLARE_GLOBAL_DATA_PTR
;
32 #ifdef CONFIG_TARGET_LS1088AQDS
34 struct ifc_regs ifc_cfg_ifc_nor_boot
[CONFIG_SYS_FSL_IFC_BANK_COUNT
] = {
37 CONFIG_SYS_NOR0_CSPR_EARLY
,
38 CONFIG_SYS_NOR0_CSPR_EXT
,
53 CONFIG_SYS_NOR1_CSPR_EARLY
,
54 CONFIG_SYS_NOR0_CSPR_EXT
,
55 CONFIG_SYS_NOR_AMASK_EARLY
,
70 CONFIG_SYS_NAND_CSPR_EXT
,
71 CONFIG_SYS_NAND_AMASK
,
74 CONFIG_SYS_NAND_FTIM0
,
75 CONFIG_SYS_NAND_FTIM1
,
76 CONFIG_SYS_NAND_FTIM2
,
83 CONFIG_SYS_FPGA_CSPR_EXT
,
98 struct ifc_regs ifc_cfg_qspi_nor_boot
[CONFIG_SYS_FSL_IFC_BANK_COUNT
] = {
101 CONFIG_SYS_NAND_CSPR
,
102 CONFIG_SYS_NAND_CSPR_EXT
,
103 CONFIG_SYS_NAND_AMASK
,
104 CONFIG_SYS_NAND_CSOR
,
106 CONFIG_SYS_NAND_FTIM0
,
107 CONFIG_SYS_NAND_FTIM1
,
108 CONFIG_SYS_NAND_FTIM2
,
109 CONFIG_SYS_NAND_FTIM3
117 CONFIG_SYS_FPGA_CSPR
,
118 CONFIG_SYS_FPGA_CSPR_EXT
,
120 CONFIG_SYS_FPGA_CSOR
,
133 void ifc_cfg_boot_info(struct ifc_regs_info
*regs_info
)
135 enum boot_src src
= get_boot_src();
137 if (src
== BOOT_SOURCE_QSPI_NOR
)
138 regs_info
->regs
= ifc_cfg_qspi_nor_boot
;
140 regs_info
->regs
= ifc_cfg_ifc_nor_boot
;
142 regs_info
->cs_size
= CONFIG_SYS_FSL_IFC_BANK_COUNT
;
144 #endif /* CONFIG_TFABOOT */
145 #endif /* CONFIG_TARGET_LS1088AQDS */
147 int board_early_init_f(void)
149 #if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_TARGET_LS1088AQDS)
152 fsl_lsch3_early_init_f();
156 #ifdef CONFIG_FSL_QIXIS
157 unsigned long long get_qixis_addr(void)
159 unsigned long long addr
;
161 if (gd
->flags
& GD_FLG_RELOC
)
162 addr
= QIXIS_BASE_PHYS
;
164 addr
= QIXIS_BASE_PHYS_EARLY
;
167 * IFC address under 256MB is mapped to 0x30000000, any address above
168 * is mapped to 0x5_10000000 up to 4GB.
170 addr
= addr
> 0x10000000 ? addr
+ 0x500000000ULL
: addr
+ 0x30000000;
176 #if defined(CONFIG_VID)
177 int init_func_vid(void)
179 if (adjust_vdd(0) < 0)
180 printf("core voltage not adjusted\n");
186 int is_pb_board(void)
190 board_id
= QIXIS_READ(id
);
191 if (board_id
== LS1088ARDB_PB_BOARD
)
197 int fixup_ls1088ardb_pb_banner(void *fdt
)
199 fdt_setprop_string(fdt
, 0, "model", "LS1088ARDB-PB Board");
204 #if !defined(CONFIG_SPL_BUILD)
207 #ifdef CONFIG_TFABOOT
208 enum boot_src src
= get_boot_src();
212 static const char *const freq
[] = {"100", "125", "156.25",
213 "100 separate SSCG"};
216 #ifdef CONFIG_TARGET_LS1088AQDS
217 printf("Board: LS1088A-QDS, ");
220 printf("Board: LS1088ARDB-PB, ");
222 printf("Board: LS1088A-RDB, ");
225 sw
= QIXIS_READ(arch
);
226 printf("Board Arch: V%d, ", sw
>> 4);
228 #ifdef CONFIG_TARGET_LS1088AQDS
229 printf("Board version: %c, boot from ", (sw
& 0xf) + 'A' - 1);
231 printf("Board version: %c, boot from ", (sw
& 0xf) + 'A');
234 memset((u8
*)buf
, 0x00, ARRAY_SIZE(buf
));
236 sw
= QIXIS_READ(brdcfg
[0]);
237 sw
= (sw
& QIXIS_LBMAP_MASK
) >> QIXIS_LBMAP_SHIFT
;
239 #ifdef CONFIG_TFABOOT
240 if (src
== BOOT_SOURCE_SD_MMC
)
243 #ifdef CONFIG_SD_BOOT
246 #endif /* CONFIG_TFABOOT */
248 #ifdef CONFIG_TARGET_LS1088AQDS
257 printf("vBank: %d\n", sw
);
270 sw
= QIXIS_READ(brdcfg
[0]);
271 sw
= (sw
& QIXIS_QMAP_MASK
) >> QIXIS_QMAP_SHIFT
;
272 if (sw
== 0 || sw
== 4)
281 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH
);
285 #ifdef CONFIG_TARGET_LS1088AQDS
286 printf("FPGA: v%d (%s), build %d",
287 (int)QIXIS_READ(scver
), qixis_read_tag(buf
),
288 (int)qixis_read_minor());
289 /* the timestamp string contains "\n" at the end */
290 printf(" on %s", qixis_read_time(buf
));
292 printf("CPLD: v%d.%d\n", QIXIS_READ(scver
), QIXIS_READ(tagdata
));
296 * Display the actual SERDES reference clocks as configured by the
297 * dip switches on the board. Note that the SWx registers could
298 * technically be set to force the reference clocks to match the
299 * values that the SERDES expects (or vice versa). For now, however,
300 * we just display both values and hope the user notices when they
303 puts("SERDES1 Reference : ");
304 sw
= QIXIS_READ(brdcfg
[2]);
305 clock
= (sw
>> 6) & 3;
306 printf("Clock1 = %sMHz ", freq
[clock
]);
307 clock
= (sw
>> 4) & 3;
308 printf("Clock2 = %sMHz", freq
[clock
]);
310 puts("\nSERDES2 Reference : ");
311 clock
= (sw
>> 2) & 3;
312 printf("Clock1 = %sMHz ", freq
[clock
]);
313 clock
= (sw
>> 0) & 3;
314 printf("Clock2 = %sMHz\n", freq
[clock
]);
320 bool if_board_diff_clk(void)
322 #ifdef CONFIG_TARGET_LS1088AQDS
323 u8 diff_conf
= QIXIS_READ(brdcfg
[11]);
324 return diff_conf
& 0x40;
326 u8 diff_conf
= QIXIS_READ(dutcfg
[11]);
327 return diff_conf
& 0x80;
331 unsigned long get_board_sys_clk(void)
333 u8 sysclk_conf
= QIXIS_READ(brdcfg
[1]);
335 switch (sysclk_conf
& 0x0f) {
336 case QIXIS_SYSCLK_83
:
338 case QIXIS_SYSCLK_100
:
340 case QIXIS_SYSCLK_125
:
342 case QIXIS_SYSCLK_133
:
344 case QIXIS_SYSCLK_150
:
346 case QIXIS_SYSCLK_160
:
348 case QIXIS_SYSCLK_166
:
355 unsigned long get_board_ddr_clk(void)
357 u8 ddrclk_conf
= QIXIS_READ(brdcfg
[1]);
359 if (if_board_diff_clk())
360 return get_board_sys_clk();
361 switch ((ddrclk_conf
& 0x30) >> 4) {
362 case QIXIS_DDRCLK_100
:
364 case QIXIS_DDRCLK_125
:
366 case QIXIS_DDRCLK_133
:
373 int select_i2c_ch_pca9547(u8 ch
)
377 #ifndef CONFIG_DM_I2C
378 ret
= i2c_write(I2C_MUX_PCA_ADDR_PRI
, 0, 1, &ch
, 1);
382 ret
= i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI
, 1, &dev
);
384 ret
= dm_i2c_write(dev
, 0, &ch
, 1);
387 puts("PCA: failed to select proper channel\n");
394 #if !defined(CONFIG_SPL_BUILD)
395 void board_retimer_init(void)
399 /* Retimer is connected to I2C1_CH5 */
400 select_i2c_ch_pca9547(I2C_MUX_CH5
);
402 /* Access to Control/Shared register */
404 #ifndef CONFIG_DM_I2C
405 i2c_write(I2C_RETIMER_ADDR
, 0xff, 1, ®
, 1);
409 i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR
, 1, &dev
);
410 dm_i2c_write(dev
, 0xff, ®
, 1);
413 /* Read device revision and ID */
414 #ifndef CONFIG_DM_I2C
415 i2c_read(I2C_RETIMER_ADDR
, 1, 1, ®
, 1);
417 dm_i2c_read(dev
, 1, ®
, 1);
419 debug("Retimer version id = 0x%x\n", reg
);
421 /* Enable Broadcast. All writes target all channel register sets */
423 #ifndef CONFIG_DM_I2C
424 i2c_write(I2C_RETIMER_ADDR
, 0xff, 1, ®
, 1);
426 dm_i2c_write(dev
, 0xff, ®
, 1);
429 /* Reset Channel Registers */
430 #ifndef CONFIG_DM_I2C
431 i2c_read(I2C_RETIMER_ADDR
, 0, 1, ®
, 1);
433 dm_i2c_read(dev
, 0, ®
, 1);
436 #ifndef CONFIG_DM_I2C
437 i2c_write(I2C_RETIMER_ADDR
, 0, 1, ®
, 1);
439 dm_i2c_write(dev
, 0, ®
, 1);
442 /* Set data rate as 10.3125 Gbps */
444 #ifndef CONFIG_DM_I2C
445 i2c_write(I2C_RETIMER_ADDR
, 0x60, 1, ®
, 1);
447 dm_i2c_write(dev
, 0x60, ®
, 1);
450 #ifndef CONFIG_DM_I2C
451 i2c_write(I2C_RETIMER_ADDR
, 0x61, 1, ®
, 1);
453 dm_i2c_write(dev
, 0x61, ®
, 1);
456 #ifndef CONFIG_DM_I2C
457 i2c_write(I2C_RETIMER_ADDR
, 0x62, 1, ®
, 1);
459 dm_i2c_write(dev
, 0x62, ®
, 1);
462 #ifndef CONFIG_DM_I2C
463 i2c_write(I2C_RETIMER_ADDR
, 0x63, 1, ®
, 1);
465 dm_i2c_write(dev
, 0x63, ®
, 1);
468 #ifndef CONFIG_DM_I2C
469 i2c_write(I2C_RETIMER_ADDR
, 0x64, 1, ®
, 1);
471 dm_i2c_write(dev
, 0x64, ®
, 1);
474 /* Select VCO Divider to full rate (000) */
475 #ifndef CONFIG_DM_I2C
476 i2c_read(I2C_RETIMER_ADDR
, 0x2F, 1, ®
, 1);
478 dm_i2c_read(dev
, 0x2F, ®
, 1);
482 #ifndef CONFIG_DM_I2C
483 i2c_write(I2C_RETIMER_ADDR
, 0x2F, 1, ®
, 1);
485 dm_i2c_write(dev
, 0x2F, ®
, 1);
488 #ifdef CONFIG_TARGET_LS1088AQDS
489 /* Retimer is connected to I2C1_CH5 */
490 select_i2c_ch_pca9547(I2C_MUX_CH5
);
492 /* Access to Control/Shared register */
494 #ifndef CONFIG_DM_I2C
495 i2c_write(I2C_RETIMER_ADDR2
, 0xff, 1, ®
, 1);
497 i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR2
, 1, &dev
);
498 dm_i2c_write(dev
, 0xff, ®
, 1);
501 /* Read device revision and ID */
502 #ifndef CONFIG_DM_I2C
503 i2c_read(I2C_RETIMER_ADDR2
, 1, 1, ®
, 1);
505 dm_i2c_read(dev
, 1, ®
, 1);
507 debug("Retimer version id = 0x%x\n", reg
);
509 /* Enable Broadcast. All writes target all channel register sets */
511 #ifndef CONFIG_DM_I2C
512 i2c_write(I2C_RETIMER_ADDR2
, 0xff, 1, ®
, 1);
514 dm_i2c_write(dev
, 0xff, ®
, 1);
517 /* Reset Channel Registers */
518 #ifndef CONFIG_DM_I2C
519 i2c_read(I2C_RETIMER_ADDR2
, 0, 1, ®
, 1);
521 dm_i2c_read(dev
, 0, ®
, 1);
524 #ifndef CONFIG_DM_I2C
525 i2c_write(I2C_RETIMER_ADDR2
, 0, 1, ®
, 1);
527 dm_i2c_write(dev
, 0, ®
, 1);
530 /* Set data rate as 10.3125 Gbps */
532 #ifndef CONFIG_DM_I2C
533 i2c_write(I2C_RETIMER_ADDR2
, 0x60, 1, ®
, 1);
535 dm_i2c_write(dev
, 0x60, ®
, 1);
538 #ifndef CONFIG_DM_I2C
539 i2c_write(I2C_RETIMER_ADDR2
, 0x61, 1, ®
, 1);
541 dm_i2c_write(dev
, 0x61, ®
, 1);
544 #ifndef CONFIG_DM_I2C
545 i2c_write(I2C_RETIMER_ADDR2
, 0x62, 1, ®
, 1);
547 dm_i2c_write(dev
, 0x62, ®
, 1);
550 #ifndef CONFIG_DM_I2C
551 i2c_write(I2C_RETIMER_ADDR2
, 0x63, 1, ®
, 1);
553 dm_i2c_write(dev
, 0x63, ®
, 1);
556 #ifndef CONFIG_DM_I2C
557 i2c_write(I2C_RETIMER_ADDR2
, 0x64, 1, ®
, 1);
559 dm_i2c_write(dev
, 0x64, ®
, 1);
562 /* Select VCO Divider to full rate (000) */
563 #ifndef CONFIG_DM_I2C
564 i2c_read(I2C_RETIMER_ADDR2
, 0x2F, 1, ®
, 1);
566 dm_i2c_read(dev
, 0x2F, ®
, 1);
570 #ifndef CONFIG_DM_I2C
571 i2c_write(I2C_RETIMER_ADDR2
, 0x2F, 1, ®
, 1);
573 dm_i2c_write(dev
, 0x2F, ®
, 1);
577 /*return the default channel*/
578 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT
);
581 #ifdef CONFIG_MISC_INIT_R
582 int misc_init_r(void)
584 #ifdef CONFIG_TARGET_LS1088ARDB
587 if (hwconfig("esdhc-force-sd")) {
588 brdcfg5
= QIXIS_READ(brdcfg
[5]);
589 brdcfg5
&= ~BRDCFG5_SPISDHC_MASK
;
590 brdcfg5
|= BRDCFG5_FORCE_SD
;
591 QIXIS_WRITE(brdcfg
[5], brdcfg5
);
599 int i2c_multiplexer_select_vid_channel(u8 channel
)
601 return select_i2c_ch_pca9547(channel
);
604 #ifdef CONFIG_TARGET_LS1088AQDS
605 /* read the current value(SVDD) of the LTM Regulator Voltage */
606 int get_serdes_volt(void)
609 u8 chan
= PWM_CHANNEL0
;
611 /* Select the PAGE 0 using PMBus commands PAGE for VDD */
612 #ifndef CONFIG_DM_I2C
613 ret
= i2c_write(I2C_SVDD_MONITOR_ADDR
,
614 PMBUS_CMD_PAGE
, 1, &chan
, 1);
618 ret
= i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR
, 1, &dev
);
620 ret
= dm_i2c_write(dev
, PMBUS_CMD_PAGE
,
625 printf("VID: failed to select VDD Page 0\n");
629 /* Read the output voltage using PMBus command READ_VOUT */
630 #ifndef CONFIG_DM_I2C
631 ret
= i2c_read(I2C_SVDD_MONITOR_ADDR
,
632 PMBUS_CMD_READ_VOUT
, 1, (void *)&vcode
, 2);
634 dm_i2c_read(dev
, PMBUS_CMD_READ_VOUT
, (void *)&vcode
, 2);
637 printf("VID: failed to read the volatge\n");
644 int set_serdes_volt(int svdd
)
647 u8 buff
[5] = {0x04, PWM_CHANNEL0
, PMBUS_CMD_VOUT_COMMAND
,
648 svdd
& 0xFF, (svdd
& 0xFF00) >> 8};
650 /* Write the desired voltage code to the SVDD regulator */
651 #ifndef CONFIG_DM_I2C
652 ret
= i2c_write(I2C_SVDD_MONITOR_ADDR
,
653 PMBUS_CMD_PAGE_PLUS_WRITE
, 1, (void *)&buff
, 5);
657 ret
= i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR
, 1, &dev
);
659 ret
= dm_i2c_write(dev
, PMBUS_CMD_PAGE_PLUS_WRITE
,
663 printf("VID: I2C failed to write to the volatge regulator\n");
667 /* Wait for the volatge to get to the desired value */
669 vdd_last
= get_serdes_volt();
671 printf("VID: Couldn't read sensor abort VID adjust\n");
674 } while (vdd_last
!= svdd
);
679 int get_serdes_volt(void)
684 int set_serdes_volt(int svdd
)
689 printf("SVDD changing of RDB\n");
691 /* Read the BRDCFG54 via CLPD */
692 #ifndef CONFIG_DM_I2C
693 ret
= i2c_read(CONFIG_SYS_I2C_FPGA_ADDR
,
694 QIXIS_BRDCFG4_OFFSET
, 1, (void *)&brdcfg4
, 1);
698 ret
= i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR
, 1, &dev
);
700 ret
= dm_i2c_read(dev
, QIXIS_BRDCFG4_OFFSET
,
701 (void *)&brdcfg4
, 1);
705 printf("VID: I2C failed to read the CPLD BRDCFG4\n");
709 brdcfg4
= brdcfg4
| 0x08;
711 /* Write to the BRDCFG4 */
712 #ifndef CONFIG_DM_I2C
713 ret
= i2c_write(CONFIG_SYS_I2C_FPGA_ADDR
,
714 QIXIS_BRDCFG4_OFFSET
, 1, (void *)&brdcfg4
, 1);
716 ret
= dm_i2c_write(dev
, QIXIS_BRDCFG4_OFFSET
,
717 (void *)&brdcfg4
, 1);
721 debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
725 /* Wait for the volatge to get to the desired value */
732 /* this function disables the SERDES, changes the SVDD Voltage and enables it*/
733 int board_adjust_vdd(int vdd
)
737 debug("%s: vdd = %d\n", __func__
, vdd
);
739 /* Special settings to be performed when voltage is 900mV */
741 ret
= setup_serdes_volt(vdd
);
751 #if !defined(CONFIG_SPL_BUILD)
754 init_final_memctl_regs();
755 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
756 u32 __iomem
*irq_ccsr
= (u32 __iomem
*)ISC_BASE
;
759 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT
);
760 board_retimer_init();
762 #ifdef CONFIG_ENV_IS_NOWHERE
763 gd
->env_addr
= (ulong
)&default_environment
[0];
766 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
767 /* invert AQR105 IRQ pins polarity */
768 out_le32(irq_ccsr
+ IRQCR_OFFSET
/ 4, AQR105_IRQ_MASK
);
771 #ifdef CONFIG_FSL_CAAM
774 #ifdef CONFIG_FSL_LS_PPA
780 void detail_board_ddr_info(void)
783 print_size(gd
->bd
->bi_dram
[0].size
+ gd
->bd
->bi_dram
[1].size
, "");
787 #if defined(CONFIG_ARCH_MISC_INIT)
788 int arch_misc_init(void)
794 #ifdef CONFIG_FSL_MC_ENET
795 void board_quiesce_devices(void)
797 fsl_mc_ldpaa_exit(gd
->bd
);
800 void fdt_fixup_board_enet(void *fdt
)
804 offset
= fdt_path_offset(fdt
, "/fsl-mc");
807 offset
= fdt_path_offset(fdt
, "/soc/fsl-mc");
810 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
815 if (get_mc_boot_status() == 0 &&
816 (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
817 fdt_status_okay(fdt
, offset
);
819 fdt_status_fail(fdt
, offset
);
823 #ifdef CONFIG_OF_BOARD_SETUP
824 void fsl_fdt_fixup_flash(void *fdt
)
827 #ifdef CONFIG_TFABOOT
828 u32 __iomem
*dcfg_ccsr
= (u32 __iomem
*)DCFG_BASE
;
833 * IFC-NOR and QSPI are muxed on SoC.
834 * So disable IFC node in dts if QSPI is enabled or
835 * disable QSPI node in dts in case QSPI is not enabled.
838 #ifdef CONFIG_TFABOOT
839 enum boot_src src
= get_boot_src();
840 bool disable_ifc
= false;
843 case BOOT_SOURCE_IFC_NOR
:
846 case BOOT_SOURCE_QSPI_NOR
:
850 val
= in_le32(dcfg_ccsr
+ DCFG_RCWSR15
/ 4);
851 if (DCFG_RCWSR15_IFCGRPABASE_QSPI
== (val
& (u32
)0x3))
857 offset
= fdt_path_offset(fdt
, "/soc/ifc/nor");
860 offset
= fdt_path_offset(fdt
, "/ifc/nor");
862 offset
= fdt_path_offset(fdt
, "/soc/quadspi");
865 offset
= fdt_path_offset(fdt
, "/quadspi");
869 #ifdef CONFIG_FSL_QSPI
870 offset
= fdt_path_offset(fdt
, "/soc/ifc/nor");
873 offset
= fdt_path_offset(fdt
, "/ifc/nor");
875 offset
= fdt_path_offset(fdt
, "/soc/quadspi");
878 offset
= fdt_path_offset(fdt
, "/quadspi");
884 fdt_status_disabled(fdt
, offset
);
887 int ft_board_setup(void *blob
, bd_t
*bd
)
890 u16 mc_memory_bank
= 0;
894 u64 mc_memory_base
= 0;
895 u64 mc_memory_size
= 0;
896 u16 total_memory_banks
;
898 ft_cpu_setup(blob
, bd
);
900 fdt_fixup_mc_ddr(&mc_memory_base
, &mc_memory_size
);
902 if (mc_memory_base
!= 0)
905 total_memory_banks
= CONFIG_NR_DRAM_BANKS
+ mc_memory_bank
;
907 base
= calloc(total_memory_banks
, sizeof(u64
));
908 size
= calloc(total_memory_banks
, sizeof(u64
));
910 /* fixup DT for the two GPP DDR banks */
911 for (i
= 0; i
< CONFIG_NR_DRAM_BANKS
; i
++) {
912 base
[i
] = gd
->bd
->bi_dram
[i
].start
;
913 size
[i
] = gd
->bd
->bi_dram
[i
].size
;
916 #ifdef CONFIG_RESV_RAM
917 /* reduce size if reserved memory is within this bank */
918 if (gd
->arch
.resv_ram
>= base
[0] &&
919 gd
->arch
.resv_ram
< base
[0] + size
[0])
920 size
[0] = gd
->arch
.resv_ram
- base
[0];
921 else if (gd
->arch
.resv_ram
>= base
[1] &&
922 gd
->arch
.resv_ram
< base
[1] + size
[1])
923 size
[1] = gd
->arch
.resv_ram
- base
[1];
926 if (mc_memory_base
!= 0) {
927 for (i
= 0; i
<= total_memory_banks
; i
++) {
928 if (base
[i
] == 0 && size
[i
] == 0) {
929 base
[i
] = mc_memory_base
;
930 size
[i
] = mc_memory_size
;
936 fdt_fixup_memory_banks(blob
, base
, size
, total_memory_banks
);
938 fdt_fsl_mc_fixup_iommu_map_entry(blob
);
940 fsl_fdt_fixup_flash(blob
);
942 #ifdef CONFIG_FSL_MC_ENET
943 fdt_fixup_board_enet(blob
);
946 fixup_ls1088ardb_pb_banner(blob
);
951 #endif /* defined(CONFIG_SPL_BUILD) */
953 #ifdef CONFIG_TFABOOT
954 #ifdef CONFIG_MTD_NOR_FLASH
955 int is_flash_available(void)
957 char *env_hwconfig
= env_get("hwconfig");
958 enum boot_src src
= get_boot_src();
959 int is_nor_flash_available
= 1;
962 case BOOT_SOURCE_IFC_NOR
:
963 is_nor_flash_available
= 1;
965 case BOOT_SOURCE_QSPI_NOR
:
966 is_nor_flash_available
= 0;
969 * In Case of SD boot,if qspi is defined in env_hwconfig
970 * disable nor flash probe.
973 if (hwconfig_f("qspi", env_hwconfig
))
974 is_nor_flash_available
= 0;
977 return is_nor_flash_available
;
981 void *env_sf_get_env_addr(void)
983 return (void *)(CONFIG_SYS_FSL_QSPI_BASE
+ CONFIG_ENV_OFFSET
);