1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2015 Freescale Semiconductor, Inc.
10 #include <asm/arch/fsl_serdes.h>
17 #include <fsl-mc/fsl_mc.h>
18 #include <fsl-mc/ldpaa_wriop.h>
20 #include "../common/qixis.h"
22 #include "ls2080aqds_qixis.h"
24 #define MC_BOOT_ENV_VAR "mcinitcmd"
26 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
27 /* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks.
28 * Bank 1 -> Lanes A, B, C, D, E, F, G, H
29 * Bank 2 -> Lanes A,B, C, D, E, F, G, H
32 /* Mapping of 16 SERDES lanes to LS2080A QDS board slots. A value of '0' here
33 * means that the mapping must be determined dynamically, or that the lane
34 * maps to something other than a board slot.
37 static u8 lane_to_slot_fsm1
[] = {
38 0, 0, 0, 0, 0, 0, 0, 0
41 static u8 lane_to_slot_fsm2
[] = {
42 0, 0, 0, 0, 0, 0, 0, 0
45 /* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
49 static int xqsgii_riser_phy_addr
[] = {
50 XQSGMII_CARD_PHY1_PORT0_ADDR
,
51 XQSGMII_CARD_PHY2_PORT0_ADDR
,
52 XQSGMII_CARD_PHY3_PORT0_ADDR
,
53 XQSGMII_CARD_PHY4_PORT0_ADDR
,
54 XQSGMII_CARD_PHY3_PORT2_ADDR
,
55 XQSGMII_CARD_PHY1_PORT2_ADDR
,
56 XQSGMII_CARD_PHY4_PORT2_ADDR
,
57 XQSGMII_CARD_PHY2_PORT2_ADDR
,
60 static int sgmii_riser_phy_addr
[] = {
61 SGMII_CARD_PORT1_PHY_ADDR
,
62 SGMII_CARD_PORT2_PHY_ADDR
,
63 SGMII_CARD_PORT3_PHY_ADDR
,
64 SGMII_CARD_PORT4_PHY_ADDR
,
67 /* Slot2 does not have EMI connections */
78 static const char * const mdio_names
[] = {
85 DEFAULT_WRIOP_MDIO2_NAME
,
88 struct ls2080a_qds_mdio
{
90 struct mii_dev
*realbus
;
98 static void sgmii_configure_repeater(int serdes_port
)
103 int dpmac_id
= 0, dpmac
, mii_bus
= 0;
104 unsigned short value
;
105 char dev
[2][20] = {"LS2080A_QDS_MDIO0", "LS2080A_QDS_MDIO3"};
106 uint8_t i2c_addr
[] = {0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5f, 0x60};
108 uint8_t ch_a_eq
[] = {0x1, 0x2, 0x3, 0x7};
109 uint8_t ch_a_ctl2
[] = {0x81, 0x82, 0x83, 0x84};
110 uint8_t ch_b_eq
[] = {0x1, 0x2, 0x3, 0x7};
111 uint8_t ch_b_ctl2
[] = {0x81, 0x82, 0x83, 0x84};
113 u8 reg_val
[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
114 struct reg_pair reg_pair
[10] = {
115 {6, ®_val
[0]}, {4, ®_val
[1]},
116 {8, ®_val
[2]}, {0xf, NULL
},
117 {0x11, NULL
}, {0x16, NULL
},
118 {0x18, NULL
}, {0x23, ®_val
[3]},
119 {0x2d, ®_val
[4]}, {4, ®_val
[5]},
122 int *riser_phy_addr
= &xqsgii_riser_phy_addr
[0];
124 struct udevice
*udev
;
127 /* Set I2c to Slot 1 */
128 #ifndef CONFIG_DM_I2C
129 ret
= i2c_write(0x77, 0, 0, &a
, 1);
131 ret
= i2c_get_chip_for_busnum(0, 0x77, 1, &udev
);
133 ret
= dm_i2c_write(udev
, 0, &a
, 1);
138 for (dpmac
= 0; dpmac
< 8; dpmac
++) {
139 /* Check the PHY status */
140 switch (serdes_port
) {
143 dpmac_id
= dpmac
+ 1;
147 dpmac_id
= dpmac
+ 9;
149 #ifndef CONFIG_DM_I2C
150 ret
= i2c_write(0x76, 0, 0, &a
, 1);
152 ret
= i2c_get_chip_for_busnum(0, 0x76, 1, &udev
);
154 ret
= dm_i2c_write(udev
, 0, &a
, 1);
161 ret
= miiphy_set_current_dev(dev
[mii_bus
]);
165 bus
= mdio_get_current_dev();
166 debug("Reading from bus %s\n", bus
->name
);
168 ret
= miiphy_write(dev
[mii_bus
], riser_phy_addr
[dpmac
], 0x1f,
174 ret
= miiphy_read(dev
[mii_bus
], riser_phy_addr
[dpmac
], 0x11,
181 if ((value
& 0xfff) == 0x401) {
182 printf("DPMAC %d:PHY is ..... Configured\n", dpmac_id
);
183 miiphy_write(dev
[mii_bus
], riser_phy_addr
[dpmac
],
188 for (i
= 0; i
< 4; i
++) {
189 for (j
= 0; j
< 4; j
++) {
190 reg_pair
[3].val
= &ch_a_eq
[i
];
191 reg_pair
[4].val
= &ch_a_ctl2
[j
];
192 reg_pair
[5].val
= &ch_b_eq
[i
];
193 reg_pair
[6].val
= &ch_b_ctl2
[j
];
195 for (k
= 0; k
< 10; k
++) {
196 #ifndef CONFIG_DM_I2C
197 ret
= i2c_write(i2c_addr
[dpmac
],
199 1, reg_pair
[k
].val
, 1);
201 ret
= i2c_get_chip_for_busnum(0,
205 ret
= dm_i2c_write(udev
,
214 ret
= miiphy_read(dev
[mii_bus
],
215 riser_phy_addr
[dpmac
],
221 ret
= miiphy_read(dev
[mii_bus
],
222 riser_phy_addr
[dpmac
],
227 if ((value
& 0xfff) == 0x401) {
228 printf("DPMAC %d :PHY is configured ",
230 printf("after setting repeater 0x%x\n",
235 printf("DPMAC %d :PHY is failed to ",
237 printf("configure the repeater 0x%x\n",
242 miiphy_write(dev
[mii_bus
], riser_phy_addr
[dpmac
], 0x1f, 0);
246 printf("DPMAC %d ..... FAILED to configure PHY\n", dpmac_id
);
250 static void qsgmii_configure_repeater(int dpmac
)
254 int i2c_phy_addr
= 0;
256 int i2c_addr
[] = {0x58, 0x59, 0x5a, 0x5b};
258 uint8_t ch_a_eq
[] = {0x1, 0x2, 0x3, 0x7};
259 uint8_t ch_a_ctl2
[] = {0x81, 0x82, 0x83, 0x84};
260 uint8_t ch_b_eq
[] = {0x1, 0x2, 0x3, 0x7};
261 uint8_t ch_b_ctl2
[] = {0x81, 0x82, 0x83, 0x84};
263 u8 reg_val
[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
264 struct reg_pair reg_pair
[10] = {
265 {6, ®_val
[0]}, {4, ®_val
[1]},
266 {8, ®_val
[2]}, {0xf, NULL
},
267 {0x11, NULL
}, {0x16, NULL
},
268 {0x18, NULL
}, {0x23, ®_val
[3]},
269 {0x2d, ®_val
[4]}, {4, ®_val
[5]},
272 const char *dev
= "LS2080A_QDS_MDIO0";
274 unsigned short value
;
276 struct udevice
*udev
;
279 /* Set I2c to Slot 1 */
280 #ifndef CONFIG_DM_I2C
281 ret
= i2c_write(0x77, 0, 0, &a
, 1);
283 ret
= i2c_get_chip_for_busnum(0, 0x77, 1, &udev
);
285 ret
= dm_i2c_write(udev
, 0, &a
, 1);
295 i2c_phy_addr
= i2c_addr
[0];
303 i2c_phy_addr
= i2c_addr
[1];
311 i2c_phy_addr
= i2c_addr
[2];
319 i2c_phy_addr
= i2c_addr
[3];
324 /* Check the PHY status */
325 ret
= miiphy_set_current_dev(dev
);
326 ret
= miiphy_write(dev
, phy_addr
, 0x1f, 3);
328 ret
= miiphy_read(dev
, phy_addr
, 0x11, &value
);
330 ret
= miiphy_read(dev
, phy_addr
, 0x11, &value
);
332 if ((value
& 0xf) == 0xf) {
333 printf("DPMAC %d :PHY is ..... Configured\n", dpmac
);
337 for (i
= 0; i
< 4; i
++) {
338 for (j
= 0; j
< 4; j
++) {
339 reg_pair
[3].val
= &ch_a_eq
[i
];
340 reg_pair
[4].val
= &ch_a_ctl2
[j
];
341 reg_pair
[5].val
= &ch_b_eq
[i
];
342 reg_pair
[6].val
= &ch_b_ctl2
[j
];
344 for (k
= 0; k
< 10; k
++) {
345 #ifndef CONFIG_DM_I2C
346 ret
= i2c_write(i2c_phy_addr
,
348 1, reg_pair
[k
].val
, 1);
350 ret
= i2c_get_chip_for_busnum(0,
354 ret
= dm_i2c_write(udev
,
363 ret
= miiphy_read(dev
, phy_addr
, 0x11, &value
);
367 ret
= miiphy_read(dev
, phy_addr
, 0x11, &value
);
371 if ((value
& 0xf) == 0xf) {
372 printf("DPMAC %d :PHY is ..... Configured\n",
379 printf("DPMAC %d :PHY ..... FAILED to configure PHY\n", dpmac
);
383 static const char *ls2080a_qds_mdio_name_for_muxval(u8 muxval
)
385 return mdio_names
[muxval
];
388 struct mii_dev
*mii_dev_for_muxval(u8 muxval
)
391 const char *name
= ls2080a_qds_mdio_name_for_muxval(muxval
);
394 printf("No bus for muxval %x\n", muxval
);
398 bus
= miiphy_get_dev_by_name(name
);
401 printf("No bus by name %s\n", name
);
408 static void ls2080a_qds_enable_SFP_TX(u8 muxval
)
412 brdcfg9
= QIXIS_READ(brdcfg
[9]);
413 brdcfg9
&= ~BRDCFG9_SFPTX_MASK
;
414 brdcfg9
|= (muxval
<< BRDCFG9_SFPTX_SHIFT
);
415 QIXIS_WRITE(brdcfg
[9], brdcfg9
);
418 static void ls2080a_qds_mux_mdio(u8 muxval
)
423 brdcfg4
= QIXIS_READ(brdcfg
[4]);
424 brdcfg4
&= ~BRDCFG4_EMISEL_MASK
;
425 brdcfg4
|= (muxval
<< BRDCFG4_EMISEL_SHIFT
);
426 QIXIS_WRITE(brdcfg
[4], brdcfg4
);
430 static int ls2080a_qds_mdio_read(struct mii_dev
*bus
, int addr
,
431 int devad
, int regnum
)
433 struct ls2080a_qds_mdio
*priv
= bus
->priv
;
435 ls2080a_qds_mux_mdio(priv
->muxval
);
437 return priv
->realbus
->read(priv
->realbus
, addr
, devad
, regnum
);
440 static int ls2080a_qds_mdio_write(struct mii_dev
*bus
, int addr
, int devad
,
441 int regnum
, u16 value
)
443 struct ls2080a_qds_mdio
*priv
= bus
->priv
;
445 ls2080a_qds_mux_mdio(priv
->muxval
);
447 return priv
->realbus
->write(priv
->realbus
, addr
, devad
, regnum
, value
);
450 static int ls2080a_qds_mdio_reset(struct mii_dev
*bus
)
452 struct ls2080a_qds_mdio
*priv
= bus
->priv
;
454 return priv
->realbus
->reset(priv
->realbus
);
457 static int ls2080a_qds_mdio_init(char *realbusname
, u8 muxval
)
459 struct ls2080a_qds_mdio
*pmdio
;
460 struct mii_dev
*bus
= mdio_alloc();
463 printf("Failed to allocate ls2080a_qds MDIO bus\n");
467 pmdio
= malloc(sizeof(*pmdio
));
469 printf("Failed to allocate ls2080a_qds private data\n");
474 bus
->read
= ls2080a_qds_mdio_read
;
475 bus
->write
= ls2080a_qds_mdio_write
;
476 bus
->reset
= ls2080a_qds_mdio_reset
;
477 strcpy(bus
->name
, ls2080a_qds_mdio_name_for_muxval(muxval
));
479 pmdio
->realbus
= miiphy_get_dev_by_name(realbusname
);
481 if (!pmdio
->realbus
) {
482 printf("No bus with name %s\n", realbusname
);
488 pmdio
->muxval
= muxval
;
491 return mdio_register(bus
);
495 * Initialize the dpmac_info array.
498 static void initialize_dpmac_to_slot(void)
500 struct ccsr_gur __iomem
*gur
= (void *)CONFIG_SYS_FSL_GUTS_ADDR
;
501 int serdes1_prtcl
= (in_le32(&gur
->rcwsr
[28]) &
502 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK
)
503 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT
;
504 int serdes2_prtcl
= (in_le32(&gur
->rcwsr
[28]) &
505 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK
)
506 >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
;
509 env_hwconfig
= env_get("hwconfig");
511 switch (serdes1_prtcl
) {
515 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
517 lane_to_slot_fsm1
[0] = EMI1_SLOT1
;
518 lane_to_slot_fsm1
[1] = EMI1_SLOT1
;
519 lane_to_slot_fsm1
[2] = EMI1_SLOT1
;
520 lane_to_slot_fsm1
[3] = EMI1_SLOT1
;
521 if (hwconfig_f("xqsgmii", env_hwconfig
)) {
522 lane_to_slot_fsm1
[4] = EMI1_SLOT1
;
523 lane_to_slot_fsm1
[5] = EMI1_SLOT1
;
524 lane_to_slot_fsm1
[6] = EMI1_SLOT1
;
525 lane_to_slot_fsm1
[7] = EMI1_SLOT1
;
527 lane_to_slot_fsm1
[4] = EMI1_SLOT2
;
528 lane_to_slot_fsm1
[5] = EMI1_SLOT2
;
529 lane_to_slot_fsm1
[6] = EMI1_SLOT2
;
530 lane_to_slot_fsm1
[7] = EMI1_SLOT2
;
535 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
537 if (hwconfig_f("xqsgmii", env_hwconfig
)) {
538 lane_to_slot_fsm1
[0] = EMI1_SLOT3
;
539 lane_to_slot_fsm1
[1] = EMI1_SLOT3
;
540 lane_to_slot_fsm1
[2] = EMI1_SLOT3
;
541 lane_to_slot_fsm1
[3] = EMI_NONE
;
543 lane_to_slot_fsm1
[0] = EMI_NONE
;
544 lane_to_slot_fsm1
[1] = EMI_NONE
;
545 lane_to_slot_fsm1
[2] = EMI_NONE
;
546 lane_to_slot_fsm1
[3] = EMI_NONE
;
548 lane_to_slot_fsm1
[4] = EMI1_SLOT3
;
549 lane_to_slot_fsm1
[5] = EMI1_SLOT3
;
550 lane_to_slot_fsm1
[6] = EMI1_SLOT3
;
551 lane_to_slot_fsm1
[7] = EMI_NONE
;
555 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
557 if (hwconfig_f("xqsgmii", env_hwconfig
)) {
558 lane_to_slot_fsm1
[0] = EMI1_SLOT3
;
559 lane_to_slot_fsm1
[1] = EMI1_SLOT3
;
560 lane_to_slot_fsm1
[2] = EMI_NONE
;
561 lane_to_slot_fsm1
[3] = EMI_NONE
;
563 lane_to_slot_fsm1
[0] = EMI_NONE
;
564 lane_to_slot_fsm1
[1] = EMI_NONE
;
565 lane_to_slot_fsm1
[2] = EMI_NONE
;
566 lane_to_slot_fsm1
[3] = EMI_NONE
;
568 lane_to_slot_fsm1
[4] = EMI1_SLOT3
;
569 lane_to_slot_fsm1
[5] = EMI1_SLOT3
;
570 lane_to_slot_fsm1
[6] = EMI_NONE
;
571 lane_to_slot_fsm1
[7] = EMI_NONE
;
577 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
581 printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
582 __func__
, serdes1_prtcl
);
586 switch (serdes2_prtcl
) {
591 printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
593 lane_to_slot_fsm2
[0] = EMI1_SLOT4
;
594 lane_to_slot_fsm2
[1] = EMI1_SLOT4
;
595 lane_to_slot_fsm2
[2] = EMI1_SLOT4
;
596 lane_to_slot_fsm2
[3] = EMI1_SLOT4
;
598 if (hwconfig_f("xqsgmii", env_hwconfig
)) {
599 lane_to_slot_fsm2
[4] = EMI1_SLOT4
;
600 lane_to_slot_fsm2
[5] = EMI1_SLOT4
;
601 lane_to_slot_fsm2
[6] = EMI1_SLOT4
;
602 lane_to_slot_fsm2
[7] = EMI1_SLOT4
;
604 /* No MDIO physical connection */
605 lane_to_slot_fsm2
[4] = EMI1_SLOT6
;
606 lane_to_slot_fsm2
[5] = EMI1_SLOT6
;
607 lane_to_slot_fsm2
[6] = EMI1_SLOT6
;
608 lane_to_slot_fsm2
[7] = EMI1_SLOT6
;
613 printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
615 lane_to_slot_fsm2
[0] = EMI_NONE
;
616 lane_to_slot_fsm2
[1] = EMI1_SLOT5
;
617 lane_to_slot_fsm2
[2] = EMI1_SLOT5
;
618 lane_to_slot_fsm2
[3] = EMI1_SLOT5
;
620 if (hwconfig_f("xqsgmii", env_hwconfig
)) {
621 lane_to_slot_fsm2
[4] = EMI_NONE
;
622 lane_to_slot_fsm2
[5] = EMI1_SLOT5
;
623 lane_to_slot_fsm2
[6] = EMI1_SLOT5
;
624 lane_to_slot_fsm2
[7] = EMI1_SLOT5
;
629 printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
631 if (hwconfig_f("xqsgmii", env_hwconfig
)) {
632 lane_to_slot_fsm2
[0] = EMI_NONE
;
633 lane_to_slot_fsm2
[1] = EMI_NONE
;
634 lane_to_slot_fsm2
[2] = EMI_NONE
;
635 lane_to_slot_fsm2
[3] = EMI_NONE
;
637 lane_to_slot_fsm2
[4] = EMI_NONE
;
638 lane_to_slot_fsm2
[5] = EMI_NONE
;
639 lane_to_slot_fsm2
[6] = EMI1_SLOT5
;
640 lane_to_slot_fsm2
[7] = EMI1_SLOT5
;
644 printf(" %s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
645 __func__
, serdes2_prtcl
);
650 void ls2080a_handle_phy_interface_sgmii(int dpmac_id
)
654 struct ccsr_gur __iomem
*gur
= (void *)CONFIG_SYS_FSL_GUTS_ADDR
;
655 int serdes1_prtcl
= (in_le32(&gur
->rcwsr
[28]) &
656 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK
)
657 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT
;
658 int serdes2_prtcl
= (in_le32(&gur
->rcwsr
[28]) &
659 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK
)
660 >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
;
663 char *env_hwconfig
= env_get("hwconfig");
665 if (hwconfig_f("xqsgmii", env_hwconfig
))
666 riser_phy_addr
= &xqsgii_riser_phy_addr
[0];
668 riser_phy_addr
= &sgmii_riser_phy_addr
[0];
670 if (dpmac_id
> WRIOP1_DPMAC9
)
673 switch (serdes1_prtcl
) {
677 lane
= serdes_get_first_lane(FSL_SRDS_1
, SGMII1
+ dpmac_id
- 1);
679 slot
= lane_to_slot_fsm1
[lane
];
683 /* Slot housing a SGMII riser card? */
684 wriop_set_phy_address(dpmac_id
, 0,
685 riser_phy_addr
[dpmac_id
- 1]);
686 dpmac_info
[dpmac_id
].board_mux
= EMI1_SLOT1
;
687 bus
= mii_dev_for_muxval(EMI1_SLOT1
);
688 wriop_set_mdio(dpmac_id
, bus
);
691 /* Slot housing a SGMII riser card? */
692 wriop_set_phy_address(dpmac_id
, 0,
693 riser_phy_addr
[dpmac_id
- 1]);
694 dpmac_info
[dpmac_id
].board_mux
= EMI1_SLOT2
;
695 bus
= mii_dev_for_muxval(EMI1_SLOT2
);
696 wriop_set_mdio(dpmac_id
, bus
);
699 if (slot
== EMI_NONE
)
701 if (serdes1_prtcl
== 0x39) {
702 wriop_set_phy_address(dpmac_id
, 0,
703 riser_phy_addr
[dpmac_id
- 2]);
704 if (dpmac_id
>= 6 && hwconfig_f("xqsgmii",
706 wriop_set_phy_address(dpmac_id
, 0,
707 riser_phy_addr
[dpmac_id
- 3]);
709 wriop_set_phy_address(dpmac_id
, 0,
710 riser_phy_addr
[dpmac_id
- 2]);
711 if (dpmac_id
>= 7 && hwconfig_f("xqsgmii",
713 wriop_set_phy_address(dpmac_id
, 0,
714 riser_phy_addr
[dpmac_id
- 3]);
716 dpmac_info
[dpmac_id
].board_mux
= EMI1_SLOT3
;
717 bus
= mii_dev_for_muxval(EMI1_SLOT3
);
718 wriop_set_mdio(dpmac_id
, bus
);
729 printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
730 __func__
, serdes1_prtcl
);
735 switch (serdes2_prtcl
) {
741 lane
= serdes_get_first_lane(FSL_SRDS_2
, SGMII9
+
743 slot
= lane_to_slot_fsm2
[lane
];
751 /* Slot housing a SGMII riser card? */
752 wriop_set_phy_address(dpmac_id
, 0,
753 riser_phy_addr
[dpmac_id
- 9]);
754 dpmac_info
[dpmac_id
].board_mux
= EMI1_SLOT4
;
755 bus
= mii_dev_for_muxval(EMI1_SLOT4
);
756 wriop_set_mdio(dpmac_id
, bus
);
759 if (slot
== EMI_NONE
)
761 if (serdes2_prtcl
== 0x47) {
762 wriop_set_phy_address(dpmac_id
, 0,
763 riser_phy_addr
[dpmac_id
- 10]);
764 if (dpmac_id
>= 14 && hwconfig_f("xqsgmii",
766 wriop_set_phy_address(dpmac_id
, 0,
767 riser_phy_addr
[dpmac_id
- 11]);
769 wriop_set_phy_address(dpmac_id
, 0,
770 riser_phy_addr
[dpmac_id
- 11]);
772 dpmac_info
[dpmac_id
].board_mux
= EMI1_SLOT5
;
773 bus
= mii_dev_for_muxval(EMI1_SLOT5
);
774 wriop_set_mdio(dpmac_id
, bus
);
777 /* Slot housing a SGMII riser card? */
778 wriop_set_phy_address(dpmac_id
, 0,
779 riser_phy_addr
[dpmac_id
- 13]);
780 dpmac_info
[dpmac_id
].board_mux
= EMI1_SLOT6
;
781 bus
= mii_dev_for_muxval(EMI1_SLOT6
);
782 wriop_set_mdio(dpmac_id
, bus
);
787 printf("%s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
788 __func__
, serdes2_prtcl
);
793 void ls2080a_handle_phy_interface_qsgmii(int dpmac_id
)
797 struct ccsr_gur __iomem
*gur
= (void *)CONFIG_SYS_FSL_GUTS_ADDR
;
798 int serdes1_prtcl
= (in_le32(&gur
->rcwsr
[28]) &
799 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK
)
800 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT
;
802 switch (serdes1_prtcl
) {
809 lane
= serdes_get_first_lane(FSL_SRDS_1
, QSGMII_A
);
815 lane
= serdes_get_first_lane(FSL_SRDS_1
, QSGMII_B
);
821 lane
= serdes_get_first_lane(FSL_SRDS_1
, QSGMII_C
);
827 lane
= serdes_get_first_lane(FSL_SRDS_1
, QSGMII_D
);
831 slot
= lane_to_slot_fsm1
[lane
];
835 /* Slot housing a QSGMII riser card? */
836 wriop_set_phy_address(dpmac_id
, 0, dpmac_id
- 1);
837 dpmac_info
[dpmac_id
].board_mux
= EMI1_SLOT1
;
838 bus
= mii_dev_for_muxval(EMI1_SLOT1
);
839 wriop_set_mdio(dpmac_id
, bus
);
852 printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
857 qsgmii_configure_repeater(dpmac_id
);
860 void ls2080a_handle_phy_interface_xsgmii(int i
)
862 struct ccsr_gur __iomem
*gur
= (void *)CONFIG_SYS_FSL_GUTS_ADDR
;
863 int serdes1_prtcl
= (in_le32(&gur
->rcwsr
[28]) &
864 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK
)
865 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT
;
867 switch (serdes1_prtcl
) {
872 * XFI does not need a PHY to work, but to avoid U-Boot use
873 * default PHY address which is zero to a MAC when it found
874 * a MAC has no PHY address, we give a PHY address to XFI
875 * MAC, and should not use a real XAUI PHY address, since
876 * MDIO can access it successfully, and then MDIO thinks
877 * the XAUI card is used for the XFI MAC, which will cause
880 wriop_set_phy_address(i
, 0, i
+ 4);
881 ls2080a_qds_enable_SFP_TX(SFP_TX
);
885 printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
892 int board_eth_init(bd_t
*bis
)
895 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
896 struct ccsr_gur __iomem
*gur
= (void *)CONFIG_SYS_FSL_GUTS_ADDR
;
897 int serdes1_prtcl
= (in_le32(&gur
->rcwsr
[28]) &
898 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK
)
899 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT
;
900 int serdes2_prtcl
= (in_le32(&gur
->rcwsr
[28]) &
901 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK
)
902 >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
;
904 struct memac_mdio_info
*memac_mdio0_info
;
905 struct memac_mdio_info
*memac_mdio1_info
;
909 env_hwconfig
= env_get("hwconfig");
911 initialize_dpmac_to_slot();
913 memac_mdio0_info
= (struct memac_mdio_info
*)malloc(
914 sizeof(struct memac_mdio_info
));
915 memac_mdio0_info
->regs
=
916 (struct memac_mdio_controller
*)
917 CONFIG_SYS_FSL_WRIOP1_MDIO1
;
918 memac_mdio0_info
->name
= DEFAULT_WRIOP_MDIO1_NAME
;
920 /* Register the real MDIO1 bus */
921 fm_memac_mdio_init(bis
, memac_mdio0_info
);
923 memac_mdio1_info
= (struct memac_mdio_info
*)malloc(
924 sizeof(struct memac_mdio_info
));
925 memac_mdio1_info
->regs
=
926 (struct memac_mdio_controller
*)
927 CONFIG_SYS_FSL_WRIOP1_MDIO2
;
928 memac_mdio1_info
->name
= DEFAULT_WRIOP_MDIO2_NAME
;
930 /* Register the real MDIO2 bus */
931 fm_memac_mdio_init(bis
, memac_mdio1_info
);
933 /* Register the muxing front-ends to the MDIO buses */
934 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME
, EMI1_SLOT1
);
935 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME
, EMI1_SLOT2
);
936 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME
, EMI1_SLOT3
);
937 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME
, EMI1_SLOT4
);
938 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME
, EMI1_SLOT5
);
939 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME
, EMI1_SLOT6
);
941 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO2_NAME
, EMI2
);
943 for (i
= WRIOP1_DPMAC1
; i
< NUM_WRIOP_PORTS
; i
++) {
944 switch (wriop_get_enet_if(i
)) {
945 case PHY_INTERFACE_MODE_QSGMII
:
946 ls2080a_handle_phy_interface_qsgmii(i
);
948 case PHY_INTERFACE_MODE_SGMII
:
949 ls2080a_handle_phy_interface_sgmii(i
);
951 case PHY_INTERFACE_MODE_XGMII
:
952 ls2080a_handle_phy_interface_xsgmii(i
);
962 error
= cpu_eth_init(bis
);
964 if (hwconfig_f("xqsgmii", env_hwconfig
)) {
965 if (serdes1_prtcl
== 0x7)
966 sgmii_configure_repeater(1);
967 if (serdes2_prtcl
== 0x7 || serdes2_prtcl
== 0x8 ||
968 serdes2_prtcl
== 0x49)
969 sgmii_configure_repeater(2);
972 error
= pci_eth_init(bis
);
976 #if defined(CONFIG_RESET_PHY_R)
981 #endif /* CONFIG_RESET_PHY_R */