board/freescale/ls2080ardb/ls2080ardb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2015 Freescale Semiconductor
   4  * Copyright 2017 NXP
   5  */
   6 #include <common.h>
   7 #include <env.h>
   8 #include <malloc.h>
   9 #include <errno.h>
  10 #include <netdev.h>
  11 #include <fsl_ifc.h>
  12 #include <fsl_ddr.h>
  13 #include <asm/io.h>
  14 #include <hwconfig.h>
  15 #include <fdt_support.h>
  16 #include <linux/libfdt.h>
  17 #include <fsl-mc/fsl_mc.h>
  18 #include <env_internal.h>
  19 #include <efi_loader.h>
  20 #include <i2c.h>
  21 #include <asm/arch/mmu.h>
  22 #include <asm/arch/soc.h>
  23 #include <asm/arch/ppa.h>
  24 #include <fsl_sec.h>
  25
  26 #ifdef CONFIG_FSL_QIXIS
  27 #include "../common/qixis.h"
  28 #include "ls2080ardb_qixis.h"
  29 #endif
  30 #include "../common/vid.h"
  31
  32 #define PIN_MUX_SEL_SDHC        0x00
  33 #define PIN_MUX_SEL_DSPI        0x0a
  34
  35 #define SET_SDHC_MUX_SEL(reg, value)    ((reg & 0xf0) | value)
  36 DECLARE_GLOBAL_DATA_PTR;
  37
  38 enum {
  39         MUX_TYPE_SDHC,
  40         MUX_TYPE_DSPI,
  41 };
  42
  43 unsigned long long get_qixis_addr(void)
  44 {
  45         unsigned long long addr;
  46
  47         if (gd->flags & GD_FLG_RELOC)
  48                 addr = QIXIS_BASE_PHYS;
  49         else
  50                 addr = QIXIS_BASE_PHYS_EARLY;
  51
  52         /*
  53          * IFC address under 256MB is mapped to 0x30000000, any address above
  54          * is mapped to 0x5_10000000 up to 4GB.
  55          */
  56         addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
  57
  58         return addr;
  59 }
  60
  61 int checkboard(void)
  62 {
  63 #ifdef CONFIG_FSL_QIXIS
  64         u8 sw;
  65 #endif
  66         char buf[15];
  67
  68         cpu_name(buf);
  69         printf("Board: %s-RDB, ", buf);
  70
  71 #ifdef CONFIG_TARGET_LS2081ARDB
  72 #ifdef CONFIG_FSL_QIXIS
  73         sw = QIXIS_READ(arch);
  74         printf("Board version: %c, ", (sw & 0xf) + 'A');
  75
  76         sw = QIXIS_READ(brdcfg[0]);
  77         sw = (sw >> QIXIS_QMAP_SHIFT) & QIXIS_QMAP_MASK;
  78         switch (sw) {
  79         case 0:
  80                 puts("boot from QSPI DEV#0\n");
  81                 puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
  82                 break;
  83         case 1:
  84                 puts("boot from QSPI DEV#1\n");
  85                 puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
  86                 break;
  87         case 2:
  88                 puts("boot from QSPI EMU\n");
  89                 puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
  90                 break;
  91         case 3:
  92                 puts("boot from QSPI EMU\n");
  93                 puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
  94                 break;
  95         case 4:
  96                 puts("boot from QSPI DEV#0\n");
  97                 puts("QSPI_CSA_1 mapped to QSPI EMU\n");
  98                 break;
  99         default:
 100                 printf("invalid setting of SW%u\n", sw);
 101                 break;
 102         }
 103         printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
 104 #endif
 105         puts("SERDES1 Reference : ");
 106         printf("Clock1 = 100MHz ");
 107         printf("Clock2 = 161.13MHz");
 108 #else
 109 #ifdef CONFIG_FSL_QIXIS
 110         sw = QIXIS_READ(arch);
 111         printf("Board Arch: V%d, ", sw >> 4);
 112         printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
 113
 114         sw = QIXIS_READ(brdcfg[0]);
 115         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 116
 117         if (sw < 0x8)
 118                 printf("vBank: %d\n", sw);
 119         else if (sw == 0x9)
 120                 puts("NAND\n");
 121         else
 122                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 123
 124         printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
 125 #endif
 126         puts("SERDES1 Reference : ");
 127         printf("Clock1 = 156.25MHz ");
 128         printf("Clock2 = 156.25MHz");
 129 #endif
 130
 131         puts("\nSERDES2 Reference : ");
 132         printf("Clock1 = 100MHz ");
 133         printf("Clock2 = 100MHz\n");
 134
 135         return 0;
 136 }
 137
 138 unsigned long get_board_sys_clk(void)
 139 {
 140 #ifdef CONFIG_FSL_QIXIS
 141         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 142
 143         switch (sysclk_conf & 0x0F) {
 144         case QIXIS_SYSCLK_83:
 145                 return 83333333;
 146         case QIXIS_SYSCLK_100:
 147                 return 100000000;
 148         case QIXIS_SYSCLK_125:
 149                 return 125000000;
 150         case QIXIS_SYSCLK_133:
 151                 return 133333333;
 152         case QIXIS_SYSCLK_150:
 153                 return 150000000;
 154         case QIXIS_SYSCLK_160:
 155                 return 160000000;
 156         case QIXIS_SYSCLK_166:
 157                 return 166666666;
 158         }
 159 #endif
 160         return 100000000;
 161 }
 162
 163 int select_i2c_ch_pca9547(u8 ch)
 164 {
 165         int ret;
 166
 167         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
 168         if (ret) {
 169                 puts("PCA: failed to select proper channel\n");
 170                 return ret;
 171         }
 172
 173         return 0;
 174 }
 175
 176 int i2c_multiplexer_select_vid_channel(u8 channel)
 177 {
 178         return select_i2c_ch_pca9547(channel);
 179 }
 180
 181 int config_board_mux(int ctrl_type)
 182 {
 183 #ifdef CONFIG_FSL_QIXIS
 184         u8 reg5;
 185
 186         reg5 = QIXIS_READ(brdcfg[5]);
 187
 188         switch (ctrl_type) {
 189         case MUX_TYPE_SDHC:
 190                 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
 191                 break;
 192         case MUX_TYPE_DSPI:
 193                 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
 194                 break;
 195         default:
 196                 printf("Wrong mux interface type\n");
 197                 return -1;
 198         }
 199
 200         QIXIS_WRITE(brdcfg[5], reg5);
 201 #endif
 202         return 0;
 203 }
 204
 205 int board_init(void)
 206 {
 207 #ifdef CONFIG_FSL_MC_ENET
 208         u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
 209 #endif
 210
 211         init_final_memctl_regs();
 212
 213 #ifdef CONFIG_ENV_IS_NOWHERE
 214         gd->env_addr = (ulong)&default_environment[0];
 215 #endif
 216         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 217
 218 #ifdef CONFIG_FSL_QIXIS
 219         QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
 220 #endif
 221
 222 #ifdef CONFIG_FSL_CAAM
 223         sec_init();
 224 #endif
 225 #ifdef CONFIG_FSL_LS_PPA
 226         ppa_init();
 227 #endif
 228
 229 #ifdef CONFIG_FSL_MC_ENET
 230         /* invert AQR405 IRQ pins polarity */
 231         out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
 232 #endif
 233 #ifdef CONFIG_FSL_CAAM
 234         sec_init();
 235 #endif
 236
 237         return 0;
 238 }
 239
 240 int board_early_init_f(void)
 241 {
 242 #ifdef CONFIG_SYS_I2C_EARLY_INIT
 243         i2c_early_init_f();
 244 #endif
 245         fsl_lsch3_early_init_f();
 246         return 0;
 247 }
 248
 249 int misc_init_r(void)
 250 {
 251         char *env_hwconfig;
 252         u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
 253         u32 val;
 254         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 255         u32 svr = gur_in32(&gur->svr);
 256
 257         val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
 258
 259         env_hwconfig = env_get("hwconfig");
 260
 261         if (hwconfig_f("dspi", env_hwconfig) &&
 262             DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
 263                 config_board_mux(MUX_TYPE_DSPI);
 264         else
 265                 config_board_mux(MUX_TYPE_SDHC);
 266
 267         /*
 268          * LS2081ARDB RevF board has smart voltage translator
 269          * which needs to be programmed to enable high speed SD interface
 270          * by setting GPIO4_10 output to zero
 271          */
 272 #ifdef CONFIG_TARGET_LS2081ARDB
 273                 out_le32(GPIO4_GPDIR_ADDR, (1 << 21 |
 274                                             in_le32(GPIO4_GPDIR_ADDR)));
 275                 out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) &
 276                                             in_le32(GPIO4_GPDAT_ADDR)));
 277 #endif
 278         if (hwconfig("sdhc"))
 279                 config_board_mux(MUX_TYPE_SDHC);
 280
 281         if (adjust_vdd(0))
 282                 printf("Warning: Adjusting core voltage failed.\n");
 283         /*
 284          * Default value of board env is based on filename which is
 285          * ls2080ardb. Modify board env for other supported SoCs
 286          */
 287         if ((SVR_SOC_VER(svr) == SVR_LS2088A) ||
 288             (SVR_SOC_VER(svr) == SVR_LS2048A))
 289                 env_set("board", "ls2088ardb");
 290         else if ((SVR_SOC_VER(svr) == SVR_LS2081A) ||
 291             (SVR_SOC_VER(svr) == SVR_LS2041A))
 292                 env_set("board", "ls2081ardb");
 293
 294         return 0;
 295 }
 296
 297 void detail_board_ddr_info(void)
 298 {
 299         puts("\nDDR    ");
 300         print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 301         print_ddr_info(0);
 302 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 303         if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
 304                 puts("\nDP-DDR ");
 305                 print_size(gd->bd->bi_dram[2].size, "");
 306                 print_ddr_info(CONFIG_DP_DDR_CTRL);
 307         }
 308 #endif
 309 }
 310
 311 #if defined(CONFIG_ARCH_MISC_INIT)
 312 int arch_misc_init(void)
 313 {
 314         return 0;
 315 }
 316 #endif
 317
 318 #ifdef CONFIG_FSL_MC_ENET
 319 void fdt_fixup_board_enet(void *fdt)
 320 {
 321         int offset;
 322
 323         offset = fdt_path_offset(fdt, "/soc/fsl-mc");
 324
 325         if (offset < 0)
 326                 offset = fdt_path_offset(fdt, "/fsl-mc");
 327
 328         if (offset < 0) {
 329                 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
 330                        __func__, offset);
 331                 return;
 332         }
 333
 334         if (get_mc_boot_status() == 0 &&
 335             (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
 336                 fdt_status_okay(fdt, offset);
 337         else
 338                 fdt_status_fail(fdt, offset);
 339 }
 340
 341 void board_quiesce_devices(void)
 342 {
 343         fsl_mc_ldpaa_exit(gd->bd);
 344 }
 345 #endif
 346
 347 #ifdef CONFIG_OF_BOARD_SETUP
 348 void fsl_fdt_fixup_flash(void *fdt)
 349 {
 350         int offset;
 351 #ifdef CONFIG_TFABOOT
 352         u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
 353         u32 val;
 354 #endif
 355
 356 /*
 357  * IFC and QSPI are muxed on board.
 358  * So disable IFC node in dts if QSPI is enabled or
 359  * disable QSPI node in dts in case QSPI is not enabled.
 360  */
 361 #ifdef CONFIG_TFABOOT
 362         enum boot_src src = get_boot_src();
 363         bool disable_ifc = false;
 364
 365         switch (src) {
 366         case BOOT_SOURCE_IFC_NOR:
 367                 disable_ifc = false;
 368                 break;
 369         case BOOT_SOURCE_QSPI_NOR:
 370                 disable_ifc = true;
 371                 break;
 372         default:
 373                 val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
 374                 if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
 375                         disable_ifc = true;
 376                 break;
 377         }
 378
 379         if (disable_ifc) {
 380                 offset = fdt_path_offset(fdt, "/soc/ifc");
 381
 382                 if (offset < 0)
 383                         offset = fdt_path_offset(fdt, "/ifc");
 384         } else {
 385                 offset = fdt_path_offset(fdt, "/soc/quadspi");
 386
 387                 if (offset < 0)
 388                         offset = fdt_path_offset(fdt, "/quadspi");
 389         }
 390
 391 #else
 392 #ifdef CONFIG_FSL_QSPI
 393         offset = fdt_path_offset(fdt, "/soc/ifc");
 394
 395         if (offset < 0)
 396                 offset = fdt_path_offset(fdt, "/ifc");
 397 #else
 398         offset = fdt_path_offset(fdt, "/soc/quadspi");
 399
 400         if (offset < 0)
 401                 offset = fdt_path_offset(fdt, "/quadspi");
 402 #endif
 403 #endif
 404
 405         if (offset < 0)
 406                 return;
 407
 408         fdt_status_disabled(fdt, offset);
 409 }
 410
 411 int ft_board_setup(void *blob, bd_t *bd)
 412 {
 413         u64 base[CONFIG_NR_DRAM_BANKS];
 414         u64 size[CONFIG_NR_DRAM_BANKS];
 415
 416         ft_cpu_setup(blob, bd);
 417
 418         /* fixup DT for the two GPP DDR banks */
 419         base[0] = gd->bd->bi_dram[0].start;
 420         size[0] = gd->bd->bi_dram[0].size;
 421         base[1] = gd->bd->bi_dram[1].start;
 422         size[1] = gd->bd->bi_dram[1].size;
 423
 424 #ifdef CONFIG_RESV_RAM
 425         /* reduce size if reserved memory is within this bank */
 426         if (gd->arch.resv_ram >= base[0] &&
 427             gd->arch.resv_ram < base[0] + size[0])
 428                 size[0] = gd->arch.resv_ram - base[0];
 429         else if (gd->arch.resv_ram >= base[1] &&
 430                  gd->arch.resv_ram < base[1] + size[1])
 431                 size[1] = gd->arch.resv_ram - base[1];
 432 #endif
 433
 434         fdt_fixup_memory_banks(blob, base, size, 2);
 435
 436         fdt_fsl_mc_fixup_iommu_map_entry(blob);
 437
 438         fsl_fdt_fixup_dr_usb(blob, bd);
 439
 440         fsl_fdt_fixup_flash(blob);
 441
 442 #ifdef CONFIG_FSL_MC_ENET
 443         fdt_fixup_board_enet(blob);
 444 #endif
 445
 446         return 0;
 447 }
 448 #endif
 449
 450 void qixis_dump_switch(void)
 451 {
 452 #ifdef CONFIG_FSL_QIXIS
 453         int i, nr_of_cfgsw;
 454
 455         QIXIS_WRITE(cms[0], 0x00);
 456         nr_of_cfgsw = QIXIS_READ(cms[1]);
 457
 458         puts("DIP switch settings dump:\n");
 459         for (i = 1; i <= nr_of_cfgsw; i++) {
 460                 QIXIS_WRITE(cms[0], i);
 461                 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
 462         }
 463 #endif
 464 }
 465
 466 /*
 467  * Board rev C and earlier has duplicated I2C addresses for 2nd controller.
 468  * Both slots has 0x54, resulting 2nd slot unusable.
 469  */
 470 void update_spd_address(unsigned int ctrl_num,
 471                         unsigned int slot,
 472                         unsigned int *addr)
 473 {
 474 #ifndef CONFIG_TARGET_LS2081ARDB
 475 #ifdef CONFIG_FSL_QIXIS
 476         u8 sw;
 477
 478         sw = QIXIS_READ(arch);
 479         if ((sw & 0xf) < 0x3) {
 480                 if (ctrl_num == 1 && slot == 0)
 481                         *addr = SPD_EEPROM_ADDRESS4;
 482                 else if (ctrl_num == 1 && slot == 1)
 483                         *addr = SPD_EEPROM_ADDRESS3;
 484         }
 485 #endif
 486 #endif
 487 }