1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
8 #include <dm/platform_data/serial_pl01x.h>
16 #include <fdt_support.h>
17 #include <linux/libfdt.h>
18 #include <fsl-mc/fsl_mc.h>
19 #include <env_internal.h>
20 #include <efi_loader.h>
21 #include <asm/arch/mmu.h>
23 #include <asm/arch/fsl_serdes.h>
24 #include <asm/arch/soc.h>
25 #include "../common/qixis.h"
26 #include "../common/vid.h"
27 #include <fsl_immap.h>
30 #include "../common/emc2305.h"
33 #ifdef CONFIG_TARGET_LX2160AQDS
34 #define CFG_MUX_I2C_SDHC(reg, value) ((reg & 0x3f) | value)
35 #define SET_CFG_MUX1_SDHC1_SDHC(reg) (reg & 0x3f)
36 #define SET_CFG_MUX2_SDHC1_SPI(reg, value) ((reg & 0xcf) | value)
37 #define SET_CFG_MUX3_SDHC1_SPI(reg, value) ((reg & 0xf8) | value)
38 #define SET_CFG_MUX_SDHC2_DSPI(reg, value) ((reg & 0xf8) | value)
39 #define SET_CFG_MUX1_SDHC1_DSPI(reg, value) ((reg & 0x3f) | value)
40 #define SDHC1_BASE_PMUX_DSPI 2
41 #define SDHC2_BASE_PMUX_DSPI 2
42 #define IIC5_PMUX_SPI3 3
43 #endif /* CONFIG_TARGET_LX2160AQDS */
45 DECLARE_GLOBAL_DATA_PTR
;
47 static struct pl01x_serial_platdata serial0
= {
48 #if CONFIG_CONS_INDEX == 0
49 .base
= CONFIG_SYS_SERIAL0
,
50 #elif CONFIG_CONS_INDEX == 1
51 .base
= CONFIG_SYS_SERIAL1
,
53 #error "Unsupported console index value."
58 U_BOOT_DEVICE(nxp_serial0
) = {
59 .name
= "serial_pl01x",
63 static struct pl01x_serial_platdata serial1
= {
64 .base
= CONFIG_SYS_SERIAL1
,
68 U_BOOT_DEVICE(nxp_serial1
) = {
69 .name
= "serial_pl01x",
73 int select_i2c_ch_pca9547(u8 ch
)
78 ret
= i2c_write(I2C_MUX_PCA_ADDR_PRI
, 0, 1, &ch
, 1);
82 ret
= i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI
, 1, &dev
);
84 ret
= dm_i2c_write(dev
, 0, &ch
, 1);
87 puts("PCA: failed to select proper channel\n");
94 static void uart_get_clock(void)
96 serial0
.clock
= get_serial_clock();
97 serial1
.clock
= get_serial_clock();
100 int board_early_init_f(void)
102 #ifdef CONFIG_SYS_I2C_EARLY_INIT
105 /* get required clock for UART IP */
108 #ifdef CONFIG_EMC2305
109 select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305
);
111 set_fan_speed(I2C_EMC2305_PWM
);
112 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT
);
115 fsl_lsch3_early_init_f();
119 #if defined(CONFIG_TARGET_LX2160AQDS)
120 void esdhc_dspi_status_fixup(void *blob
)
122 const char esdhc0_path
[] = "/soc/esdhc@2140000";
123 const char esdhc1_path
[] = "/soc/esdhc@2150000";
124 const char dspi0_path
[] = "/soc/dspi@2100000";
125 const char dspi1_path
[] = "/soc/dspi@2110000";
126 const char dspi2_path
[] = "/soc/dspi@2120000";
128 struct ccsr_gur __iomem
*gur
= (void *)(CONFIG_SYS_FSL_GUTS_ADDR
);
133 /* Check RCW field sdhc1_base_pmux to enable/disable
134 * esdhc0/dspi0 DT node
136 sdhc1_base_pmux
= gur_in32(&gur
->rcwsr
[FSL_CHASSIS3_RCWSR12_REGSR
- 1])
137 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK
;
138 sdhc1_base_pmux
>>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT
;
140 if (sdhc1_base_pmux
== SDHC1_BASE_PMUX_DSPI
) {
141 do_fixup_by_path(blob
, dspi0_path
, "status", "okay",
143 do_fixup_by_path(blob
, esdhc0_path
, "status", "disabled",
144 sizeof("disabled"), 1);
146 do_fixup_by_path(blob
, esdhc0_path
, "status", "okay",
148 do_fixup_by_path(blob
, dspi0_path
, "status", "disabled",
149 sizeof("disabled"), 1);
152 /* Check RCW field sdhc2_base_pmux to enable/disable
153 * esdhc1/dspi1 DT node
155 sdhc2_base_pmux
= gur_in32(&gur
->rcwsr
[FSL_CHASSIS3_RCWSR13_REGSR
- 1])
156 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK
;
157 sdhc2_base_pmux
>>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT
;
159 if (sdhc2_base_pmux
== SDHC2_BASE_PMUX_DSPI
) {
160 do_fixup_by_path(blob
, dspi1_path
, "status", "okay",
162 do_fixup_by_path(blob
, esdhc1_path
, "status", "disabled",
163 sizeof("disabled"), 1);
165 do_fixup_by_path(blob
, esdhc1_path
, "status", "okay",
167 do_fixup_by_path(blob
, dspi1_path
, "status", "disabled",
168 sizeof("disabled"), 1);
171 /* Check RCW field IIC5 to enable dspi2 DT node */
172 iic5_pmux
= gur_in32(&gur
->rcwsr
[FSL_CHASSIS3_RCWSR12_REGSR
- 1])
173 & FSL_CHASSIS3_IIC5_PMUX_MASK
;
174 iic5_pmux
>>= FSL_CHASSIS3_IIC5_PMUX_SHIFT
;
176 if (iic5_pmux
== IIC5_PMUX_SPI3
) {
177 do_fixup_by_path(blob
, dspi2_path
, "status", "okay",
183 int esdhc_status_fixup(void *blob
, const char *compat
)
185 #if defined(CONFIG_TARGET_LX2160AQDS)
186 /* Enable esdhc and dspi DT nodes based on RCW fields */
187 esdhc_dspi_status_fixup(blob
);
189 /* Enable both esdhc DT nodes for LX2160ARDB */
190 do_fixup_by_compat(blob
, compat
, "status", "okay",
196 #if defined(CONFIG_VID)
197 int i2c_multiplexer_select_vid_channel(u8 channel
)
199 return select_i2c_ch_pca9547(channel
);
202 int init_func_vid(void)
204 if (adjust_vdd(0) < 0)
205 printf("core voltage not adjusted\n");
213 enum boot_src src
= get_boot_src();
216 #ifdef CONFIG_TARGET_LX2160AQDS
218 static const char *const freq
[] = {"100", "125", "156.25",
219 "161.13", "322.26", "", "", "",
220 "", "", "", "", "", "", "",
221 "100 separate SSCG"};
225 #ifdef CONFIG_TARGET_LX2160AQDS
226 printf("Board: %s-QDS, ", buf
);
228 printf("Board: %s-RDB, ", buf
);
231 sw
= QIXIS_READ(arch
);
232 printf("Board version: %c, boot from ", (sw
& 0xf) - 1 + 'A');
234 if (src
== BOOT_SOURCE_SD_MMC
) {
237 sw
= QIXIS_READ(brdcfg
[0]);
238 sw
= (sw
>> QIXIS_XMAP_SHIFT
) & QIXIS_XMAP_MASK
;
242 puts("FlexSPI DEV#0\n");
245 puts("FlexSPI DEV#1\n");
249 puts("FlexSPI EMU\n");
252 printf("invalid setting, xmap: %d\n", sw
);
256 #ifdef CONFIG_TARGET_LX2160AQDS
257 printf("FPGA: v%d (%s), build %d",
258 (int)QIXIS_READ(scver
), qixis_read_tag(buf
),
259 (int)qixis_read_minor());
260 /* the timestamp string contains "\n" at the end */
261 printf(" on %s", qixis_read_time(buf
));
263 puts("SERDES1 Reference : ");
264 sw
= QIXIS_READ(brdcfg
[2]);
266 printf("Clock1 = %sMHz ", freq
[clock
]);
268 printf("Clock2 = %sMHz", freq
[clock
]);
270 sw
= QIXIS_READ(brdcfg
[3]);
271 puts("\nSERDES2 Reference : ");
273 printf("Clock1 = %sMHz ", freq
[clock
]);
275 printf("Clock2 = %sMHz", freq
[clock
]);
277 sw
= QIXIS_READ(brdcfg
[12]);
278 puts("\nSERDES3 Reference : ");
280 printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq
[clock
], freq
[clock
]);
282 printf("FPGA: v%d.%d\n", QIXIS_READ(scver
), QIXIS_READ(tagdata
));
284 puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
285 puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
286 puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100Hz\n");
291 #ifdef CONFIG_TARGET_LX2160AQDS
293 * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
295 u8
qixis_esdhc_detect_quirk(void)
297 /* for LX2160AQDS res1[1] @ offset 0x1A is SDHC1 Control/Status (SDHC1)
299 * Specifies the type of card installed in the SDHC1 adapter slot.
301 * 001= eMMC V4.5 adapter is installed.
302 * 010= SD/MMC 3.3V adapter is installed.
303 * 011= eMMC V4.4 adapter is installed.
304 * 100= eMMC V5.0 adapter is installed.
305 * 101= MMC card/Legacy (3.3V) adapter is installed.
306 * 110= SDCard V2/V3 adapter installed.
307 * 111= no adapter is installed.
309 return ((QIXIS_READ(res1
[1]) & QIXIS_SDID_MASK
) !=
310 QIXIS_ESDHC_NO_ADAPTER
);
313 int config_board_mux(void)
315 u8 reg11
, reg5
, reg13
;
316 struct ccsr_gur __iomem
*gur
= (void *)(CONFIG_SYS_FSL_GUTS_ADDR
);
321 /* Routes {I2C2_SCL, I2C2_SDA} to SDHC1 as {SDHC1_CD_B, SDHC1_WP}.
322 * Routes {I2C3_SCL, I2C3_SDA} to CAN transceiver as {CAN1_TX,CAN1_RX}.
323 * Routes {I2C4_SCL, I2C4_SDA} to CAN transceiver as {CAN2_TX,CAN2_RX}.
324 * Qixis and remote systems are isolated from the I2C1 bus.
325 * Processor connections are still available.
326 * SPI2 CS2_B controls EN25S64 SPI memory device.
327 * SPI3 CS2_B controls EN25S64 SPI memory device.
328 * EC2 connects to PHY #2 using RGMII protocol.
329 * CLK_OUT connects to FPGA for clock measurement.
332 reg5
= QIXIS_READ(brdcfg
[5]);
333 reg5
= CFG_MUX_I2C_SDHC(reg5
, 0x40);
334 QIXIS_WRITE(brdcfg
[5], reg5
);
336 /* Check RCW field sdhc1_base_pmux
337 * esdhc0 : sdhc1_base_pmux = 0
338 * dspi0 : sdhc1_base_pmux = 2
340 sdhc1_base_pmux
= gur_in32(&gur
->rcwsr
[FSL_CHASSIS3_RCWSR12_REGSR
- 1])
341 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK
;
342 sdhc1_base_pmux
>>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT
;
344 if (sdhc1_base_pmux
== SDHC1_BASE_PMUX_DSPI
) {
345 reg11
= QIXIS_READ(brdcfg
[11]);
346 reg11
= SET_CFG_MUX1_SDHC1_DSPI(reg11
, 0x40);
347 QIXIS_WRITE(brdcfg
[11], reg11
);
349 /* - Routes {SDHC1_CMD, SDHC1_CLK } to SDHC1 adapter slot.
350 * {SDHC1_DAT3, SDHC1_DAT2} to SDHC1 adapter slot.
351 * {SDHC1_DAT1, SDHC1_DAT0} to SDHC1 adapter slot.
353 reg11
= QIXIS_READ(brdcfg
[11]);
354 reg11
= SET_CFG_MUX1_SDHC1_SDHC(reg11
);
355 QIXIS_WRITE(brdcfg
[11], reg11
);
358 /* Check RCW field sdhc2_base_pmux
359 * esdhc1 : sdhc2_base_pmux = 0 (default)
360 * dspi1 : sdhc2_base_pmux = 2
362 sdhc2_base_pmux
= gur_in32(&gur
->rcwsr
[FSL_CHASSIS3_RCWSR13_REGSR
- 1])
363 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK
;
364 sdhc2_base_pmux
>>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT
;
366 if (sdhc2_base_pmux
== SDHC2_BASE_PMUX_DSPI
) {
367 reg13
= QIXIS_READ(brdcfg
[13]);
368 reg13
= SET_CFG_MUX_SDHC2_DSPI(reg13
, 0x01);
369 QIXIS_WRITE(brdcfg
[13], reg13
);
371 reg13
= QIXIS_READ(brdcfg
[13]);
372 reg13
= SET_CFG_MUX_SDHC2_DSPI(reg13
, 0x00);
373 QIXIS_WRITE(brdcfg
[13], reg13
);
376 /* Check RCW field IIC5 to enable dspi2 DT nodei
379 iic5_pmux
= gur_in32(&gur
->rcwsr
[FSL_CHASSIS3_RCWSR12_REGSR
- 1])
380 & FSL_CHASSIS3_IIC5_PMUX_MASK
;
381 iic5_pmux
>>= FSL_CHASSIS3_IIC5_PMUX_SHIFT
;
383 if (iic5_pmux
== IIC5_PMUX_SPI3
) {
384 /* - Routes {SDHC1_DAT4} to SPI3 devices as {SPI3_M_CS0_B}. */
385 reg11
= QIXIS_READ(brdcfg
[11]);
386 reg11
= SET_CFG_MUX2_SDHC1_SPI(reg11
, 0x10);
387 QIXIS_WRITE(brdcfg
[11], reg11
);
389 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} nowhere.
390 * {SDHC1_DAT7, SDHC1_DS } to {nothing, SPI3_M0_CLK }.
391 * {I2C5_SCL, I2C5_SDA } to {SPI3_M0_MOSI, SPI3_M0_MISO}.
393 reg11
= QIXIS_READ(brdcfg
[11]);
394 reg11
= SET_CFG_MUX3_SDHC1_SPI(reg11
, 0x01);
395 QIXIS_WRITE(brdcfg
[11], reg11
);
397 /* Routes {SDHC1_DAT4} to SDHC1 adapter slot */
398 reg11
= QIXIS_READ(brdcfg
[11]);
399 reg11
= SET_CFG_MUX2_SDHC1_SPI(reg11
, 0x00);
400 QIXIS_WRITE(brdcfg
[11], reg11
);
402 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot.
403 * {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot.
404 * {I2C5_SCL, I2C5_SDA } to SDHC1 adapter slot.
406 reg11
= QIXIS_READ(brdcfg
[11]);
407 reg11
= SET_CFG_MUX3_SDHC1_SPI(reg11
, 0x00);
408 QIXIS_WRITE(brdcfg
[11], reg11
);
413 #elif defined(CONFIG_TARGET_LX2160ARDB)
414 int config_board_mux(void)
418 brdcfg
= QIXIS_READ(brdcfg
[4]);
419 /* The BRDCFG4 register controls general board configuration.
420 *|-------------------------------------------|
422 *|-------------------------------------------|
423 *|5 | CAN I/O Enable (net CFG_CAN_EN_B):|
424 *|CAN_EN | 0= CAN transceivers are disabled. |
425 *| | 1= CAN transceivers are enabled. |
426 *|-------------------------------------------|
428 brdcfg
|= BIT_MASK(5);
429 QIXIS_WRITE(brdcfg
[4], brdcfg
);
434 int config_board_mux(void)
440 unsigned long get_board_sys_clk(void)
442 #ifdef CONFIG_TARGET_LX2160AQDS
443 u8 sysclk_conf
= QIXIS_READ(brdcfg
[1]);
445 switch (sysclk_conf
& 0x03) {
446 case QIXIS_SYSCLK_100
:
448 case QIXIS_SYSCLK_125
:
450 case QIXIS_SYSCLK_133
:
459 unsigned long get_board_ddr_clk(void)
461 #ifdef CONFIG_TARGET_LX2160AQDS
462 u8 ddrclk_conf
= QIXIS_READ(brdcfg
[1]);
464 switch ((ddrclk_conf
& 0x30) >> 4) {
465 case QIXIS_DDRCLK_100
:
467 case QIXIS_DDRCLK_125
:
469 case QIXIS_DDRCLK_133
:
480 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
481 u32 __iomem
*irq_ccsr
= (u32 __iomem
*)ISC_BASE
;
483 #ifdef CONFIG_ENV_IS_NOWHERE
484 gd
->env_addr
= (ulong
)&default_environment
[0];
487 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT
);
489 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
490 /* invert AQR107 IRQ pins polarity */
491 out_le32(irq_ccsr
+ IRQCR_OFFSET
/ 4, AQR107_IRQ_MASK
);
494 #ifdef CONFIG_FSL_CAAM
501 void detail_board_ddr_info(void)
507 for (i
= 0; i
< CONFIG_NR_DRAM_BANKS
; i
++)
508 ddr_size
+= gd
->bd
->bi_dram
[i
].size
;
509 print_size(ddr_size
, "");
513 #if defined(CONFIG_ARCH_MISC_INIT)
514 int arch_misc_init(void)
522 #ifdef CONFIG_FSL_MC_ENET
523 extern int fdt_fixup_board_phy(void *fdt
);
525 void fdt_fixup_board_enet(void *fdt
)
529 offset
= fdt_path_offset(fdt
, "/soc/fsl-mc");
532 offset
= fdt_path_offset(fdt
, "/fsl-mc");
535 printf("%s: fsl-mc node not found in device tree (error %d)\n",
540 if (get_mc_boot_status() == 0 &&
541 (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) {
542 fdt_status_okay(fdt
, offset
);
543 fdt_fixup_board_phy(fdt
);
545 fdt_status_fail(fdt
, offset
);
549 void board_quiesce_devices(void)
551 fsl_mc_ldpaa_exit(gd
->bd
);
555 #ifdef CONFIG_OF_BOARD_SETUP
557 int ft_board_setup(void *blob
, bd_t
*bd
)
560 u16 mc_memory_bank
= 0;
564 u64 mc_memory_base
= 0;
565 u64 mc_memory_size
= 0;
566 u16 total_memory_banks
;
568 ft_cpu_setup(blob
, bd
);
570 fdt_fixup_mc_ddr(&mc_memory_base
, &mc_memory_size
);
572 if (mc_memory_base
!= 0)
575 total_memory_banks
= CONFIG_NR_DRAM_BANKS
+ mc_memory_bank
;
577 base
= calloc(total_memory_banks
, sizeof(u64
));
578 size
= calloc(total_memory_banks
, sizeof(u64
));
580 /* fixup DT for the three GPP DDR banks */
581 for (i
= 0; i
< CONFIG_NR_DRAM_BANKS
; i
++) {
582 base
[i
] = gd
->bd
->bi_dram
[i
].start
;
583 size
[i
] = gd
->bd
->bi_dram
[i
].size
;
586 #ifdef CONFIG_RESV_RAM
587 /* reduce size if reserved memory is within this bank */
588 if (gd
->arch
.resv_ram
>= base
[0] &&
589 gd
->arch
.resv_ram
< base
[0] + size
[0])
590 size
[0] = gd
->arch
.resv_ram
- base
[0];
591 else if (gd
->arch
.resv_ram
>= base
[1] &&
592 gd
->arch
.resv_ram
< base
[1] + size
[1])
593 size
[1] = gd
->arch
.resv_ram
- base
[1];
594 else if (gd
->arch
.resv_ram
>= base
[2] &&
595 gd
->arch
.resv_ram
< base
[2] + size
[2])
596 size
[2] = gd
->arch
.resv_ram
- base
[2];
599 if (mc_memory_base
!= 0) {
600 for (i
= 0; i
<= total_memory_banks
; i
++) {
601 if (base
[i
] == 0 && size
[i
] == 0) {
602 base
[i
] = mc_memory_base
;
603 size
[i
] = mc_memory_size
;
609 fdt_fixup_memory_banks(blob
, base
, size
, total_memory_banks
);
612 fsl_fdt_fixup_dr_usb(blob
, bd
);
615 #ifdef CONFIG_FSL_MC_ENET
616 fdt_fsl_mc_fixup_iommu_map_entry(blob
);
617 fdt_fixup_board_enet(blob
);
624 void qixis_dump_switch(void)
628 QIXIS_WRITE(cms
[0], 0x00);
629 nr_of_cfgsw
= QIXIS_READ(cms
[1]);
631 puts("DIP switch settings dump:\n");
632 for (i
= 1; i
<= nr_of_cfgsw
; i
++) {
633 QIXIS_WRITE(cms
[0], i
);
634 printf("SW%d = (0x%02x)\n", i
, QIXIS_READ(cms
[1]));