1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
8 #include <dm/platform_data/serial_pl01x.h>
16 #include <fdt_support.h>
17 #include <linux/libfdt.h>
18 #include <fsl-mc/fsl_mc.h>
19 #include <env_internal.h>
20 #include <efi_loader.h>
21 #include <asm/arch/mmu.h>
23 #include <asm/arch/fsl_serdes.h>
24 #include <asm/arch/soc.h>
25 #include "../common/qixis.h"
26 #include "../common/vid.h"
27 #include <fsl_immap.h>
30 #include "../common/emc2305.h"
33 #ifdef CONFIG_TARGET_LX2160AQDS
34 #define CFG_MUX_I2C_SDHC(reg, value) ((reg & 0x3f) | value)
35 #define SET_CFG_MUX1_SDHC1_SDHC(reg) (reg & 0x3f)
36 #define SET_CFG_MUX2_SDHC1_SPI(reg, value) ((reg & 0xcf) | value)
37 #define SET_CFG_MUX3_SDHC1_SPI(reg, value) ((reg & 0xf8) | value)
38 #define SET_CFG_MUX_SDHC2_DSPI(reg, value) ((reg & 0xf8) | value)
39 #define SET_CFG_MUX1_SDHC1_DSPI(reg, value) ((reg & 0x3f) | value)
40 #define SDHC1_BASE_PMUX_DSPI 2
41 #define SDHC2_BASE_PMUX_DSPI 2
42 #define IIC5_PMUX_SPI3 3
43 #endif /* CONFIG_TARGET_LX2160AQDS */
45 DECLARE_GLOBAL_DATA_PTR
;
47 static struct pl01x_serial_platdata serial0
= {
48 #if CONFIG_CONS_INDEX == 0
49 .base
= CONFIG_SYS_SERIAL0
,
50 #elif CONFIG_CONS_INDEX == 1
51 .base
= CONFIG_SYS_SERIAL1
,
53 #error "Unsupported console index value."
58 U_BOOT_DEVICE(nxp_serial0
) = {
59 .name
= "serial_pl01x",
63 static struct pl01x_serial_platdata serial1
= {
64 .base
= CONFIG_SYS_SERIAL1
,
68 U_BOOT_DEVICE(nxp_serial1
) = {
69 .name
= "serial_pl01x",
73 int select_i2c_ch_pca9547(u8 ch
)
77 ret
= i2c_write(I2C_MUX_PCA_ADDR_PRI
, 0, 1, &ch
, 1);
79 puts("PCA: failed to select proper channel\n");
86 static void uart_get_clock(void)
88 serial0
.clock
= get_serial_clock();
89 serial1
.clock
= get_serial_clock();
92 int board_early_init_f(void)
94 #ifdef CONFIG_SYS_I2C_EARLY_INIT
97 /* get required clock for UART IP */
100 #ifdef CONFIG_EMC2305
101 select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305
);
103 set_fan_speed(I2C_EMC2305_PWM
);
104 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT
);
107 fsl_lsch3_early_init_f();
111 #if defined(CONFIG_TARGET_LX2160AQDS)
112 void esdhc_dspi_status_fixup(void *blob
)
114 const char esdhc0_path
[] = "/soc/esdhc@2140000";
115 const char esdhc1_path
[] = "/soc/esdhc@2150000";
116 const char dspi0_path
[] = "/soc/dspi@2100000";
117 const char dspi1_path
[] = "/soc/dspi@2110000";
118 const char dspi2_path
[] = "/soc/dspi@2120000";
120 struct ccsr_gur __iomem
*gur
= (void *)(CONFIG_SYS_FSL_GUTS_ADDR
);
125 /* Check RCW field sdhc1_base_pmux to enable/disable
126 * esdhc0/dspi0 DT node
128 sdhc1_base_pmux
= gur_in32(&gur
->rcwsr
[FSL_CHASSIS3_RCWSR12_REGSR
- 1])
129 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK
;
130 sdhc1_base_pmux
>>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT
;
132 if (sdhc1_base_pmux
== SDHC1_BASE_PMUX_DSPI
) {
133 do_fixup_by_path(blob
, dspi0_path
, "status", "okay",
135 do_fixup_by_path(blob
, esdhc0_path
, "status", "disabled",
136 sizeof("disabled"), 1);
138 do_fixup_by_path(blob
, esdhc0_path
, "status", "okay",
140 do_fixup_by_path(blob
, dspi0_path
, "status", "disabled",
141 sizeof("disabled"), 1);
144 /* Check RCW field sdhc2_base_pmux to enable/disable
145 * esdhc1/dspi1 DT node
147 sdhc2_base_pmux
= gur_in32(&gur
->rcwsr
[FSL_CHASSIS3_RCWSR13_REGSR
- 1])
148 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK
;
149 sdhc2_base_pmux
>>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT
;
151 if (sdhc2_base_pmux
== SDHC2_BASE_PMUX_DSPI
) {
152 do_fixup_by_path(blob
, dspi1_path
, "status", "okay",
154 do_fixup_by_path(blob
, esdhc1_path
, "status", "disabled",
155 sizeof("disabled"), 1);
157 do_fixup_by_path(blob
, esdhc1_path
, "status", "okay",
159 do_fixup_by_path(blob
, dspi1_path
, "status", "disabled",
160 sizeof("disabled"), 1);
163 /* Check RCW field IIC5 to enable dspi2 DT node */
164 iic5_pmux
= gur_in32(&gur
->rcwsr
[FSL_CHASSIS3_RCWSR12_REGSR
- 1])
165 & FSL_CHASSIS3_IIC5_PMUX_MASK
;
166 iic5_pmux
>>= FSL_CHASSIS3_IIC5_PMUX_SHIFT
;
168 if (iic5_pmux
== IIC5_PMUX_SPI3
) {
169 do_fixup_by_path(blob
, dspi2_path
, "status", "okay",
175 int esdhc_status_fixup(void *blob
, const char *compat
)
177 #if defined(CONFIG_TARGET_LX2160AQDS)
178 /* Enable esdhc and dspi DT nodes based on RCW fields */
179 esdhc_dspi_status_fixup(blob
);
181 /* Enable both esdhc DT nodes for LX2160ARDB */
182 do_fixup_by_compat(blob
, compat
, "status", "okay",
188 #if defined(CONFIG_VID)
189 int i2c_multiplexer_select_vid_channel(u8 channel
)
191 return select_i2c_ch_pca9547(channel
);
194 int init_func_vid(void)
196 if (adjust_vdd(0) < 0)
197 printf("core voltage not adjusted\n");
205 enum boot_src src
= get_boot_src();
208 #ifdef CONFIG_TARGET_LX2160AQDS
210 static const char *const freq
[] = {"100", "125", "156.25",
211 "161.13", "322.26", "", "", "",
212 "", "", "", "", "", "", "",
213 "100 separate SSCG"};
217 #ifdef CONFIG_TARGET_LX2160AQDS
218 printf("Board: %s-QDS, ", buf
);
220 printf("Board: %s-RDB, ", buf
);
223 sw
= QIXIS_READ(arch
);
224 printf("Board version: %c, boot from ", (sw
& 0xf) - 1 + 'A');
226 if (src
== BOOT_SOURCE_SD_MMC
) {
229 sw
= QIXIS_READ(brdcfg
[0]);
230 sw
= (sw
>> QIXIS_XMAP_SHIFT
) & QIXIS_XMAP_MASK
;
234 puts("FlexSPI DEV#0\n");
237 puts("FlexSPI DEV#1\n");
241 puts("FlexSPI EMU\n");
244 printf("invalid setting, xmap: %d\n", sw
);
248 #ifdef CONFIG_TARGET_LX2160AQDS
249 printf("FPGA: v%d (%s), build %d",
250 (int)QIXIS_READ(scver
), qixis_read_tag(buf
),
251 (int)qixis_read_minor());
252 /* the timestamp string contains "\n" at the end */
253 printf(" on %s", qixis_read_time(buf
));
255 puts("SERDES1 Reference : ");
256 sw
= QIXIS_READ(brdcfg
[2]);
258 printf("Clock1 = %sMHz ", freq
[clock
]);
260 printf("Clock2 = %sMHz", freq
[clock
]);
262 sw
= QIXIS_READ(brdcfg
[3]);
263 puts("\nSERDES2 Reference : ");
265 printf("Clock1 = %sMHz ", freq
[clock
]);
267 printf("Clock2 = %sMHz", freq
[clock
]);
269 sw
= QIXIS_READ(brdcfg
[12]);
270 puts("\nSERDES3 Reference : ");
272 printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq
[clock
], freq
[clock
]);
274 printf("FPGA: v%d.%d\n", QIXIS_READ(scver
), QIXIS_READ(tagdata
));
276 puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
277 puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
278 puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100Hz\n");
283 #ifdef CONFIG_TARGET_LX2160AQDS
285 * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
287 u8
qixis_esdhc_detect_quirk(void)
289 /* for LX2160AQDS res1[1] @ offset 0x1A is SDHC1 Control/Status (SDHC1)
291 * Specifies the type of card installed in the SDHC1 adapter slot.
293 * 001= eMMC V4.5 adapter is installed.
294 * 010= SD/MMC 3.3V adapter is installed.
295 * 011= eMMC V4.4 adapter is installed.
296 * 100= eMMC V5.0 adapter is installed.
297 * 101= MMC card/Legacy (3.3V) adapter is installed.
298 * 110= SDCard V2/V3 adapter installed.
299 * 111= no adapter is installed.
301 return ((QIXIS_READ(res1
[1]) & QIXIS_SDID_MASK
) !=
302 QIXIS_ESDHC_NO_ADAPTER
);
305 int config_board_mux(void)
307 u8 reg11
, reg5
, reg13
;
308 struct ccsr_gur __iomem
*gur
= (void *)(CONFIG_SYS_FSL_GUTS_ADDR
);
313 /* Routes {I2C2_SCL, I2C2_SDA} to SDHC1 as {SDHC1_CD_B, SDHC1_WP}.
314 * Routes {I2C3_SCL, I2C3_SDA} to CAN transceiver as {CAN1_TX,CAN1_RX}.
315 * Routes {I2C4_SCL, I2C4_SDA} to CAN transceiver as {CAN2_TX,CAN2_RX}.
316 * Qixis and remote systems are isolated from the I2C1 bus.
317 * Processor connections are still available.
318 * SPI2 CS2_B controls EN25S64 SPI memory device.
319 * SPI3 CS2_B controls EN25S64 SPI memory device.
320 * EC2 connects to PHY #2 using RGMII protocol.
321 * CLK_OUT connects to FPGA for clock measurement.
324 reg5
= QIXIS_READ(brdcfg
[5]);
325 reg5
= CFG_MUX_I2C_SDHC(reg5
, 0x40);
326 QIXIS_WRITE(brdcfg
[5], reg5
);
328 /* Check RCW field sdhc1_base_pmux
329 * esdhc0 : sdhc1_base_pmux = 0
330 * dspi0 : sdhc1_base_pmux = 2
332 sdhc1_base_pmux
= gur_in32(&gur
->rcwsr
[FSL_CHASSIS3_RCWSR12_REGSR
- 1])
333 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK
;
334 sdhc1_base_pmux
>>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT
;
336 if (sdhc1_base_pmux
== SDHC1_BASE_PMUX_DSPI
) {
337 reg11
= QIXIS_READ(brdcfg
[11]);
338 reg11
= SET_CFG_MUX1_SDHC1_DSPI(reg11
, 0x40);
339 QIXIS_WRITE(brdcfg
[11], reg11
);
341 /* - Routes {SDHC1_CMD, SDHC1_CLK } to SDHC1 adapter slot.
342 * {SDHC1_DAT3, SDHC1_DAT2} to SDHC1 adapter slot.
343 * {SDHC1_DAT1, SDHC1_DAT0} to SDHC1 adapter slot.
345 reg11
= QIXIS_READ(brdcfg
[11]);
346 reg11
= SET_CFG_MUX1_SDHC1_SDHC(reg11
);
347 QIXIS_WRITE(brdcfg
[11], reg11
);
350 /* Check RCW field sdhc2_base_pmux
351 * esdhc1 : sdhc2_base_pmux = 0 (default)
352 * dspi1 : sdhc2_base_pmux = 2
354 sdhc2_base_pmux
= gur_in32(&gur
->rcwsr
[FSL_CHASSIS3_RCWSR13_REGSR
- 1])
355 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK
;
356 sdhc2_base_pmux
>>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT
;
358 if (sdhc2_base_pmux
== SDHC2_BASE_PMUX_DSPI
) {
359 reg13
= QIXIS_READ(brdcfg
[13]);
360 reg13
= SET_CFG_MUX_SDHC2_DSPI(reg13
, 0x01);
361 QIXIS_WRITE(brdcfg
[13], reg13
);
363 reg13
= QIXIS_READ(brdcfg
[13]);
364 reg13
= SET_CFG_MUX_SDHC2_DSPI(reg13
, 0x00);
365 QIXIS_WRITE(brdcfg
[13], reg13
);
368 /* Check RCW field IIC5 to enable dspi2 DT nodei
371 iic5_pmux
= gur_in32(&gur
->rcwsr
[FSL_CHASSIS3_RCWSR12_REGSR
- 1])
372 & FSL_CHASSIS3_IIC5_PMUX_MASK
;
373 iic5_pmux
>>= FSL_CHASSIS3_IIC5_PMUX_SHIFT
;
375 if (iic5_pmux
== IIC5_PMUX_SPI3
) {
376 /* - Routes {SDHC1_DAT4} to SPI3 devices as {SPI3_M_CS0_B}. */
377 reg11
= QIXIS_READ(brdcfg
[11]);
378 reg11
= SET_CFG_MUX2_SDHC1_SPI(reg11
, 0x10);
379 QIXIS_WRITE(brdcfg
[11], reg11
);
381 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} nowhere.
382 * {SDHC1_DAT7, SDHC1_DS } to {nothing, SPI3_M0_CLK }.
383 * {I2C5_SCL, I2C5_SDA } to {SPI3_M0_MOSI, SPI3_M0_MISO}.
385 reg11
= QIXIS_READ(brdcfg
[11]);
386 reg11
= SET_CFG_MUX3_SDHC1_SPI(reg11
, 0x01);
387 QIXIS_WRITE(brdcfg
[11], reg11
);
389 /* Routes {SDHC1_DAT4} to SDHC1 adapter slot */
390 reg11
= QIXIS_READ(brdcfg
[11]);
391 reg11
= SET_CFG_MUX2_SDHC1_SPI(reg11
, 0x00);
392 QIXIS_WRITE(brdcfg
[11], reg11
);
394 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot.
395 * {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot.
396 * {I2C5_SCL, I2C5_SDA } to SDHC1 adapter slot.
398 reg11
= QIXIS_READ(brdcfg
[11]);
399 reg11
= SET_CFG_MUX3_SDHC1_SPI(reg11
, 0x00);
400 QIXIS_WRITE(brdcfg
[11], reg11
);
406 int config_board_mux(void)
412 unsigned long get_board_sys_clk(void)
414 #ifdef CONFIG_TARGET_LX2160AQDS
415 u8 sysclk_conf
= QIXIS_READ(brdcfg
[1]);
417 switch (sysclk_conf
& 0x03) {
418 case QIXIS_SYSCLK_100
:
420 case QIXIS_SYSCLK_125
:
422 case QIXIS_SYSCLK_133
:
431 unsigned long get_board_ddr_clk(void)
433 #ifdef CONFIG_TARGET_LX2160AQDS
434 u8 ddrclk_conf
= QIXIS_READ(brdcfg
[1]);
436 switch ((ddrclk_conf
& 0x30) >> 4) {
437 case QIXIS_DDRCLK_100
:
439 case QIXIS_DDRCLK_125
:
441 case QIXIS_DDRCLK_133
:
452 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
453 u32 __iomem
*irq_ccsr
= (u32 __iomem
*)ISC_BASE
;
455 #ifdef CONFIG_ENV_IS_NOWHERE
456 gd
->env_addr
= (ulong
)&default_environment
[0];
459 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT
);
461 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
462 /* invert AQR107 IRQ pins polarity */
463 out_le32(irq_ccsr
+ IRQCR_OFFSET
/ 4, AQR107_IRQ_MASK
);
466 #ifdef CONFIG_FSL_CAAM
473 void detail_board_ddr_info(void)
479 for (i
= 0; i
< CONFIG_NR_DRAM_BANKS
; i
++)
480 ddr_size
+= gd
->bd
->bi_dram
[i
].size
;
481 print_size(ddr_size
, "");
485 #if defined(CONFIG_ARCH_MISC_INIT)
486 int arch_misc_init(void)
494 #ifdef CONFIG_FSL_MC_ENET
495 extern int fdt_fixup_board_phy(void *fdt
);
497 void fdt_fixup_board_enet(void *fdt
)
501 offset
= fdt_path_offset(fdt
, "/soc/fsl-mc");
504 offset
= fdt_path_offset(fdt
, "/fsl-mc");
507 printf("%s: fsl-mc node not found in device tree (error %d)\n",
512 if (get_mc_boot_status() == 0 &&
513 (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) {
514 fdt_status_okay(fdt
, offset
);
515 fdt_fixup_board_phy(fdt
);
517 fdt_status_fail(fdt
, offset
);
521 void board_quiesce_devices(void)
523 fsl_mc_ldpaa_exit(gd
->bd
);
527 #ifdef CONFIG_OF_BOARD_SETUP
529 int ft_board_setup(void *blob
, bd_t
*bd
)
532 u64 base
[CONFIG_NR_DRAM_BANKS
];
533 u64 size
[CONFIG_NR_DRAM_BANKS
];
535 ft_cpu_setup(blob
, bd
);
537 /* fixup DT for the three GPP DDR banks */
538 for (i
= 0; i
< CONFIG_NR_DRAM_BANKS
; i
++) {
539 base
[i
] = gd
->bd
->bi_dram
[i
].start
;
540 size
[i
] = gd
->bd
->bi_dram
[i
].size
;
543 #ifdef CONFIG_RESV_RAM
544 /* reduce size if reserved memory is within this bank */
545 if (gd
->arch
.resv_ram
>= base
[0] &&
546 gd
->arch
.resv_ram
< base
[0] + size
[0])
547 size
[0] = gd
->arch
.resv_ram
- base
[0];
548 else if (gd
->arch
.resv_ram
>= base
[1] &&
549 gd
->arch
.resv_ram
< base
[1] + size
[1])
550 size
[1] = gd
->arch
.resv_ram
- base
[1];
551 else if (gd
->arch
.resv_ram
>= base
[2] &&
552 gd
->arch
.resv_ram
< base
[2] + size
[2])
553 size
[2] = gd
->arch
.resv_ram
- base
[2];
556 fdt_fixup_memory_banks(blob
, base
, size
, CONFIG_NR_DRAM_BANKS
);
559 fsl_fdt_fixup_dr_usb(blob
, bd
);
562 #ifdef CONFIG_FSL_MC_ENET
563 fdt_fsl_mc_fixup_iommu_map_entry(blob
);
564 fdt_fixup_board_enet(blob
);
571 void qixis_dump_switch(void)
575 QIXIS_WRITE(cms
[0], 0x00);
576 nr_of_cfgsw
= QIXIS_READ(cms
[1]);
578 puts("DIP switch settings dump:\n");
579 for (i
= 1; i
<= nr_of_cfgsw
; i
++) {
580 QIXIS_WRITE(cms
[0], i
);
581 printf("SW%d = (0x%02x)\n", i
, QIXIS_READ(cms
[1]));