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configs: Disable now unbuildable SPI options for boards
[thirdparty/u-boot.git] / board / renesas / sh7757lcr / sh7757lcr.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2011 Renesas Solutions Corp.
4 */
5
6 #include <common.h>
7 #include <environment.h>
8 #include <malloc.h>
9 #include <asm/processor.h>
10 #include <asm/io.h>
11 #include <asm/mmc.h>
12 #include <spi.h>
13 #include <spi_flash.h>
14
15 int checkboard(void)
16 {
17 puts("BOARD: R0P7757LC0030RL board\n");
18
19 return 0;
20 }
21
22 static void init_gctrl(void)
23 {
24 struct gctrl_regs *gctrl = GCTRL_BASE;
25 unsigned long graofst;
26
27 graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
28 writel(graofst | 0x20000f00, &gctrl->gracr3);
29 }
30
31 static int init_pcie_bridge_from_spi(void *buf, size_t size)
32 {
33 #ifdef CONFIG_DEPRECATED
34 struct spi_flash *spi;
35 int ret;
36 unsigned long pcie_addr;
37
38 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
39 if (!spi) {
40 printf("%s: spi_flash probe error.\n", __func__);
41 return 1;
42 }
43
44 if (is_sh7757_b0())
45 pcie_addr = SH7757LCR_PCIEBRG_ADDR_B0;
46 else
47 pcie_addr = SH7757LCR_PCIEBRG_ADDR;
48
49 ret = spi_flash_read(spi, pcie_addr, size, buf);
50 if (ret) {
51 printf("%s: spi_flash read error.\n", __func__);
52 spi_flash_free(spi);
53 return 1;
54 }
55 spi_flash_free(spi);
56
57 return 0;
58 #else
59 printf("No SPI support so no PCIe support\n");
60 return 1;
61 #endif
62 }
63
64 static void init_pcie_bridge(void)
65 {
66 struct pciebrg_regs *pciebrg = PCIEBRG_BASE;
67 struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
68 int i;
69 unsigned char *data;
70 unsigned short tmp;
71 unsigned long pcie_size;
72
73 if (!(readw(&pciebrg->ctrl_h8s) & 0x0001))
74 return;
75
76 if (is_sh7757_b0())
77 pcie_size = SH7757LCR_PCIEBRG_SIZE_B0;
78 else
79 pcie_size = SH7757LCR_PCIEBRG_SIZE;
80
81 data = malloc(pcie_size);
82 if (!data) {
83 printf("%s: malloc error.\n", __func__);
84 return;
85 }
86 if (init_pcie_bridge_from_spi(data, pcie_size)) {
87 free(data);
88 return;
89 }
90
91 if (data[0] == 0xff && data[1] == 0xff && data[2] == 0xff &&
92 data[3] == 0xff) {
93 free(data);
94 printf("%s: skipped initialization\n", __func__);
95 return;
96 }
97
98 writew(0xa501, &pciebrg->ctrl_h8s); /* reset */
99 writew(0x0000, &pciebrg->cp_ctrl);
100 writew(0x0000, &pciebrg->cp_addr);
101
102 for (i = 0; i < pcie_size; i += 2) {
103 tmp = (data[i] << 8) | data[i + 1];
104 writew(tmp, &pciebrg->cp_data);
105 }
106
107 writew(0xa500, &pciebrg->ctrl_h8s); /* start */
108 if (!is_sh7757_b0())
109 writel(0x00000001, &pcie_setup->pbictl3);
110
111 free(data);
112 }
113
114 static void init_usb_phy(void)
115 {
116 struct usb_common_regs *common0 = USB0_COMMON_BASE;
117 struct usb_common_regs *common1 = USB1_COMMON_BASE;
118 struct usb0_phy_regs *phy = USB0_PHY_BASE;
119 struct usb1_port_regs *port = USB1_PORT_BASE;
120 struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
121
122 writew(0x0100, &phy->reset); /* set reset */
123 /* port0 = USB0, port1 = USB1 */
124 writew(0x0002, &phy->portsel);
125 writel(0x0001, &port->port1sel); /* port1 = Host */
126 writew(0x0111, &phy->reset); /* clear reset */
127
128 writew(0x4000, &common0->suspmode);
129 writew(0x4000, &common1->suspmode);
130
131 #if defined(__LITTLE_ENDIAN)
132 writel(0x00000000, &align->ehcidatac);
133 writel(0x00000000, &align->ohcidatac);
134 #endif
135 }
136
137 static void set_mac_to_sh_eth_register(int channel, char *mac_string)
138 {
139 struct ether_mac_regs *ether;
140 unsigned char mac[6];
141 unsigned long val;
142
143 eth_parse_enetaddr(mac_string, mac);
144
145 if (!channel)
146 ether = ETHER0_MAC_BASE;
147 else
148 ether = ETHER1_MAC_BASE;
149
150 val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
151 writel(val, &ether->mahr);
152 val = (mac[4] << 8) | mac[5];
153 writel(val, &ether->malr);
154 }
155
156 static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
157 {
158 struct ether_mac_regs *ether;
159 unsigned char mac[6];
160 unsigned long val;
161
162 eth_parse_enetaddr(mac_string, mac);
163
164 if (!channel)
165 ether = GETHER0_MAC_BASE;
166 else
167 ether = GETHER1_MAC_BASE;
168
169 val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
170 writel(val, &ether->mahr);
171 val = (mac[4] << 8) | mac[5];
172 writel(val, &ether->malr);
173 }
174
175 /*****************************************************************
176 * This PMB must be set on this timing. The lowlevel_init is run on
177 * Area 0(phys 0x00000000), so we have to map it.
178 *
179 * The new PMB table is following:
180 * ent virt phys v sz c wt
181 * 0 0xa0000000 0x40000000 1 128M 0 1
182 * 1 0xa8000000 0x48000000 1 128M 0 1
183 * 2 0xb0000000 0x50000000 1 128M 0 1
184 * 3 0xb8000000 0x58000000 1 128M 0 1
185 * 4 0x80000000 0x40000000 1 128M 1 1
186 * 5 0x88000000 0x48000000 1 128M 1 1
187 * 6 0x90000000 0x50000000 1 128M 1 1
188 * 7 0x98000000 0x58000000 1 128M 1 1
189 */
190 static void set_pmb_on_board_init(void)
191 {
192 struct mmu_regs *mmu = MMU_BASE;
193
194 /* clear ITLB */
195 writel(0x00000004, &mmu->mmucr);
196
197 /* delete PMB for SPIBOOT */
198 writel(0, PMB_ADDR_BASE(0));
199 writel(0, PMB_DATA_BASE(0));
200
201 /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
202 /* ppn ub v s1 s0 c wt */
203 writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
204 writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
205 writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
206 writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
207 writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
208 writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
209 writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
210 writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
211 writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
212 writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
213 writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
214 writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
215 }
216
217 int board_init(void)
218 {
219 struct gether_control_regs *gether = GETHER_CONTROL_BASE;
220
221 set_pmb_on_board_init();
222
223 /* enable RMII's MDIO (disable GRMII's MDIO) */
224 writel(0x00030000, &gether->gbecont);
225
226 init_gctrl();
227 init_usb_phy();
228
229 return 0;
230 }
231
232 int board_mmc_init(bd_t *bis)
233 {
234 return mmcif_mmc_init();
235 }
236
237 static int get_sh_eth_mac_raw(unsigned char *buf, int size)
238 {
239 #ifdef CONFIG_DEPRECATED
240 struct spi_flash *spi;
241 int ret;
242
243 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
244 if (spi == NULL) {
245 printf("%s: spi_flash probe error.\n", __func__);
246 return 1;
247 }
248
249 ret = spi_flash_read(spi, SH7757LCR_ETHERNET_MAC_BASE, size, buf);
250 if (ret) {
251 printf("%s: spi_flash read error.\n", __func__);
252 spi_flash_free(spi);
253 return 1;
254 }
255 spi_flash_free(spi);
256 #endif
257
258 return 0;
259 }
260
261 static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
262 {
263 memcpy(mac_string, &buf[channel * (SH7757LCR_ETHERNET_MAC_SIZE + 1)],
264 SH7757LCR_ETHERNET_MAC_SIZE);
265 mac_string[SH7757LCR_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
266
267 return 0;
268 }
269
270 static void init_ethernet_mac(void)
271 {
272 char mac_string[64];
273 char env_string[64];
274 int i;
275 unsigned char *buf;
276
277 buf = malloc(256);
278 if (!buf) {
279 printf("%s: malloc error.\n", __func__);
280 return;
281 }
282 get_sh_eth_mac_raw(buf, 256);
283
284 /* Fast Ethernet */
285 for (i = 0; i < SH7757LCR_ETHERNET_NUM_CH; i++) {
286 get_sh_eth_mac(i, mac_string, buf);
287 if (i == 0)
288 env_set("ethaddr", mac_string);
289 else {
290 sprintf(env_string, "eth%daddr", i);
291 env_set(env_string, mac_string);
292 }
293
294 set_mac_to_sh_eth_register(i, mac_string);
295 }
296
297 /* Gigabit Ethernet */
298 for (i = 0; i < SH7757LCR_GIGA_ETHERNET_NUM_CH; i++) {
299 get_sh_eth_mac(i + SH7757LCR_ETHERNET_NUM_CH, mac_string, buf);
300 sprintf(env_string, "eth%daddr", i + SH7757LCR_ETHERNET_NUM_CH);
301 env_set(env_string, mac_string);
302
303 set_mac_to_sh_giga_eth_register(i, mac_string);
304 }
305
306 free(buf);
307 }
308
309 static void init_pcie(void)
310 {
311 struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
312 struct pcie_system_bus_regs *pcie_sysbus = PCIE_SYSTEM_BUS_BASE;
313
314 writel(0x00000ff2, &pcie_setup->ladmsk0);
315 writel(0x00000001, &pcie_setup->barmap);
316 writel(0xffcaa000, &pcie_setup->lad0);
317 writel(0x00030000, &pcie_sysbus->endictl0);
318 writel(0x00000003, &pcie_sysbus->endictl1);
319 writel(0x00000004, &pcie_setup->pbictl2);
320 }
321
322 static void finish_spiboot(void)
323 {
324 struct gctrl_regs *gctrl = GCTRL_BASE;
325 /*
326 * SH7757 B0 does not use LBSC.
327 * So if we set SPIBOOTCAN to 1, SH7757 can not access Area0.
328 * This setting is not cleared by manual reset, So we have to set it
329 * to 0.
330 */
331 writel(0x00000000, &gctrl->spibootcan);
332 }
333
334 int board_late_init(void)
335 {
336 init_ethernet_mac();
337 init_pcie_bridge();
338 init_pcie();
339 finish_spiboot();
340
341 return 0;
342 }
343
344 int do_sh_g200(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
345 {
346 struct gctrl_regs *gctrl = GCTRL_BASE;
347 unsigned long graofst;
348
349 writel(0xfedcba98, &gctrl->wprotect);
350 graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
351 writel(graofst | 0xa0000f00, &gctrl->gracr3);
352
353 return 0;
354 }
355
356 U_BOOT_CMD(
357 sh_g200, 1, 1, do_sh_g200,
358 "enable sh-g200",
359 "enable SH-G200 bus (disable PCIe-G200)"
360 );
361
362 #ifdef CONFIG_DEPRECATED
363 int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
364 {
365 int i, ret;
366 char mac_string[256];
367 struct spi_flash *spi;
368 unsigned char *buf;
369
370 if (argc != 5) {
371 buf = malloc(256);
372 if (!buf) {
373 printf("%s: malloc error.\n", __func__);
374 return 1;
375 }
376
377 get_sh_eth_mac_raw(buf, 256);
378
379 /* print current MAC address */
380 for (i = 0; i < 4; i++) {
381 get_sh_eth_mac(i, mac_string, buf);
382 if (i < 2)
383 printf(" ETHERC ch%d = %s\n", i, mac_string);
384 else
385 printf("GETHERC ch%d = %s\n", i-2, mac_string);
386 }
387 free(buf);
388 return 0;
389 }
390
391 /* new setting */
392 memset(mac_string, 0xff, sizeof(mac_string));
393 sprintf(mac_string, "%s\t%s\t%s\t%s",
394 argv[1], argv[2], argv[3], argv[4]);
395
396 /* write MAC data to SPI rom */
397 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
398 if (!spi) {
399 printf("%s: spi_flash probe error.\n", __func__);
400 return 1;
401 }
402
403 ret = spi_flash_erase(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
404 SH7757LCR_SPI_SECTOR_SIZE);
405 if (ret) {
406 printf("%s: spi_flash erase error.\n", __func__);
407 return 1;
408 }
409
410 ret = spi_flash_write(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
411 sizeof(mac_string), mac_string);
412 if (ret) {
413 printf("%s: spi_flash write error.\n", __func__);
414 spi_flash_free(spi);
415 return 1;
416 }
417 spi_flash_free(spi);
418
419 puts("The writing of the MAC address to SPI ROM was completed.\n");
420
421 return 0;
422 }
423
424 U_BOOT_CMD(
425 write_mac, 5, 1, do_write_mac,
426 "write MAC address for ETHERC/GETHERC",
427 "[ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1]\n"
428 );
429 #endif
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