1 // SPDX-License-Identifier: GPL-2.0+
5 * Board functions for TI AM335X based boards
7 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
21 #include <asm/arch/cpu.h>
22 #include <asm/arch/hardware.h>
23 #include <asm/arch/omap.h>
24 #include <asm/arch/ddr_defs.h>
25 #include <asm/arch/clock.h>
26 #include <asm/arch/clk_synthesizer.h>
27 #include <asm/arch/gpio.h>
28 #include <asm/arch/mmc_host_def.h>
29 #include <asm/arch/sys_proto.h>
30 #include <asm/arch/mem.h>
31 #include <asm/global_data.h>
35 #include <asm/omap_common.h>
36 #include <asm/omap_mmc.h>
40 #include <linux/bitops.h>
41 #include <linux/compiler.h>
42 #include <linux/delay.h>
43 #include <power/tps65217.h>
44 #include <power/tps65910.h>
45 #include <env_internal.h>
47 #include "../common/board_detect.h"
48 #include "../common/cape_detect.h"
51 DECLARE_GLOBAL_DATA_PTR
;
53 /* GPIO that controls power to DDR on EVM-SK */
54 #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
55 #define GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 7)
56 #define ICE_GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 18)
57 #define GPIO_PR1_MII_CTRL GPIO_TO_PIN(3, 4)
58 #define GPIO_MUX_MII_CTRL GPIO_TO_PIN(3, 10)
59 #define GPIO_FET_SWITCH_CTRL GPIO_TO_PIN(0, 7)
60 #define GPIO_PHY_RESET GPIO_TO_PIN(2, 5)
61 #define GPIO_ETH0_MODE GPIO_TO_PIN(0, 11)
62 #define GPIO_ETH1_MODE GPIO_TO_PIN(1, 26)
64 static struct ctrl_dev
*cdev
= (struct ctrl_dev
*)CTRL_DEVICE_BASE
;
66 #define GPIO0_RISINGDETECT (AM33XX_GPIO0_BASE + OMAP_GPIO_RISINGDETECT)
67 #define GPIO1_RISINGDETECT (AM33XX_GPIO1_BASE + OMAP_GPIO_RISINGDETECT)
69 #define GPIO0_IRQSTATUS1 (AM33XX_GPIO0_BASE + OMAP_GPIO_IRQSTATUS1)
70 #define GPIO1_IRQSTATUS1 (AM33XX_GPIO1_BASE + OMAP_GPIO_IRQSTATUS1)
72 #define GPIO0_IRQSTATUSRAW (AM33XX_GPIO0_BASE + 0x024)
73 #define GPIO1_IRQSTATUSRAW (AM33XX_GPIO1_BASE + 0x024)
76 * Read header information from EEPROM into global structure.
78 #ifdef CONFIG_TI_I2C_BOARD_DETECT
79 void do_board_detect(void)
81 enable_i2c0_pin_mux();
82 enable_i2c2_pin_mux();
83 if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS
,
84 CONFIG_EEPROM_CHIP_ADDRESS
))
85 printf("ti_i2c_eeprom_init failed\n");
89 #ifndef CONFIG_DM_SERIAL
90 struct serial_device
*default_serial_console(void)
93 return &eserial4_device
;
95 return &eserial1_device
;
99 #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
100 static const struct ddr_data ddr2_data
= {
101 .datardsratio0
= MT47H128M16RT25E_RD_DQS
,
102 .datafwsratio0
= MT47H128M16RT25E_PHY_FIFO_WE
,
103 .datawrsratio0
= MT47H128M16RT25E_PHY_WR_DATA
,
106 static const struct cmd_control ddr2_cmd_ctrl_data
= {
107 .cmd0csratio
= MT47H128M16RT25E_RATIO
,
109 .cmd1csratio
= MT47H128M16RT25E_RATIO
,
111 .cmd2csratio
= MT47H128M16RT25E_RATIO
,
114 static const struct emif_regs ddr2_emif_reg_data
= {
115 .sdram_config
= MT47H128M16RT25E_EMIF_SDCFG
,
116 .ref_ctrl
= MT47H128M16RT25E_EMIF_SDREF
,
117 .sdram_tim1
= MT47H128M16RT25E_EMIF_TIM1
,
118 .sdram_tim2
= MT47H128M16RT25E_EMIF_TIM2
,
119 .sdram_tim3
= MT47H128M16RT25E_EMIF_TIM3
,
120 .emif_ddr_phy_ctlr_1
= MT47H128M16RT25E_EMIF_READ_LATENCY
,
123 static const struct emif_regs ddr2_evm_emif_reg_data
= {
124 .sdram_config
= MT47H128M16RT25E_EMIF_SDCFG
,
125 .ref_ctrl
= MT47H128M16RT25E_EMIF_SDREF
,
126 .sdram_tim1
= MT47H128M16RT25E_EMIF_TIM1
,
127 .sdram_tim2
= MT47H128M16RT25E_EMIF_TIM2
,
128 .sdram_tim3
= MT47H128M16RT25E_EMIF_TIM3
,
129 .ocp_config
= EMIF_OCP_CONFIG_AM335X_EVM
,
130 .emif_ddr_phy_ctlr_1
= MT47H128M16RT25E_EMIF_READ_LATENCY
,
133 static const struct ddr_data ddr3_data
= {
134 .datardsratio0
= MT41J128MJT125_RD_DQS
,
135 .datawdsratio0
= MT41J128MJT125_WR_DQS
,
136 .datafwsratio0
= MT41J128MJT125_PHY_FIFO_WE
,
137 .datawrsratio0
= MT41J128MJT125_PHY_WR_DATA
,
140 static const struct ddr_data ddr3_beagleblack_data
= {
141 .datardsratio0
= MT41K256M16HA125E_RD_DQS
,
142 .datawdsratio0
= MT41K256M16HA125E_WR_DQS
,
143 .datafwsratio0
= MT41K256M16HA125E_PHY_FIFO_WE
,
144 .datawrsratio0
= MT41K256M16HA125E_PHY_WR_DATA
,
147 static const struct ddr_data ddr3_evm_data
= {
148 .datardsratio0
= MT41J512M8RH125_RD_DQS
,
149 .datawdsratio0
= MT41J512M8RH125_WR_DQS
,
150 .datafwsratio0
= MT41J512M8RH125_PHY_FIFO_WE
,
151 .datawrsratio0
= MT41J512M8RH125_PHY_WR_DATA
,
154 static const struct ddr_data ddr3_icev2_data
= {
155 .datardsratio0
= MT41J128MJT125_RD_DQS_400MHz
,
156 .datawdsratio0
= MT41J128MJT125_WR_DQS_400MHz
,
157 .datafwsratio0
= MT41J128MJT125_PHY_FIFO_WE_400MHz
,
158 .datawrsratio0
= MT41J128MJT125_PHY_WR_DATA_400MHz
,
161 static const struct cmd_control ddr3_cmd_ctrl_data
= {
162 .cmd0csratio
= MT41J128MJT125_RATIO
,
163 .cmd0iclkout
= MT41J128MJT125_INVERT_CLKOUT
,
165 .cmd1csratio
= MT41J128MJT125_RATIO
,
166 .cmd1iclkout
= MT41J128MJT125_INVERT_CLKOUT
,
168 .cmd2csratio
= MT41J128MJT125_RATIO
,
169 .cmd2iclkout
= MT41J128MJT125_INVERT_CLKOUT
,
172 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data
= {
173 .cmd0csratio
= MT41K256M16HA125E_RATIO
,
174 .cmd0iclkout
= MT41K256M16HA125E_INVERT_CLKOUT
,
176 .cmd1csratio
= MT41K256M16HA125E_RATIO
,
177 .cmd1iclkout
= MT41K256M16HA125E_INVERT_CLKOUT
,
179 .cmd2csratio
= MT41K256M16HA125E_RATIO
,
180 .cmd2iclkout
= MT41K256M16HA125E_INVERT_CLKOUT
,
183 static const struct cmd_control ddr3_evm_cmd_ctrl_data
= {
184 .cmd0csratio
= MT41J512M8RH125_RATIO
,
185 .cmd0iclkout
= MT41J512M8RH125_INVERT_CLKOUT
,
187 .cmd1csratio
= MT41J512M8RH125_RATIO
,
188 .cmd1iclkout
= MT41J512M8RH125_INVERT_CLKOUT
,
190 .cmd2csratio
= MT41J512M8RH125_RATIO
,
191 .cmd2iclkout
= MT41J512M8RH125_INVERT_CLKOUT
,
194 static const struct cmd_control ddr3_icev2_cmd_ctrl_data
= {
195 .cmd0csratio
= MT41J128MJT125_RATIO_400MHz
,
196 .cmd0iclkout
= MT41J128MJT125_INVERT_CLKOUT_400MHz
,
198 .cmd1csratio
= MT41J128MJT125_RATIO_400MHz
,
199 .cmd1iclkout
= MT41J128MJT125_INVERT_CLKOUT_400MHz
,
201 .cmd2csratio
= MT41J128MJT125_RATIO_400MHz
,
202 .cmd2iclkout
= MT41J128MJT125_INVERT_CLKOUT_400MHz
,
205 static struct emif_regs ddr3_emif_reg_data
= {
206 .sdram_config
= MT41J128MJT125_EMIF_SDCFG
,
207 .ref_ctrl
= MT41J128MJT125_EMIF_SDREF
,
208 .sdram_tim1
= MT41J128MJT125_EMIF_TIM1
,
209 .sdram_tim2
= MT41J128MJT125_EMIF_TIM2
,
210 .sdram_tim3
= MT41J128MJT125_EMIF_TIM3
,
211 .zq_config
= MT41J128MJT125_ZQ_CFG
,
212 .emif_ddr_phy_ctlr_1
= MT41J128MJT125_EMIF_READ_LATENCY
|
216 static struct emif_regs ddr3_beagleblack_emif_reg_data
= {
217 .sdram_config
= MT41K256M16HA125E_EMIF_SDCFG
,
218 .ref_ctrl
= MT41K256M16HA125E_EMIF_SDREF
,
219 .sdram_tim1
= MT41K256M16HA125E_EMIF_TIM1
,
220 .sdram_tim2
= MT41K256M16HA125E_EMIF_TIM2
,
221 .sdram_tim3
= MT41K256M16HA125E_EMIF_TIM3
,
222 .ocp_config
= EMIF_OCP_CONFIG_BEAGLEBONE_BLACK
,
223 .zq_config
= MT41K256M16HA125E_ZQ_CFG
,
224 .emif_ddr_phy_ctlr_1
= MT41K256M16HA125E_EMIF_READ_LATENCY
,
227 static struct emif_regs ddr3_evm_emif_reg_data
= {
228 .sdram_config
= MT41J512M8RH125_EMIF_SDCFG
,
229 .ref_ctrl
= MT41J512M8RH125_EMIF_SDREF
,
230 .sdram_tim1
= MT41J512M8RH125_EMIF_TIM1
,
231 .sdram_tim2
= MT41J512M8RH125_EMIF_TIM2
,
232 .sdram_tim3
= MT41J512M8RH125_EMIF_TIM3
,
233 .ocp_config
= EMIF_OCP_CONFIG_AM335X_EVM
,
234 .zq_config
= MT41J512M8RH125_ZQ_CFG
,
235 .emif_ddr_phy_ctlr_1
= MT41J512M8RH125_EMIF_READ_LATENCY
|
239 static struct emif_regs ddr3_icev2_emif_reg_data
= {
240 .sdram_config
= MT41J128MJT125_EMIF_SDCFG_400MHz
,
241 .ref_ctrl
= MT41J128MJT125_EMIF_SDREF_400MHz
,
242 .sdram_tim1
= MT41J128MJT125_EMIF_TIM1_400MHz
,
243 .sdram_tim2
= MT41J128MJT125_EMIF_TIM2_400MHz
,
244 .sdram_tim3
= MT41J128MJT125_EMIF_TIM3_400MHz
,
245 .zq_config
= MT41J128MJT125_ZQ_CFG_400MHz
,
246 .emif_ddr_phy_ctlr_1
= MT41J128MJT125_EMIF_READ_LATENCY_400MHz
|
250 #ifdef CONFIG_SPL_OS_BOOT
251 int spl_start_uboot(void)
253 #ifdef CONFIG_SPL_SERIAL
254 /* break into full u-boot on 'c' */
255 if (serial_tstc() && serial_getc() == 'c')
259 #ifdef CONFIG_SPL_ENV_SUPPORT
262 if (env_get_yesno("boot_os") != 1)
270 const struct dpll_params
*get_dpll_ddr_params(void)
272 int ind
= get_sys_clk_index();
274 if (board_is_evm_sk())
275 return &dpll_ddr3_303MHz
[ind
];
276 else if (board_is_pb() || board_is_bone_lt() || board_is_icev2())
277 return &dpll_ddr3_400MHz
[ind
];
278 else if (board_is_evm_15_or_later())
279 return &dpll_ddr3_303MHz
[ind
];
281 return &dpll_ddr2_266MHz
[ind
];
284 static u8
bone_not_connected_to_ac_power(void)
286 if (board_is_bone()) {
287 uchar pmic_status_reg
;
288 if (tps65217_reg_read(TPS65217_STATUS
,
291 if (!(pmic_status_reg
& TPS65217_PWR_SRC_AC_BITMASK
)) {
292 puts("No AC power, switching to default OPP\n");
299 const struct dpll_params
*get_dpll_mpu_params(void)
301 int ind
= get_sys_clk_index();
302 int freq
= am335x_get_efuse_mpu_max_freq(cdev
);
304 if (bone_not_connected_to_ac_power())
307 if (board_is_pb() || board_is_bone_lt())
308 freq
= MPUPLL_M_1000
;
312 return &dpll_mpu_opp
[ind
][5];
314 return &dpll_mpu_opp
[ind
][4];
316 return &dpll_mpu_opp
[ind
][3];
318 return &dpll_mpu_opp
[ind
][2];
320 return &dpll_mpu_opp100
;
322 return &dpll_mpu_opp
[ind
][0];
325 return &dpll_mpu_opp
[ind
][0];
328 static void scale_vcores_bone(int freq
)
330 int usb_cur_lim
, mpu_vdd
;
333 * Only perform PMIC configurations if board rev > A1
334 * on Beaglebone White
336 if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4))
339 if (power_tps65217_init(0))
344 * On Beaglebone White we need to ensure we have AC power
345 * before increasing the frequency.
347 if (bone_not_connected_to_ac_power())
351 * Override what we have detected since we know if we have
352 * a Beaglebone Black it supports 1GHz.
354 if (board_is_pb() || board_is_bone_lt())
355 freq
= MPUPLL_M_1000
;
359 mpu_vdd
= TPS65217_DCDC_VOLT_SEL_1325MV
;
360 usb_cur_lim
= TPS65217_USB_INPUT_CUR_LIMIT_1800MA
;
363 mpu_vdd
= TPS65217_DCDC_VOLT_SEL_1275MV
;
364 usb_cur_lim
= TPS65217_USB_INPUT_CUR_LIMIT_1300MA
;
367 mpu_vdd
= TPS65217_DCDC_VOLT_SEL_1200MV
;
368 usb_cur_lim
= TPS65217_USB_INPUT_CUR_LIMIT_1300MA
;
374 mpu_vdd
= TPS65217_DCDC_VOLT_SEL_1100MV
;
375 usb_cur_lim
= TPS65217_USB_INPUT_CUR_LIMIT_1300MA
;
379 if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE
,
382 TPS65217_USB_INPUT_CUR_LIMIT_MASK
))
383 puts("tps65217_reg_write failure\n");
385 /* Set DCDC3 (CORE) voltage to 1.10V */
386 if (tps65217_voltage_update(TPS65217_DEFDCDC3
,
387 TPS65217_DCDC_VOLT_SEL_1100MV
)) {
388 puts("tps65217_voltage_update failure\n");
392 /* Set DCDC2 (MPU) voltage */
393 if (tps65217_voltage_update(TPS65217_DEFDCDC2
, mpu_vdd
)) {
394 puts("tps65217_voltage_update failure\n");
399 * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
400 * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
402 if (board_is_bone()) {
403 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2
,
405 TPS65217_LDO_VOLTAGE_OUT_3_3
,
407 puts("tps65217_reg_write failure\n");
409 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2
,
411 TPS65217_LDO_VOLTAGE_OUT_1_8
,
413 puts("tps65217_reg_write failure\n");
416 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2
,
418 TPS65217_LDO_VOLTAGE_OUT_3_3
,
420 puts("tps65217_reg_write failure\n");
423 void scale_vcores_generic(int freq
)
425 int sil_rev
, mpu_vdd
;
428 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
429 * MPU frequencies we support we use a CORE voltage of
430 * 1.10V. For MPU voltage we need to switch based on
431 * the frequency we are running at.
433 if (power_tps65910_init(0))
436 * Depending on MPU clock and PG we will need a different
437 * VDD to drive at that speed.
439 sil_rev
= readl(&cdev
->deviceid
) >> 28;
440 mpu_vdd
= am335x_get_tps65910_mpu_vdd(sil_rev
, freq
);
442 /* Tell the TPS65910 to use i2c */
443 tps65910_set_i2c_control();
445 /* First update MPU voltage. */
446 if (tps65910_voltage_update(MPU
, mpu_vdd
))
449 /* Second, update the CORE voltage. */
450 if (tps65910_voltage_update(CORE
, TPS65910_OP_REG_SEL_1_1_0
))
455 void gpi2c_init(void)
457 /* When needed to be invoked prior to BSS initialization */
458 static bool first_time
= true;
461 enable_i2c0_pin_mux();
466 void scale_vcores(void)
471 freq
= am335x_get_efuse_mpu_max_freq(cdev
);
473 if (board_is_beaglebonex())
474 scale_vcores_bone(freq
);
476 scale_vcores_generic(freq
);
479 void set_uart_mux_conf(void)
481 #if CONFIG_CONS_INDEX == 1
482 enable_uart0_pin_mux();
483 #elif CONFIG_CONS_INDEX == 2
484 enable_uart1_pin_mux();
485 #elif CONFIG_CONS_INDEX == 3
486 enable_uart2_pin_mux();
487 #elif CONFIG_CONS_INDEX == 4
488 enable_uart3_pin_mux();
489 #elif CONFIG_CONS_INDEX == 5
490 enable_uart4_pin_mux();
491 #elif CONFIG_CONS_INDEX == 6
492 enable_uart5_pin_mux();
496 void set_mux_conf_regs(void)
498 enable_board_pin_mux();
501 const struct ctrl_ioregs ioregs_evmsk
= {
502 .cm0ioctl
= MT41J128MJT125_IOCTRL_VALUE
,
503 .cm1ioctl
= MT41J128MJT125_IOCTRL_VALUE
,
504 .cm2ioctl
= MT41J128MJT125_IOCTRL_VALUE
,
505 .dt0ioctl
= MT41J128MJT125_IOCTRL_VALUE
,
506 .dt1ioctl
= MT41J128MJT125_IOCTRL_VALUE
,
509 const struct ctrl_ioregs ioregs_bonelt
= {
510 .cm0ioctl
= MT41K256M16HA125E_IOCTRL_VALUE
,
511 .cm1ioctl
= MT41K256M16HA125E_IOCTRL_VALUE
,
512 .cm2ioctl
= MT41K256M16HA125E_IOCTRL_VALUE
,
513 .dt0ioctl
= MT41K256M16HA125E_IOCTRL_VALUE
,
514 .dt1ioctl
= MT41K256M16HA125E_IOCTRL_VALUE
,
517 const struct ctrl_ioregs ioregs_evm15
= {
518 .cm0ioctl
= MT41J512M8RH125_IOCTRL_VALUE
,
519 .cm1ioctl
= MT41J512M8RH125_IOCTRL_VALUE
,
520 .cm2ioctl
= MT41J512M8RH125_IOCTRL_VALUE
,
521 .dt0ioctl
= MT41J512M8RH125_IOCTRL_VALUE
,
522 .dt1ioctl
= MT41J512M8RH125_IOCTRL_VALUE
,
525 const struct ctrl_ioregs ioregs
= {
526 .cm0ioctl
= MT47H128M16RT25E_IOCTRL_VALUE
,
527 .cm1ioctl
= MT47H128M16RT25E_IOCTRL_VALUE
,
528 .cm2ioctl
= MT47H128M16RT25E_IOCTRL_VALUE
,
529 .dt0ioctl
= MT47H128M16RT25E_IOCTRL_VALUE
,
530 .dt1ioctl
= MT47H128M16RT25E_IOCTRL_VALUE
,
533 void sdram_init(void)
535 if (board_is_evm_sk()) {
537 * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
538 * This is safe enough to do on older revs.
540 gpio_request(GPIO_DDR_VTT_EN
, "ddr_vtt_en");
541 gpio_direction_output(GPIO_DDR_VTT_EN
, 1);
544 if (board_is_icev2()) {
545 gpio_request(ICE_GPIO_DDR_VTT_EN
, "ddr_vtt_en");
546 gpio_direction_output(ICE_GPIO_DDR_VTT_EN
, 1);
549 if (board_is_evm_sk())
550 config_ddr(303, &ioregs_evmsk
, &ddr3_data
,
551 &ddr3_cmd_ctrl_data
, &ddr3_emif_reg_data
, 0);
552 else if (board_is_pb() || board_is_bone_lt())
553 config_ddr(400, &ioregs_bonelt
,
554 &ddr3_beagleblack_data
,
555 &ddr3_beagleblack_cmd_ctrl_data
,
556 &ddr3_beagleblack_emif_reg_data
, 0);
557 else if (board_is_evm_15_or_later())
558 config_ddr(303, &ioregs_evm15
, &ddr3_evm_data
,
559 &ddr3_evm_cmd_ctrl_data
, &ddr3_evm_emif_reg_data
, 0);
560 else if (board_is_icev2())
561 config_ddr(400, &ioregs_evmsk
, &ddr3_icev2_data
,
562 &ddr3_icev2_cmd_ctrl_data
, &ddr3_icev2_emif_reg_data
,
564 else if (board_is_gp_evm())
565 config_ddr(266, &ioregs
, &ddr2_data
,
566 &ddr2_cmd_ctrl_data
, &ddr2_evm_emif_reg_data
, 0);
568 config_ddr(266, &ioregs
, &ddr2_data
,
569 &ddr2_cmd_ctrl_data
, &ddr2_emif_reg_data
, 0);
573 #if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
574 (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD)))
575 static void request_and_set_gpio(int gpio
, char *name
, int val
)
579 ret
= gpio_request(gpio
, name
);
581 printf("%s: Unable to request %s\n", __func__
, name
);
585 ret
= gpio_direction_output(gpio
, 0);
587 printf("%s: Unable to set %s as output\n", __func__
, name
);
591 gpio_set_value(gpio
, val
);
599 #define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N, 1);
600 #define REQUEST_AND_CLR_GPIO(N) request_and_set_gpio(N, #N, 0);
603 * RMII mode on ICEv2 board needs 50MHz clock. Given the clock
604 * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle
605 * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to
606 * give 50MHz output for Eth0 and 1.
608 static struct clk_synth cdce913_data
= {
617 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_CONTROL) && \
618 defined(CONFIG_DM_ETH) && defined(CONFIG_DRIVER_TI_CPSW)
620 #define MAX_CPSW_SLAVES 2
622 /* At the moment, we do not want to stop booting for any failures here */
623 int ft_board_setup(void *fdt
, struct bd_info
*bd
)
625 const char *slave_path
, *enet_name
;
626 int enetnode
, slavenode
, phynode
;
627 struct udevice
*ethdev
;
633 /* phy address fixup needed only on beagle bone family */
634 if (!board_is_beaglebonex())
637 for (i
= 0; i
< MAX_CPSW_SLAVES
; i
++) {
638 sprintf(alias
, "ethernet%d", i
);
640 slave_path
= fdt_get_alias(fdt
, alias
);
644 slavenode
= fdt_path_offset(fdt
, slave_path
);
648 enetnode
= fdt_parent_offset(fdt
, slavenode
);
649 enet_name
= fdt_get_name(fdt
, enetnode
, NULL
);
651 ethdev
= eth_get_dev_by_name(enet_name
);
655 phy_addr
= cpsw_get_slave_phy_addr(ethdev
, i
);
657 /* check for phy_id as well as phy-handle properties */
658 ret
= fdtdec_get_int_array_count(fdt
, slavenode
, "phy_id",
661 if (phy_id
[1] != phy_addr
) {
662 printf("fixing up phy_id for %s, old: %d, new: %d\n",
663 alias
, phy_id
[1], phy_addr
);
665 phy_id
[0] = cpu_to_fdt32(phy_id
[0]);
666 phy_id
[1] = cpu_to_fdt32(phy_addr
);
667 do_fixup_by_path(fdt
, slave_path
, "phy_id",
668 phy_id
, sizeof(phy_id
), 0);
671 phynode
= fdtdec_lookup_phandle(fdt
, slavenode
,
676 ret
= fdtdec_get_int(fdt
, phynode
, "reg", -ENOENT
);
680 if (ret
!= phy_addr
) {
681 printf("fixing up phy-handle for %s, old: %d, new: %d\n",
682 alias
, ret
, phy_addr
);
684 fdt_setprop_u32(fdt
, phynode
, "reg",
685 cpu_to_fdt32(phy_addr
));
695 static bool __maybe_unused prueth_is_mii
= true;
698 * Basic board specific setup. Pinmux has been handled already.
702 #if defined(CONFIG_HW_WATCHDOG)
706 gd
->bd
->bi_boot_params
= CFG_SYS_SDRAM_BASE
+ 0x100;
707 #if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
711 #if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
712 (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD)))
713 if (board_is_icev2()) {
716 bool eth0_is_mii
= true;
717 bool eth1_is_mii
= true;
719 REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL
);
720 /* Make J19 status available on GPIO1_26 */
721 REQUEST_AND_CLR_GPIO(GPIO_MUX_MII_CTRL
);
723 REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL
);
725 * Both ports can be set as RMII-CPSW or MII-PRU-ETH using
726 * jumpers near the port. Read the jumper value and set
727 * the pinmux, external mux and PHY clock accordingly.
728 * As jumper line is overridden by PHY RX_DV pin immediately
729 * after bootstrap (power-up/reset), we need to sample
730 * it during PHY reset using GPIO rising edge detection.
732 REQUEST_AND_SET_GPIO(GPIO_PHY_RESET
);
733 /* Enable rising edge IRQ on GPIO0_11 and GPIO 1_26 */
734 reg
= readl(GPIO0_RISINGDETECT
) | BIT(11);
735 writel(reg
, GPIO0_RISINGDETECT
);
736 reg
= readl(GPIO1_RISINGDETECT
) | BIT(26);
737 writel(reg
, GPIO1_RISINGDETECT
);
738 /* Reset PHYs to capture the Jumper setting */
739 gpio_set_value(GPIO_PHY_RESET
, 0);
740 udelay(2); /* PHY datasheet states 1uS min. */
741 gpio_set_value(GPIO_PHY_RESET
, 1);
743 reg
= readl(GPIO0_IRQSTATUSRAW
) & BIT(11);
745 writel(reg
, GPIO0_IRQSTATUS1
); /* clear irq */
747 printf("ETH0, CPSW\n");
751 printf("ETH0, PRU\n");
752 cdce913_data
.pdiv3
= 4; /* 25MHz PHY clk */
755 reg
= readl(GPIO1_IRQSTATUSRAW
) & BIT(26);
757 writel(reg
, GPIO1_IRQSTATUS1
); /* clear irq */
759 printf("ETH1, CPSW\n");
760 gpio_set_value(GPIO_MUX_MII_CTRL
, 1);
764 printf("ETH1, PRU\n");
765 cdce913_data
.pdiv2
= 4; /* 25MHz PHY clk */
768 if (eth0_is_mii
!= eth1_is_mii
) {
769 printf("Unsupported Ethernet port configuration\n");
770 printf("Both ports must be set as RMII or MII\n");
774 prueth_is_mii
= eth0_is_mii
;
776 /* disable rising edge IRQs */
777 reg
= readl(GPIO0_RISINGDETECT
) & ~BIT(11);
778 writel(reg
, GPIO0_RISINGDETECT
);
779 reg
= readl(GPIO1_RISINGDETECT
) & ~BIT(26);
780 writel(reg
, GPIO1_RISINGDETECT
);
782 rv
= setup_clock_synthesizer(&cdce913_data
);
784 printf("Clock synthesizer setup failed %d\n", rv
);
789 gpio_set_value(GPIO_PHY_RESET
, 0);
790 udelay(2); /* PHY datasheet states 1uS min. */
791 gpio_set_value(GPIO_PHY_RESET
, 1);
798 #ifdef CONFIG_BOARD_LATE_INIT
799 int board_late_init(void)
802 #if !defined(CONFIG_SPL_BUILD)
804 uint32_t mac_hi
, mac_lo
;
807 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
810 if (board_is_bone_lt()) {
811 /* BeagleBoard.org BeagleBone Black Wireless: */
812 if (!strncmp(board_ti_get_rev(), "BWA", 3)) {
815 /* SeeedStudio BeagleBone Green Wireless */
816 if (!strncmp(board_ti_get_rev(), "GW1", 3)) {
819 /* BeagleBoard.org BeagleBone Blue */
820 if (!strncmp(board_ti_get_rev(), "BLA", 3)) {
827 if (board_is_bben()) {
828 char subtype_id
= board_ti_get_config()[1];
830 switch (subtype_id
) {
835 name
= "BBE_EX_WIFI";
841 set_board_info_env(name
);
844 * Default FIT boot on HS devices. Non FIT images are not allowed
847 if (get_device_type() == HS_DEVICE
)
848 env_set("boot_fit", "1");
851 #if !defined(CONFIG_SPL_BUILD)
852 /* try reading mac address from efuse */
853 mac_lo
= readl(&cdev
->macid0l
);
854 mac_hi
= readl(&cdev
->macid0h
);
855 mac_addr
[0] = mac_hi
& 0xFF;
856 mac_addr
[1] = (mac_hi
& 0xFF00) >> 8;
857 mac_addr
[2] = (mac_hi
& 0xFF0000) >> 16;
858 mac_addr
[3] = (mac_hi
& 0xFF000000) >> 24;
859 mac_addr
[4] = mac_lo
& 0xFF;
860 mac_addr
[5] = (mac_lo
& 0xFF00) >> 8;
862 if (!env_get("ethaddr")) {
863 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
865 if (is_valid_ethaddr(mac_addr
))
866 eth_env_set_enetaddr("ethaddr", mac_addr
);
869 mac_lo
= readl(&cdev
->macid1l
);
870 mac_hi
= readl(&cdev
->macid1h
);
871 mac_addr
[0] = mac_hi
& 0xFF;
872 mac_addr
[1] = (mac_hi
& 0xFF00) >> 8;
873 mac_addr
[2] = (mac_hi
& 0xFF0000) >> 16;
874 mac_addr
[3] = (mac_hi
& 0xFF000000) >> 24;
875 mac_addr
[4] = mac_lo
& 0xFF;
876 mac_addr
[5] = (mac_lo
& 0xFF00) >> 8;
878 if (!env_get("eth1addr")) {
879 if (is_valid_ethaddr(mac_addr
))
880 eth_env_set_enetaddr("eth1addr", mac_addr
);
883 env_set("ice_mii", prueth_is_mii
? "mii" : "rmii");
886 if (!env_get("serial#")) {
887 char *board_serial
= env_get("board_serial");
888 char *ethaddr
= env_get("ethaddr");
890 if (!board_serial
|| !strncmp(board_serial
, "unknown", 7))
891 env_set("serial#", ethaddr
);
893 env_set("serial#", board_serial
);
896 /* Just probe the potentially supported cdce913 device */
897 uclass_get_device_by_name(UCLASS_CLK
, "cdce913@65", &dev
);
904 #if CONFIG_IS_ENABLED(NET) && !CONFIG_IS_ENABLED(OF_CONTROL)
905 struct cpsw_slave_data slave_data
[] = {
907 .slave_reg_ofs
= CPSW_SLAVE0_OFFSET
,
908 .sliver_reg_ofs
= CPSW_SLIVER0_OFFSET
,
912 .slave_reg_ofs
= CPSW_SLAVE1_OFFSET
,
913 .sliver_reg_ofs
= CPSW_SLIVER1_OFFSET
,
918 struct cpsw_platform_data am335_eth_data
= {
919 .cpsw_base
= CPSW_BASE
,
920 .version
= CPSW_CTRL_VERSION_2
,
921 .bd_ram_ofs
= CPSW_BD_OFFSET
,
922 .ale_reg_ofs
= CPSW_ALE_OFFSET
,
923 .cpdma_reg_ofs
= CPSW_CPDMA_OFFSET
,
924 .mdio_div
= CPSW_MDIO_DIV
,
925 .host_port_reg_ofs
= CPSW_HOST_PORT_OFFSET
,
928 .slave_data
= slave_data
,
932 .mdio_base
= 0x4a101000,
933 .gmii_sel
= 0x44e10650,
934 .phy_sel_compat
= "ti,am3352-cpsw-phy-sel",
935 .syscon_addr
= 0x44e10630,
936 .macid_sel_compat
= "cpsw,am33xx",
939 struct eth_pdata cpsw_pdata
= {
940 .iobase
= 0x4a100000,
942 .priv_pdata
= &am335_eth_data
,
945 U_BOOT_DRVINFO(am335x_eth
) = {
951 #ifdef CONFIG_SPL_LOAD_FIT
952 int board_fit_config_name_match(const char *name
)
954 if (board_is_gp_evm() && !strcmp(name
, "am335x-evm"))
956 else if (board_is_bone() && !strcmp(name
, "am335x-bone"))
958 else if (board_is_bone_lt() && !strcmp(name
, "am335x-boneblack"))
960 else if (board_is_pb() && !strcmp(name
, "am335x-pocketbeagle"))
962 else if (board_is_evm_sk() && !strcmp(name
, "am335x-evmsk"))
964 else if (board_is_bbg1() && !strcmp(name
, "am335x-bonegreen"))
966 else if (board_is_icev2() && !strcmp(name
, "am335x-icev2"))
968 else if (board_is_bben()) {
969 char subtype_id
= board_ti_get_config()[1];
971 if (subtype_id
== 'L') {
972 if (!strcmp(name
, "am335x-sancloud-bbe-lite"))
974 } else if (subtype_id
== 'I') {
975 if (!strcmp(name
, "am335x-sancloud-bbe-extended-wifi"))
977 } else if (!strcmp(name
, "am335x-sancloud-bbe")) {
985 #if !CONFIG_IS_ENABLED(OF_CONTROL)
986 static const struct omap_hsmmc_plat am335x_mmc0_plat
= {
987 .base_addr
= (struct hsmmc
*)OMAP_HSMMC1_BASE
,
988 .cfg
.host_caps
= MMC_MODE_HS_52MHz
| MMC_MODE_HS
| MMC_MODE_4BIT
,
990 .cfg
.f_max
= 52000000,
991 .cfg
.voltages
= MMC_VDD_32_33
| MMC_VDD_33_34
| MMC_VDD_165_195
,
992 .cfg
.b_max
= CONFIG_SYS_MMC_MAX_BLK_COUNT
,
995 U_BOOT_DRVINFO(am335x_mmc0
) = {
996 .name
= "omap_hsmmc",
997 .plat
= &am335x_mmc0_plat
,
1000 static const struct omap_hsmmc_plat am335x_mmc1_plat
= {
1001 .base_addr
= (struct hsmmc
*)OMAP_HSMMC2_BASE
,
1002 .cfg
.host_caps
= MMC_MODE_HS_52MHz
| MMC_MODE_HS
| MMC_MODE_8BIT
,
1003 .cfg
.f_min
= 400000,
1004 .cfg
.f_max
= 52000000,
1005 .cfg
.voltages
= MMC_VDD_32_33
| MMC_VDD_33_34
| MMC_VDD_165_195
,
1006 .cfg
.b_max
= CONFIG_SYS_MMC_MAX_BLK_COUNT
,
1009 U_BOOT_DRVINFO(am335x_mmc1
) = {
1010 .name
= "omap_hsmmc",
1011 .plat
= &am335x_mmc1_plat
,