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SPDX: Convert all of our single license tags to Linux Kernel style
[thirdparty/u-boot.git] / board / ti / am57xx / board.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
4 *
5 * Author: Felipe Balbi <balbi@ti.com>
6 *
7 * Based on board/ti/dra7xx/evm.c
8 */
9
10 #include <common.h>
11 #include <palmas.h>
12 #include <sata.h>
13 #include <usb.h>
14 #include <asm/omap_common.h>
15 #include <asm/omap_sec_common.h>
16 #include <asm/emif.h>
17 #include <asm/gpio.h>
18 #include <asm/arch/gpio.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/dra7xx_iodelay.h>
21 #include <asm/arch/sys_proto.h>
22 #include <asm/arch/mmc_host_def.h>
23 #include <asm/arch/sata.h>
24 #include <asm/arch/gpio.h>
25 #include <asm/arch/omap.h>
26 #include <environment.h>
27 #include <usb.h>
28 #include <linux/usb/gadget.h>
29 #include <dwc3-uboot.h>
30 #include <dwc3-omap-uboot.h>
31 #include <ti-usb-phy-uboot.h>
32 #include <mmc.h>
33
34 #include "../common/board_detect.h"
35 #include "mux_data.h"
36
37 #define board_is_x15() board_ti_is("BBRDX15_")
38 #define board_is_x15_revb1() (board_ti_is("BBRDX15_") && \
39 !strncmp("B.10", board_ti_get_rev(), 3))
40 #define board_is_x15_revc() (board_ti_is("BBRDX15_") && \
41 !strncmp("C.00", board_ti_get_rev(), 3))
42 #define board_is_am572x_evm() board_ti_is("AM572PM_")
43 #define board_is_am572x_evm_reva3() \
44 (board_ti_is("AM572PM_") && \
45 !strncmp("A.30", board_ti_get_rev(), 3))
46 #define board_is_am574x_idk() board_ti_is("AM574IDK")
47 #define board_is_am572x_idk() board_ti_is("AM572IDK")
48 #define board_is_am571x_idk() board_ti_is("AM571IDK")
49
50 #ifdef CONFIG_DRIVER_TI_CPSW
51 #include <cpsw.h>
52 #endif
53
54 DECLARE_GLOBAL_DATA_PTR;
55
56 #define GPIO_ETH_LCD GPIO_TO_PIN(2, 22)
57 /* GPIO 7_11 */
58 #define GPIO_DDR_VTT_EN 203
59
60 /* Touch screen controller to identify the LCD */
61 #define OSD_TS_FT_BUS_ADDRESS 0
62 #define OSD_TS_FT_CHIP_ADDRESS 0x38
63 #define OSD_TS_FT_REG_ID 0xA3
64 /*
65 * Touchscreen IDs for various OSD panels
66 * Ref: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf
67 */
68 /* Used on newer osd101t2587 Panels */
69 #define OSD_TS_FT_ID_5x46 0x54
70 /* Used on older osd101t2045 Panels */
71 #define OSD_TS_FT_ID_5606 0x08
72
73 #define SYSINFO_BOARD_NAME_MAX_LEN 45
74
75 #define TPS65903X_PRIMARY_SECONDARY_PAD2 0xFB
76 #define TPS65903X_PAD2_POWERHOLD_MASK 0x20
77
78 const struct omap_sysinfo sysinfo = {
79 "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
80 };
81
82 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
83 .dmm_lisa_map_3 = 0x80740300,
84 .is_ma_present = 0x1
85 };
86
87 static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
88 .dmm_lisa_map_3 = 0x80640100,
89 .is_ma_present = 0x1
90 };
91
92 static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
93 .dmm_lisa_map_2 = 0xc0600200,
94 .dmm_lisa_map_3 = 0x80600100,
95 .is_ma_present = 0x1
96 };
97
98 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
99 {
100 if (board_is_am571x_idk())
101 *dmm_lisa_regs = &am571x_idk_lisa_regs;
102 else if (board_is_am574x_idk())
103 *dmm_lisa_regs = &am574x_idk_lisa_regs;
104 else
105 *dmm_lisa_regs = &beagle_x15_lisa_regs;
106 }
107
108 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
109 .sdram_config_init = 0x61851b32,
110 .sdram_config = 0x61851b32,
111 .sdram_config2 = 0x08000000,
112 .ref_ctrl = 0x000040F1,
113 .ref_ctrl_final = 0x00001035,
114 .sdram_tim1 = 0xcccf36ab,
115 .sdram_tim2 = 0x308f7fda,
116 .sdram_tim3 = 0x409f88a8,
117 .read_idle_ctrl = 0x00050000,
118 .zq_config = 0x5007190b,
119 .temp_alert_config = 0x00000000,
120 .emif_ddr_phy_ctlr_1_init = 0x0024400b,
121 .emif_ddr_phy_ctlr_1 = 0x0e24400b,
122 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
123 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
124 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
125 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
126 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
127 .emif_rd_wr_lvl_rmp_win = 0x00000000,
128 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
129 .emif_rd_wr_lvl_ctl = 0x00000000,
130 .emif_rd_wr_exec_thresh = 0x00000305
131 };
132
133 /* Ext phy ctrl regs 1-35 */
134 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
135 0x10040100,
136 0x00910091,
137 0x00950095,
138 0x009B009B,
139 0x009E009E,
140 0x00980098,
141 0x00340034,
142 0x00350035,
143 0x00340034,
144 0x00310031,
145 0x00340034,
146 0x007F007F,
147 0x007F007F,
148 0x007F007F,
149 0x007F007F,
150 0x007F007F,
151 0x00480048,
152 0x004A004A,
153 0x00520052,
154 0x00550055,
155 0x00500050,
156 0x00000000,
157 0x00600020,
158 0x40011080,
159 0x08102040,
160 0x0,
161 0x0,
162 0x0,
163 0x0,
164 0x0,
165 0x0,
166 0x0,
167 0x0,
168 0x0,
169 0x0
170 };
171
172 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
173 .sdram_config_init = 0x61851b32,
174 .sdram_config = 0x61851b32,
175 .sdram_config2 = 0x08000000,
176 .ref_ctrl = 0x000040F1,
177 .ref_ctrl_final = 0x00001035,
178 .sdram_tim1 = 0xcccf36b3,
179 .sdram_tim2 = 0x308f7fda,
180 .sdram_tim3 = 0x407f88a8,
181 .read_idle_ctrl = 0x00050000,
182 .zq_config = 0x5007190b,
183 .temp_alert_config = 0x00000000,
184 .emif_ddr_phy_ctlr_1_init = 0x0024400b,
185 .emif_ddr_phy_ctlr_1 = 0x0e24400b,
186 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
187 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
188 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
189 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
190 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
191 .emif_rd_wr_lvl_rmp_win = 0x00000000,
192 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
193 .emif_rd_wr_lvl_ctl = 0x00000000,
194 .emif_rd_wr_exec_thresh = 0x00000305
195 };
196
197 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
198 0x10040100,
199 0x00910091,
200 0x00950095,
201 0x009B009B,
202 0x009E009E,
203 0x00980098,
204 0x00340034,
205 0x00350035,
206 0x00340034,
207 0x00310031,
208 0x00340034,
209 0x007F007F,
210 0x007F007F,
211 0x007F007F,
212 0x007F007F,
213 0x007F007F,
214 0x00480048,
215 0x004A004A,
216 0x00520052,
217 0x00550055,
218 0x00500050,
219 0x00000000,
220 0x00600020,
221 0x40011080,
222 0x08102040,
223 0x0,
224 0x0,
225 0x0,
226 0x0,
227 0x0,
228 0x0,
229 0x0,
230 0x0,
231 0x0,
232 0x0
233 };
234
235 static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = {
236 .sdram_config_init = 0x61863332,
237 .sdram_config = 0x61863332,
238 .sdram_config2 = 0x08000000,
239 .ref_ctrl = 0x0000514d,
240 .ref_ctrl_final = 0x0000144a,
241 .sdram_tim1 = 0xd333887c,
242 .sdram_tim2 = 0x30b37fe3,
243 .sdram_tim3 = 0x409f8ad8,
244 .read_idle_ctrl = 0x00050000,
245 .zq_config = 0x5007190b,
246 .temp_alert_config = 0x00000000,
247 .emif_ddr_phy_ctlr_1_init = 0x0024400f,
248 .emif_ddr_phy_ctlr_1 = 0x0e24400f,
249 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
250 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
251 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
252 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
253 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
254 .emif_rd_wr_lvl_rmp_win = 0x00000000,
255 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
256 .emif_rd_wr_lvl_ctl = 0x00000000,
257 .emif_rd_wr_exec_thresh = 0x00000305
258 };
259
260 static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = {
261 .sdram_config_init = 0x61863332,
262 .sdram_config = 0x61863332,
263 .sdram_config2 = 0x08000000,
264 .ref_ctrl = 0x0000514d,
265 .ref_ctrl_final = 0x0000144a,
266 .sdram_tim1 = 0xd333887c,
267 .sdram_tim2 = 0x30b37fe3,
268 .sdram_tim3 = 0x409f8ad8,
269 .read_idle_ctrl = 0x00050000,
270 .zq_config = 0x5007190b,
271 .temp_alert_config = 0x00000000,
272 .emif_ddr_phy_ctlr_1_init = 0x0024400f,
273 .emif_ddr_phy_ctlr_1 = 0x0e24400f,
274 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
275 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
276 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
277 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
278 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
279 .emif_rd_wr_lvl_rmp_win = 0x00000000,
280 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
281 .emif_rd_wr_lvl_ctl = 0x00000000,
282 .emif_rd_wr_exec_thresh = 0x00000305,
283 .emif_ecc_ctrl_reg = 0xD0000001,
284 .emif_ecc_address_range_1 = 0x3FFF0000,
285 .emif_ecc_address_range_2 = 0x00000000
286 };
287
288 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
289 {
290 switch (emif_nr) {
291 case 1:
292 if (board_is_am571x_idk())
293 *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
294 else if (board_is_am574x_idk())
295 *regs = &am574x_emif1_ddr3_666mhz_emif_ecc_regs;
296 else
297 *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
298 break;
299 case 2:
300 if (board_is_am574x_idk())
301 *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
302 else
303 *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
304 break;
305 }
306 }
307
308 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
309 {
310 switch (emif_nr) {
311 case 1:
312 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
313 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
314 break;
315 case 2:
316 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
317 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
318 break;
319 }
320 }
321
322 struct vcores_data beagle_x15_volts = {
323 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
324 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
325 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
326 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
327 .mpu.pmic = &tps659038,
328 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
329
330 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
331 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
332 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
333 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
334 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
335 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
336 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
337 .eve.addr = TPS659038_REG_ADDR_SMPS45,
338 .eve.pmic = &tps659038,
339 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
340
341 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
342 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
343 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
344 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
345 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
346 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
347 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
348 .gpu.addr = TPS659038_REG_ADDR_SMPS45,
349 .gpu.pmic = &tps659038,
350 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
351
352 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
353 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
354 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
355 .core.addr = TPS659038_REG_ADDR_SMPS6,
356 .core.pmic = &tps659038,
357
358 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
359 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
360 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
361 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
362 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
363 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
364 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
365 .iva.addr = TPS659038_REG_ADDR_SMPS45,
366 .iva.pmic = &tps659038,
367 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
368 };
369
370 struct vcores_data am572x_idk_volts = {
371 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
372 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
373 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
374 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
375 .mpu.pmic = &tps659038,
376 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
377
378 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
379 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
380 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
381 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
382 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
383 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
384 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
385 .eve.addr = TPS659038_REG_ADDR_SMPS45,
386 .eve.pmic = &tps659038,
387 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
388
389 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
390 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
391 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
392 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
393 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
394 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
395 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
396 .gpu.addr = TPS659038_REG_ADDR_SMPS6,
397 .gpu.pmic = &tps659038,
398 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
399
400 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
401 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
402 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
403 .core.addr = TPS659038_REG_ADDR_SMPS7,
404 .core.pmic = &tps659038,
405
406 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
407 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
408 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
409 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
410 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
411 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
412 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
413 .iva.addr = TPS659038_REG_ADDR_SMPS8,
414 .iva.pmic = &tps659038,
415 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
416 };
417
418 struct vcores_data am571x_idk_volts = {
419 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
420 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
421 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
422 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
423 .mpu.pmic = &tps659038,
424 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
425
426 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
427 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
428 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
429 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
430 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
431 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
432 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
433 .eve.addr = TPS659038_REG_ADDR_SMPS45,
434 .eve.pmic = &tps659038,
435 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
436
437 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
438 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
439 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
440 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
441 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
442 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
443 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
444 .gpu.addr = TPS659038_REG_ADDR_SMPS6,
445 .gpu.pmic = &tps659038,
446 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
447
448 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
449 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
450 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
451 .core.addr = TPS659038_REG_ADDR_SMPS7,
452 .core.pmic = &tps659038,
453
454 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
455 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
456 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
457 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
458 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
459 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
460 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
461 .iva.addr = TPS659038_REG_ADDR_SMPS45,
462 .iva.pmic = &tps659038,
463 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
464 };
465
466 int get_voltrail_opp(int rail_offset)
467 {
468 int opp;
469
470 switch (rail_offset) {
471 case VOLT_MPU:
472 opp = DRA7_MPU_OPP;
473 break;
474 case VOLT_CORE:
475 opp = DRA7_CORE_OPP;
476 break;
477 case VOLT_GPU:
478 opp = DRA7_GPU_OPP;
479 break;
480 case VOLT_EVE:
481 opp = DRA7_DSPEVE_OPP;
482 break;
483 case VOLT_IVA:
484 opp = DRA7_IVA_OPP;
485 break;
486 default:
487 opp = OPP_NOM;
488 }
489
490 return opp;
491 }
492
493
494 #ifdef CONFIG_SPL_BUILD
495 /* No env to setup for SPL */
496 static inline void setup_board_eeprom_env(void) { }
497
498 /* Override function to read eeprom information */
499 void do_board_detect(void)
500 {
501 int rc;
502
503 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
504 CONFIG_EEPROM_CHIP_ADDRESS);
505 if (rc)
506 printf("ti_i2c_eeprom_init failed %d\n", rc);
507 }
508
509 #else /* CONFIG_SPL_BUILD */
510
511 /* Override function to read eeprom information: actual i2c read done by SPL*/
512 void do_board_detect(void)
513 {
514 char *bname = NULL;
515 int rc;
516
517 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
518 CONFIG_EEPROM_CHIP_ADDRESS);
519 if (rc)
520 printf("ti_i2c_eeprom_init failed %d\n", rc);
521
522 if (board_is_x15())
523 bname = "BeagleBoard X15";
524 else if (board_is_am572x_evm())
525 bname = "AM572x EVM";
526 else if (board_is_am574x_idk())
527 bname = "AM574x IDK";
528 else if (board_is_am572x_idk())
529 bname = "AM572x IDK";
530 else if (board_is_am571x_idk())
531 bname = "AM571x IDK";
532
533 if (bname)
534 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
535 "Board: %s REV %s\n", bname, board_ti_get_rev());
536 }
537
538 static void setup_board_eeprom_env(void)
539 {
540 char *name = "beagle_x15";
541 int rc;
542
543 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
544 CONFIG_EEPROM_CHIP_ADDRESS);
545 if (rc)
546 goto invalid_eeprom;
547
548 if (board_is_x15()) {
549 if (board_is_x15_revb1())
550 name = "beagle_x15_revb1";
551 else if (board_is_x15_revc())
552 name = "beagle_x15_revc";
553 else
554 name = "beagle_x15";
555 } else if (board_is_am572x_evm()) {
556 if (board_is_am572x_evm_reva3())
557 name = "am57xx_evm_reva3";
558 else
559 name = "am57xx_evm";
560 } else if (board_is_am574x_idk()) {
561 name = "am574x_idk";
562 } else if (board_is_am572x_idk()) {
563 name = "am572x_idk";
564 } else if (board_is_am571x_idk()) {
565 name = "am571x_idk";
566 } else {
567 printf("Unidentified board claims %s in eeprom header\n",
568 board_ti_get_name());
569 }
570
571 invalid_eeprom:
572 set_board_info_env(name);
573 }
574
575 #endif /* CONFIG_SPL_BUILD */
576
577 void vcores_init(void)
578 {
579 if (board_is_am572x_idk() || board_is_am574x_idk())
580 *omap_vcores = &am572x_idk_volts;
581 else if (board_is_am571x_idk())
582 *omap_vcores = &am571x_idk_volts;
583 else
584 *omap_vcores = &beagle_x15_volts;
585 }
586
587 void hw_data_init(void)
588 {
589 *prcm = &dra7xx_prcm;
590 if (is_dra72x())
591 *dplls_data = &dra72x_dplls;
592 else if (is_dra76x())
593 *dplls_data = &dra76x_dplls;
594 else
595 *dplls_data = &dra7xx_dplls;
596 *ctrl = &dra7xx_ctrl;
597 }
598
599 bool am571x_idk_needs_lcd(void)
600 {
601 bool needs_lcd;
602
603 gpio_request(GPIO_ETH_LCD, "nLCD_Detect");
604 if (gpio_get_value(GPIO_ETH_LCD))
605 needs_lcd = false;
606 else
607 needs_lcd = true;
608
609 gpio_free(GPIO_ETH_LCD);
610
611 return needs_lcd;
612 }
613
614 int board_init(void)
615 {
616 gpmc_init();
617 gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
618
619 return 0;
620 }
621
622 void am57x_idk_lcd_detect(void)
623 {
624 int r = -ENODEV;
625 char *idk_lcd = "no";
626 uint8_t buf = 0;
627
628 /* Only valid for IDKs */
629 if (board_is_x15() || board_is_am572x_evm())
630 return;
631
632 /* Only AM571x IDK has gpio control detect.. so check that */
633 if (board_is_am571x_idk() && !am571x_idk_needs_lcd())
634 goto out;
635
636 r = i2c_set_bus_num(OSD_TS_FT_BUS_ADDRESS);
637 if (r) {
638 printf("%s: Failed to set bus address to %d: %d\n",
639 __func__, OSD_TS_FT_BUS_ADDRESS, r);
640 goto out;
641 }
642 r = i2c_probe(OSD_TS_FT_CHIP_ADDRESS);
643 if (r) {
644 /* AM572x IDK has no explicit settings for optional LCD kit */
645 if (board_is_am571x_idk()) {
646 printf("%s: Touch screen detect failed: %d!\n",
647 __func__, r);
648 }
649 goto out;
650 }
651
652 /* Read FT ID */
653 r = i2c_read(OSD_TS_FT_CHIP_ADDRESS, OSD_TS_FT_REG_ID, 1, &buf, 1);
654 if (r) {
655 printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n",
656 __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
657 OSD_TS_FT_REG_ID, r);
658 goto out;
659 }
660
661 switch (buf) {
662 case OSD_TS_FT_ID_5606:
663 idk_lcd = "osd101t2045";
664 break;
665 case OSD_TS_FT_ID_5x46:
666 idk_lcd = "osd101t2587";
667 break;
668 default:
669 printf("%s: Unidentifed Touch screen ID 0x%02x\n",
670 __func__, buf);
671 /* we will let default be "no lcd" */
672 }
673 out:
674 env_set("idk_lcd", idk_lcd);
675 return;
676 }
677
678 int board_late_init(void)
679 {
680 setup_board_eeprom_env();
681 u8 val;
682
683 /*
684 * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
685 * This is the POWERHOLD-in-Low behavior.
686 */
687 palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
688
689 /*
690 * Default FIT boot on HS devices. Non FIT images are not allowed
691 * on HS devices.
692 */
693 if (get_device_type() == HS_DEVICE)
694 env_set("boot_fit", "1");
695
696 /*
697 * Set the GPIO7 Pad to POWERHOLD. This has higher priority
698 * over DEV_CTRL.DEV_ON bit. This can be reset in case of
699 * PMIC Power off. So to be on the safer side set it back
700 * to POWERHOLD mode irrespective of the current state.
701 */
702 palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
703 &val);
704 val = val | TPS65903X_PAD2_POWERHOLD_MASK;
705 palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
706 val);
707
708 omap_die_id_serial();
709 omap_set_fastboot_vars();
710
711 am57x_idk_lcd_detect();
712
713 #if !defined(CONFIG_SPL_BUILD)
714 board_ti_set_ethaddr(2);
715 #endif
716
717 return 0;
718 }
719
720 void set_muxconf_regs(void)
721 {
722 do_set_mux32((*ctrl)->control_padconf_core_base,
723 early_padconf, ARRAY_SIZE(early_padconf));
724 }
725
726 #ifdef CONFIG_IODELAY_RECALIBRATION
727 void recalibrate_iodelay(void)
728 {
729 const struct pad_conf_entry *pconf;
730 const struct iodelay_cfg_entry *iod, *delta_iod;
731 int pconf_sz, iod_sz, delta_iod_sz = 0;
732 int ret;
733
734 if (board_is_am572x_idk()) {
735 pconf = core_padconf_array_essential_am572x_idk;
736 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
737 iod = iodelay_cfg_array_am572x_idk;
738 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
739 } else if (board_is_am574x_idk()) {
740 pconf = core_padconf_array_essential_am574x_idk;
741 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am574x_idk);
742 iod = iodelay_cfg_array_am574x_idk;
743 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am574x_idk);
744 } else if (board_is_am571x_idk()) {
745 pconf = core_padconf_array_essential_am571x_idk;
746 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
747 iod = iodelay_cfg_array_am571x_idk;
748 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
749 } else {
750 /* Common for X15/GPEVM */
751 pconf = core_padconf_array_essential_x15;
752 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
753 /* There never was an SR1.0 X15.. So.. */
754 if (omap_revision() == DRA752_ES1_1) {
755 iod = iodelay_cfg_array_x15_sr1_1;
756 iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
757 } else {
758 /* Since full production should switch to SR2.0 */
759 iod = iodelay_cfg_array_x15_sr2_0;
760 iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
761 }
762 }
763
764 /* Setup I/O isolation */
765 ret = __recalibrate_iodelay_start();
766 if (ret)
767 goto err;
768
769 /* Do the muxing here */
770 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
771
772 /* Now do the weird minor deltas that should be safe */
773 if (board_is_x15() || board_is_am572x_evm()) {
774 if (board_is_x15_revb1() || board_is_am572x_evm_reva3() ||
775 board_is_x15_revc()) {
776 pconf = core_padconf_array_delta_x15_sr2_0;
777 pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
778 } else {
779 pconf = core_padconf_array_delta_x15_sr1_1;
780 pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
781 }
782 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
783 }
784
785 if (board_is_am571x_idk()) {
786 if (am571x_idk_needs_lcd()) {
787 pconf = core_padconf_array_vout_am571x_idk;
788 pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk);
789 delta_iod = iodelay_cfg_array_am571x_idk_4port;
790 delta_iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk_4port);
791
792 } else {
793 pconf = core_padconf_array_icss1eth_am571x_idk;
794 pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk);
795 }
796 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
797 }
798
799 /* Setup IOdelay configuration */
800 ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
801 if (delta_iod_sz)
802 ret = do_set_iodelay((*ctrl)->iodelay_config_base, delta_iod,
803 delta_iod_sz);
804
805 err:
806 /* Closeup.. remove isolation */
807 __recalibrate_iodelay_end(ret);
808 }
809 #endif
810
811 #if defined(CONFIG_MMC)
812 int board_mmc_init(bd_t *bis)
813 {
814 omap_mmc_init(0, 0, 0, -1, -1);
815 omap_mmc_init(1, 0, 0, -1, -1);
816 return 0;
817 }
818
819 static const struct mmc_platform_fixups am57x_es1_1_mmc1_fixups = {
820 .hw_rev = "rev11",
821 .unsupported_caps = MMC_CAP(MMC_HS_200) |
822 MMC_CAP(UHS_SDR104),
823 .max_freq = 96000000,
824 };
825
826 static const struct mmc_platform_fixups am57x_es1_1_mmc23_fixups = {
827 .hw_rev = "rev11",
828 .unsupported_caps = MMC_CAP(MMC_HS_200) |
829 MMC_CAP(UHS_SDR104) |
830 MMC_CAP(UHS_SDR50),
831 .max_freq = 48000000,
832 };
833
834 const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
835 {
836 switch (omap_revision()) {
837 case DRA752_ES1_0:
838 case DRA752_ES1_1:
839 if (addr == OMAP_HSMMC1_BASE)
840 return &am57x_es1_1_mmc1_fixups;
841 else
842 return &am57x_es1_1_mmc23_fixups;
843 default:
844 return NULL;
845 }
846 }
847 #endif
848
849 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
850 int spl_start_uboot(void)
851 {
852 /* break into full u-boot on 'c' */
853 if (serial_tstc() && serial_getc() == 'c')
854 return 1;
855
856 #ifdef CONFIG_SPL_ENV_SUPPORT
857 env_init();
858 env_load();
859 if (env_get_yesno("boot_os") != 1)
860 return 1;
861 #endif
862
863 return 0;
864 }
865 #endif
866
867 #ifdef CONFIG_USB_DWC3
868 static struct dwc3_device usb_otg_ss2 = {
869 .maximum_speed = USB_SPEED_HIGH,
870 .base = DRA7_USB_OTG_SS2_BASE,
871 .tx_fifo_resize = false,
872 .index = 1,
873 };
874
875 static struct dwc3_omap_device usb_otg_ss2_glue = {
876 .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
877 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
878 .index = 1,
879 };
880
881 static struct ti_usb_phy_device usb_phy2_device = {
882 .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
883 .index = 1,
884 };
885
886 int usb_gadget_handle_interrupts(int index)
887 {
888 u32 status;
889
890 status = dwc3_omap_uboot_interrupt_status(index);
891 if (status)
892 dwc3_uboot_handle_interrupt(index);
893
894 return 0;
895 }
896 #endif /* CONFIG_USB_DWC3 */
897
898 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
899 int board_usb_init(int index, enum usb_init_type init)
900 {
901 enable_usb_clocks(index);
902 switch (index) {
903 case 0:
904 if (init == USB_INIT_DEVICE) {
905 printf("port %d can't be used as device\n", index);
906 disable_usb_clocks(index);
907 return -EINVAL;
908 }
909 break;
910 case 1:
911 if (init == USB_INIT_DEVICE) {
912 #ifdef CONFIG_USB_DWC3
913 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
914 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
915 ti_usb_phy_uboot_init(&usb_phy2_device);
916 dwc3_omap_uboot_init(&usb_otg_ss2_glue);
917 dwc3_uboot_init(&usb_otg_ss2);
918 #endif
919 } else {
920 printf("port %d can't be used as host\n", index);
921 disable_usb_clocks(index);
922 return -EINVAL;
923 }
924
925 break;
926 default:
927 printf("Invalid Controller Index\n");
928 }
929
930 return 0;
931 }
932
933 int board_usb_cleanup(int index, enum usb_init_type init)
934 {
935 #ifdef CONFIG_USB_DWC3
936 switch (index) {
937 case 0:
938 case 1:
939 if (init == USB_INIT_DEVICE) {
940 ti_usb_phy_uboot_exit(index);
941 dwc3_uboot_exit(index);
942 dwc3_omap_uboot_exit(index);
943 }
944 break;
945 default:
946 printf("Invalid Controller Index\n");
947 }
948 #endif
949 disable_usb_clocks(index);
950 return 0;
951 }
952 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
953
954 #ifdef CONFIG_DRIVER_TI_CPSW
955
956 /* Delay value to add to calibrated value */
957 #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
958 #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
959 #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
960 #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
961 #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
962 #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
963 #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
964 #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
965 #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
966 #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
967
968 static void cpsw_control(int enabled)
969 {
970 /* VTP can be added here */
971 }
972
973 static struct cpsw_slave_data cpsw_slaves[] = {
974 {
975 .slave_reg_ofs = 0x208,
976 .sliver_reg_ofs = 0xd80,
977 .phy_addr = 1,
978 },
979 {
980 .slave_reg_ofs = 0x308,
981 .sliver_reg_ofs = 0xdc0,
982 .phy_addr = 2,
983 },
984 };
985
986 static struct cpsw_platform_data cpsw_data = {
987 .mdio_base = CPSW_MDIO_BASE,
988 .cpsw_base = CPSW_BASE,
989 .mdio_div = 0xff,
990 .channels = 8,
991 .cpdma_reg_ofs = 0x800,
992 .slaves = 1,
993 .slave_data = cpsw_slaves,
994 .ale_reg_ofs = 0xd00,
995 .ale_entries = 1024,
996 .host_port_reg_ofs = 0x108,
997 .hw_stats_reg_ofs = 0x900,
998 .bd_ram_ofs = 0x2000,
999 .mac_control = (1 << 5),
1000 .control = cpsw_control,
1001 .host_port_num = 0,
1002 .version = CPSW_CTRL_VERSION_2,
1003 };
1004
1005 static u64 mac_to_u64(u8 mac[6])
1006 {
1007 int i;
1008 u64 addr = 0;
1009
1010 for (i = 0; i < 6; i++) {
1011 addr <<= 8;
1012 addr |= mac[i];
1013 }
1014
1015 return addr;
1016 }
1017
1018 static void u64_to_mac(u64 addr, u8 mac[6])
1019 {
1020 mac[5] = addr;
1021 mac[4] = addr >> 8;
1022 mac[3] = addr >> 16;
1023 mac[2] = addr >> 24;
1024 mac[1] = addr >> 32;
1025 mac[0] = addr >> 40;
1026 }
1027
1028 int board_eth_init(bd_t *bis)
1029 {
1030 int ret;
1031 uint8_t mac_addr[6];
1032 uint32_t mac_hi, mac_lo;
1033 uint32_t ctrl_val;
1034 int i;
1035 u64 mac1, mac2;
1036 u8 mac_addr1[6], mac_addr2[6];
1037 int num_macs;
1038
1039 /* try reading mac address from efuse */
1040 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
1041 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
1042 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
1043 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1044 mac_addr[2] = mac_hi & 0xFF;
1045 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
1046 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
1047 mac_addr[5] = mac_lo & 0xFF;
1048
1049 if (!env_get("ethaddr")) {
1050 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
1051
1052 if (is_valid_ethaddr(mac_addr))
1053 eth_env_set_enetaddr("ethaddr", mac_addr);
1054 }
1055
1056 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
1057 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
1058 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
1059 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1060 mac_addr[2] = mac_hi & 0xFF;
1061 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
1062 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
1063 mac_addr[5] = mac_lo & 0xFF;
1064
1065 if (!env_get("eth1addr")) {
1066 if (is_valid_ethaddr(mac_addr))
1067 eth_env_set_enetaddr("eth1addr", mac_addr);
1068 }
1069
1070 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
1071 ctrl_val |= 0x22;
1072 writel(ctrl_val, (*ctrl)->control_core_control_io1);
1073
1074 /* The phy address for the AM57xx IDK are different than x15 */
1075 if (board_is_am572x_idk() || board_is_am571x_idk() ||
1076 board_is_am574x_idk()) {
1077 cpsw_data.slave_data[0].phy_addr = 0;
1078 cpsw_data.slave_data[1].phy_addr = 1;
1079 }
1080
1081 ret = cpsw_register(&cpsw_data);
1082 if (ret < 0)
1083 printf("Error %d registering CPSW switch\n", ret);
1084
1085 /*
1086 * Export any Ethernet MAC addresses from EEPROM.
1087 * On AM57xx the 2 MAC addresses define the address range
1088 */
1089 board_ti_get_eth_mac_addr(0, mac_addr1);
1090 board_ti_get_eth_mac_addr(1, mac_addr2);
1091
1092 if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
1093 mac1 = mac_to_u64(mac_addr1);
1094 mac2 = mac_to_u64(mac_addr2);
1095
1096 /* must contain an address range */
1097 num_macs = mac2 - mac1 + 1;
1098 /* <= 50 to protect against user programming error */
1099 if (num_macs > 0 && num_macs <= 50) {
1100 for (i = 0; i < num_macs; i++) {
1101 u64_to_mac(mac1 + i, mac_addr);
1102 if (is_valid_ethaddr(mac_addr)) {
1103 eth_env_set_enetaddr_by_index("eth",
1104 i + 2,
1105 mac_addr);
1106 }
1107 }
1108 }
1109 }
1110
1111 return ret;
1112 }
1113 #endif
1114
1115 #ifdef CONFIG_BOARD_EARLY_INIT_F
1116 /* VTT regulator enable */
1117 static inline void vtt_regulator_enable(void)
1118 {
1119 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1120 return;
1121
1122 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
1123 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
1124 }
1125
1126 int board_early_init_f(void)
1127 {
1128 vtt_regulator_enable();
1129 return 0;
1130 }
1131 #endif
1132
1133 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1134 int ft_board_setup(void *blob, bd_t *bd)
1135 {
1136 ft_cpu_setup(blob, bd);
1137
1138 return 0;
1139 }
1140 #endif
1141
1142 #ifdef CONFIG_SPL_LOAD_FIT
1143 int board_fit_config_name_match(const char *name)
1144 {
1145 if (board_is_x15()) {
1146 if (board_is_x15_revb1()) {
1147 if (!strcmp(name, "am57xx-beagle-x15-revb1"))
1148 return 0;
1149 } else if (board_is_x15_revc()) {
1150 if (!strcmp(name, "am57xx-beagle-x15-revc"))
1151 return 0;
1152 } else if (!strcmp(name, "am57xx-beagle-x15")) {
1153 return 0;
1154 }
1155 } else if (board_is_am572x_evm() &&
1156 !strcmp(name, "am57xx-beagle-x15")) {
1157 return 0;
1158 } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
1159 return 0;
1160 } else if (board_is_am574x_idk() && !strcmp(name, "am574x-idk")) {
1161 return 0;
1162 } else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) {
1163 return 0;
1164 }
1165
1166 return -1;
1167 }
1168 #endif
1169
1170 #ifdef CONFIG_TI_SECURE_DEVICE
1171 void board_fit_image_post_process(void **p_image, size_t *p_size)
1172 {
1173 secure_boot_verify_image(p_image, p_size);
1174 }
1175
1176 void board_tee_image_process(ulong tee_image, size_t tee_size)
1177 {
1178 secure_tee_install((u32)tee_image);
1179 }
1180
1181 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
1182 #endif
"Das U-Boot" Source Tree