1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2014 - 2015 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
13 #include <asm/arch/clk.h>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/arch/psu_init_gpl.h>
18 #include <dm/device.h>
19 #include <dm/uclass.h>
21 #include <dwc3-uboot.h>
25 DECLARE_GLOBAL_DATA_PTR
;
27 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
28 static struct udevice
*watchdog_dev
__attribute__((section(".data"))) = NULL
;
31 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
32 !defined(CONFIG_SPL_BUILD)
33 static xilinx_desc zynqmppl
= XILINX_ZYNQMP_DESC
;
40 } zynqmp_devices
[] = {
132 { /* For testing purpose only */
180 int chip_id(unsigned char id
)
185 if (current_el() != 3) {
186 regs
.regs
[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID
;
195 * regs[0][31:0] = status of the operation
196 * regs[0][63:32] = CSU.IDCODE register
197 * regs[1][31:0] = CSU.version register
198 * regs[1][63:32] = CSU.IDCODE2 register
202 regs
.regs
[0] = upper_32_bits(regs
.regs
[0]);
203 regs
.regs
[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK
|
204 ZYNQMP_CSU_IDCODE_SVD_MASK
;
205 regs
.regs
[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT
;
209 regs
.regs
[1] = lower_32_bits(regs
.regs
[1]);
210 regs
.regs
[1] &= ZYNQMP_CSU_SILICON_VER_MASK
;
214 regs
.regs
[1] = lower_32_bits(regs
.regs
[1]);
215 regs
.regs
[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT
;
219 printf("%s, Invalid Req:0x%x\n", __func__
, id
);
224 val
= readl(ZYNQMP_CSU_IDCODE_ADDR
);
225 val
&= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK
|
226 ZYNQMP_CSU_IDCODE_SVD_MASK
;
227 val
>>= ZYNQMP_CSU_IDCODE_SVD_SHIFT
;
230 val
= readl(ZYNQMP_CSU_VER_ADDR
);
231 val
&= ZYNQMP_CSU_SILICON_VER_MASK
;
234 printf("%s, Invalid Req:0x%x\n", __func__
, id
);
241 #define ZYNQMP_VERSION_SIZE 9
242 #define ZYNQMP_PL_STATUS_BIT 9
243 #define ZYNQMP_IPDIS_VCU_BIT 8
244 #define ZYNQMP_PL_STATUS_MASK BIT(ZYNQMP_PL_STATUS_BIT)
245 #define ZYNQMP_CSU_VERSION_MASK ~(ZYNQMP_PL_STATUS_MASK)
246 #define ZYNQMP_CSU_VCUDIS_VER_MASK ZYNQMP_CSU_VERSION_MASK & \
247 ~BIT(ZYNQMP_IPDIS_VCU_BIT)
248 #define MAX_VARIANTS_EV 3
250 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
251 !defined(CONFIG_SPL_BUILD)
252 static char *zynqmp_get_silicon_idcode_name(void)
256 static char name
[ZYNQMP_VERSION_SIZE
];
258 id
= chip_id(IDCODE
);
259 ver
= chip_id(IDCODE2
);
261 for (i
= 0; i
< ARRAY_SIZE(zynqmp_devices
); i
++) {
262 if (zynqmp_devices
[i
].id
== id
) {
263 if (zynqmp_devices
[i
].evexists
&&
264 !(ver
& ZYNQMP_PL_STATUS_MASK
))
266 if (zynqmp_devices
[i
].ver
== (ver
&
267 ZYNQMP_CSU_VERSION_MASK
))
272 if (i
>= ARRAY_SIZE(zynqmp_devices
))
275 strncat(name
, "zu", 2);
276 if (!zynqmp_devices
[i
].evexists
||
277 (ver
& ZYNQMP_PL_STATUS_MASK
)) {
278 strncat(name
, zynqmp_devices
[i
].name
,
279 ZYNQMP_VERSION_SIZE
- 3);
284 * Here we are means, PL not powered up and ev variant
285 * exists. So, we need to ignore VCU disable bit(8) in
286 * version and findout if its CG or EG/EV variant.
288 for (j
= 0; j
< MAX_VARIANTS_EV
; j
++, i
++) {
289 if ((zynqmp_devices
[i
].ver
& ~BIT(ZYNQMP_IPDIS_VCU_BIT
)) ==
290 (ver
& ZYNQMP_CSU_VCUDIS_VER_MASK
)) {
291 strncat(name
, zynqmp_devices
[i
].name
,
292 ZYNQMP_VERSION_SIZE
- 3);
297 if (j
>= MAX_VARIANTS_EV
)
300 if (strstr(name
, "eg") || strstr(name
, "ev")) {
301 buf
= strstr(name
, "e");
309 int board_early_init_f(void)
312 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
315 pm_api_version
= zynqmp_pmufw_version();
316 printf("PMUFW:\tv%d.%d\n",
317 pm_api_version
>> ZYNQMP_PM_VERSION_MAJOR_SHIFT
,
318 pm_api_version
& ZYNQMP_PM_VERSION_MINOR_MASK
);
320 if (pm_api_version
< ZYNQMP_PM_VERSION
)
321 panic("PMUFW version error. Expected: v%d.%d\n",
322 ZYNQMP_PM_VERSION_MAJOR
, ZYNQMP_PM_VERSION_MINOR
);
325 #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
334 printf("EL Level:\tEL%d\n", current_el());
336 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
337 !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
338 defined(CONFIG_SPL_BUILD))
339 if (current_el() != 3) {
340 zynqmppl
.name
= zynqmp_get_silicon_idcode_name();
341 printf("Chip ID:\t%s\n", zynqmppl
.name
);
343 fpga_add(fpga_xilinx
, &zynqmppl
);
347 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
348 if (uclass_get_device_by_seq(UCLASS_WDT
, 0, &watchdog_dev
)) {
349 debug("Watchdog: Not found by seq!\n");
350 if (uclass_get_device(UCLASS_WDT
, 0, &watchdog_dev
)) {
351 puts("Watchdog: Not found!\n");
356 wdt_start(watchdog_dev
, 0, 0);
357 puts("Watchdog: Started\n");
363 #ifdef CONFIG_WATCHDOG
364 /* Called by macro WATCHDOG_RESET */
365 void watchdog_reset(void)
367 # if !defined(CONFIG_SPL_BUILD)
368 static ulong next_reset
;
374 now
= timer_get_us();
376 /* Do not reset the watchdog too often */
377 if (now
> next_reset
) {
378 wdt_reset(watchdog_dev
);
379 next_reset
= now
+ 1000;
385 int board_early_init_r(void)
389 if (current_el() != 3)
392 val
= readl(&crlapb_base
->timestamp_ref_ctrl
);
393 val
&= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT
;
396 val
= readl(&crlapb_base
->timestamp_ref_ctrl
);
397 val
|= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT
;
398 writel(val
, &crlapb_base
->timestamp_ref_ctrl
);
400 /* Program freq register in System counter */
401 writel(zynqmp_get_system_timer_freq(),
402 &iou_scntr_secure
->base_frequency_id_register
);
403 /* And enable system counter */
404 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN
,
405 &iou_scntr_secure
->counter_control_register
);
410 unsigned long do_go_exec(ulong (*entry
)(int, char * const []), int argc
,
415 if (current_el() > 1) {
418 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry
,
421 printf("FAIL: current EL is not above EL1\n");
427 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
428 int dram_init_banksize(void)
432 ret
= fdtdec_setup_memory_banksize();
443 if (fdtdec_setup_mem_size_base() != 0)
449 int dram_init_banksize(void)
451 #if defined(CONFIG_NR_DRAM_BANKS)
452 gd
->bd
->bi_dram
[0].start
= CONFIG_SYS_SDRAM_BASE
;
453 gd
->bd
->bi_dram
[0].size
= get_effective_memsize();
463 gd
->ram_size
= get_ram_size((void *)CONFIG_SYS_SDRAM_BASE
,
464 CONFIG_SYS_SDRAM_SIZE
);
470 void reset_cpu(ulong addr
)
474 #if defined(CONFIG_BOARD_LATE_INIT)
475 static const struct {
478 } reset_reasons
[] = {
479 { RESET_REASON_DEBUG_SYS
, "DEBUG" },
480 { RESET_REASON_SOFT
, "SOFT" },
481 { RESET_REASON_SRST
, "SRST" },
482 { RESET_REASON_PSONLY
, "PS-ONLY" },
483 { RESET_REASON_PMU
, "PMU" },
484 { RESET_REASON_INTERNAL
, "INTERNAL" },
485 { RESET_REASON_EXTERNAL
, "EXTERNAL" },
489 static int reset_reason(void)
493 const char *reason
= NULL
;
495 ret
= zynqmp_mmio_read((ulong
)&crlapb_base
->reset_reason
, ®
);
499 puts("Reset reason:\t");
501 for (i
= 0; i
< ARRAY_SIZE(reset_reasons
); i
++) {
502 if (reg
& reset_reasons
[i
].bit
) {
503 reason
= reset_reasons
[i
].name
;
504 printf("%s ", reset_reasons
[i
].name
);
511 env_set("reset_reason", reason
);
513 ret
= zynqmp_mmio_write(~0, ~0, (ulong
)&crlapb_base
->reset_reason
);
520 static int set_fdtfile(void)
522 char *compatible
, *fdtfile
;
523 const char *suffix
= ".dtb";
524 const char *vendor
= "xilinx/";
526 if (env_get("fdtfile"))
529 compatible
= (char *)fdt_getprop(gd
->fdt_blob
, 0, "compatible", NULL
);
531 debug("Compatible: %s\n", compatible
);
533 /* Discard vendor prefix */
534 strsep(&compatible
, ",");
536 fdtfile
= calloc(1, strlen(vendor
) + strlen(compatible
) +
541 sprintf(fdtfile
, "%s%s%s", vendor
, compatible
, suffix
);
543 env_set("fdtfile", fdtfile
);
550 int board_late_init(void)
557 int env_targets_len
= 0;
563 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
567 if (!(gd
->flags
& GD_FLG_ENV_DEFAULT
)) {
568 debug("Saved variables - Skipping\n");
576 ret
= zynqmp_mmio_read((ulong
)&crlapb_base
->boot_mode
, ®
);
580 if (reg
>> BOOT_MODE_ALT_SHIFT
)
581 reg
>>= BOOT_MODE_ALT_SHIFT
;
583 bootmode
= reg
& BOOT_MODES_MASK
;
590 env_set("modeboot", "usb_dfu_spl");
595 env_set("modeboot", "jtagboot");
597 case QSPI_MODE_24BIT
:
598 case QSPI_MODE_32BIT
:
601 env_set("modeboot", "qspiboot");
606 env_set("modeboot", "emmcboot");
610 if (uclass_get_device_by_name(UCLASS_MMC
,
611 "mmc@ff160000", &dev
) &&
612 uclass_get_device_by_name(UCLASS_MMC
,
613 "sdhci@ff160000", &dev
)) {
614 puts("Boot from SD0 but without SD0 enabled!\n");
617 debug("mmc0 device found at %p, seq %d\n", dev
, dev
->seq
);
621 env_set("modeboot", "sdboot");
628 if (uclass_get_device_by_name(UCLASS_MMC
,
629 "mmc@ff170000", &dev
) &&
630 uclass_get_device_by_name(UCLASS_MMC
,
631 "sdhci@ff170000", &dev
)) {
632 puts("Boot from SD1 but without SD1 enabled!\n");
635 debug("mmc1 device found at %p, seq %d\n", dev
, dev
->seq
);
639 env_set("modeboot", "sdboot");
644 env_set("modeboot", "nandboot");
648 printf("Invalid Boot Mode:0x%x\n", bootmode
);
653 bootseq_len
= snprintf(NULL
, 0, "%i", bootseq
);
654 debug("Bootseq len: %x\n", bootseq_len
);
658 * One terminating char + one byte for space between mode
659 * and default boot_targets
661 env_targets
= env_get("boot_targets");
663 env_targets_len
= strlen(env_targets
);
665 new_targets
= calloc(1, strlen(mode
) + env_targets_len
+ 2 +
671 sprintf(new_targets
, "%s%x %s", mode
, bootseq
,
672 env_targets
? env_targets
: "");
674 sprintf(new_targets
, "%s %s", mode
,
675 env_targets
? env_targets
: "");
677 env_set("boot_targets", new_targets
);
687 puts("Board: Xilinx ZynqMP\n");