board/xilinx/zynqmp/zynqmp.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   4  * Michal Simek <michal.simek@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <sata.h>
   9 #include <ahci.h>
  10 #include <scsi.h>
  11 #include <malloc.h>
  12 #include <wdt.h>
  13 #include <asm/arch/clk.h>
  14 #include <asm/arch/hardware.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/arch/psu_init_gpl.h>
  17 #include <asm/io.h>
  18 #include <dm/device.h>
  19 #include <dm/uclass.h>
  20 #include <usb.h>
  21 #include <dwc3-uboot.h>
  22 #include <zynqmppl.h>
  23 #include <i2c.h>
  24 #include <g_dnl.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
  29 static struct udevice *watchdog_dev;
  30 #endif
  31
  32 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
  33     !defined(CONFIG_SPL_BUILD)
  34 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
  35
  36 static const struct {
  37         u32 id;
  38         u32 ver;
  39         char *name;
  40         bool evexists;
  41 } zynqmp_devices[] = {
  42         {
  43                 .id = 0x10,
  44                 .name = "3eg",
  45         },
  46         {
  47                 .id = 0x10,
  48                 .ver = 0x2c,
  49                 .name = "3cg",
  50         },
  51         {
  52                 .id = 0x11,
  53                 .name = "2eg",
  54         },
  55         {
  56                 .id = 0x11,
  57                 .ver = 0x2c,
  58                 .name = "2cg",
  59         },
  60         {
  61                 .id = 0x20,
  62                 .name = "5ev",
  63                 .evexists = 1,
  64         },
  65         {
  66                 .id = 0x20,
  67                 .ver = 0x100,
  68                 .name = "5eg",
  69                 .evexists = 1,
  70         },
  71         {
  72                 .id = 0x20,
  73                 .ver = 0x12c,
  74                 .name = "5cg",
  75         },
  76         {
  77                 .id = 0x21,
  78                 .name = "4ev",
  79                 .evexists = 1,
  80         },
  81         {
  82                 .id = 0x21,
  83                 .ver = 0x100,
  84                 .name = "4eg",
  85                 .evexists = 1,
  86         },
  87         {
  88                 .id = 0x21,
  89                 .ver = 0x12c,
  90                 .name = "4cg",
  91         },
  92         {
  93                 .id = 0x30,
  94                 .name = "7ev",
  95                 .evexists = 1,
  96         },
  97         {
  98                 .id = 0x30,
  99                 .ver = 0x100,
 100                 .name = "7eg",
 101                 .evexists = 1,
 102         },
 103         {
 104                 .id = 0x30,
 105                 .ver = 0x12c,
 106                 .name = "7cg",
 107         },
 108         {
 109                 .id = 0x38,
 110                 .name = "9eg",
 111         },
 112         {
 113                 .id = 0x38,
 114                 .ver = 0x2c,
 115                 .name = "9cg",
 116         },
 117         {
 118                 .id = 0x39,
 119                 .name = "6eg",
 120         },
 121         {
 122                 .id = 0x39,
 123                 .ver = 0x2c,
 124                 .name = "6cg",
 125         },
 126         {
 127                 .id = 0x40,
 128                 .name = "11eg",
 129         },
 130         { /* For testing purpose only */
 131                 .id = 0x50,
 132                 .ver = 0x2c,
 133                 .name = "15cg",
 134         },
 135         {
 136                 .id = 0x50,
 137                 .name = "15eg",
 138         },
 139         {
 140                 .id = 0x58,
 141                 .name = "19eg",
 142         },
 143         {
 144                 .id = 0x59,
 145                 .name = "17eg",
 146         },
 147         {
 148                 .id = 0x61,
 149                 .name = "21dr",
 150         },
 151         {
 152                 .id = 0x63,
 153                 .name = "23dr",
 154         },
 155         {
 156                 .id = 0x65,
 157                 .name = "25dr",
 158         },
 159         {
 160                 .id = 0x64,
 161                 .name = "27dr",
 162         },
 163         {
 164                 .id = 0x60,
 165                 .name = "28dr",
 166         },
 167         {
 168                 .id = 0x62,
 169                 .name = "29dr",
 170         },
 171 };
 172 #endif
 173
 174 int chip_id(unsigned char id)
 175 {
 176         struct pt_regs regs;
 177         int val = -EINVAL;
 178
 179         if (current_el() != 3) {
 180                 regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
 181                 regs.regs[1] = 0;
 182                 regs.regs[2] = 0;
 183                 regs.regs[3] = 0;
 184
 185                 smc_call(&regs);
 186
 187                 /*
 188                  * SMC returns:
 189                  * regs[0][31:0]  = status of the operation
 190                  * regs[0][63:32] = CSU.IDCODE register
 191                  * regs[1][31:0]  = CSU.version register
 192                  * regs[1][63:32] = CSU.IDCODE2 register
 193                  */
 194                 switch (id) {
 195                 case IDCODE:
 196                         regs.regs[0] = upper_32_bits(regs.regs[0]);
 197                         regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
 198                                         ZYNQMP_CSU_IDCODE_SVD_MASK;
 199                         regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 200                         val = regs.regs[0];
 201                         break;
 202                 case VERSION:
 203                         regs.regs[1] = lower_32_bits(regs.regs[1]);
 204                         regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
 205                         val = regs.regs[1];
 206                         break;
 207                 case IDCODE2:
 208                         regs.regs[1] = lower_32_bits(regs.regs[1]);
 209                         regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
 210                         val = regs.regs[1];
 211                         break;
 212                 default:
 213                         printf("%s, Invalid Req:0x%x\n", __func__, id);
 214                 }
 215         } else {
 216                 switch (id) {
 217                 case IDCODE:
 218                         val = readl(ZYNQMP_CSU_IDCODE_ADDR);
 219                         val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
 220                                ZYNQMP_CSU_IDCODE_SVD_MASK;
 221                         val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 222                         break;
 223                 case VERSION:
 224                         val = readl(ZYNQMP_CSU_VER_ADDR);
 225                         val &= ZYNQMP_CSU_SILICON_VER_MASK;
 226                         break;
 227                 default:
 228                         printf("%s, Invalid Req:0x%x\n", __func__, id);
 229                 }
 230         }
 231
 232         return val;
 233 }
 234
 235 #define ZYNQMP_VERSION_SIZE             9
 236 #define ZYNQMP_PL_STATUS_BIT            9
 237 #define ZYNQMP_PL_STATUS_MASK           BIT(ZYNQMP_PL_STATUS_BIT)
 238 #define ZYNQMP_CSU_VERSION_MASK         ~(ZYNQMP_PL_STATUS_MASK)
 239
 240 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 241         !defined(CONFIG_SPL_BUILD)
 242 static char *zynqmp_get_silicon_idcode_name(void)
 243 {
 244         u32 i, id, ver;
 245         char *buf;
 246         static char name[ZYNQMP_VERSION_SIZE];
 247
 248         id = chip_id(IDCODE);
 249         ver = chip_id(IDCODE2);
 250
 251         for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
 252                 if ((zynqmp_devices[i].id == id) &&
 253                     (zynqmp_devices[i].ver == (ver &
 254                     ZYNQMP_CSU_VERSION_MASK))) {
 255                         strncat(name, "zu", 2);
 256                         strncat(name, zynqmp_devices[i].name,
 257                                 ZYNQMP_VERSION_SIZE - 3);
 258                         break;
 259                 }
 260         }
 261
 262         if (i >= ARRAY_SIZE(zynqmp_devices))
 263                 return "unknown";
 264
 265         if (!zynqmp_devices[i].evexists)
 266                 return name;
 267
 268         if (ver & ZYNQMP_PL_STATUS_MASK)
 269                 return name;
 270
 271         if (strstr(name, "eg") || strstr(name, "ev")) {
 272                 buf = strstr(name, "e");
 273                 *buf = '\0';
 274         }
 275
 276         return name;
 277 }
 278 #endif
 279
 280 int board_early_init_f(void)
 281 {
 282         int ret = 0;
 283 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
 284         zynqmp_pmufw_version();
 285 #endif
 286
 287 #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
 288         ret = psu_init();
 289 #endif
 290
 291 #if defined(CONFIG_WDT) && !defined(CONFIG_SPL_BUILD)
 292         /* bss is not cleared at time when watchdog_reset() is called */
 293         watchdog_dev = NULL;
 294 #endif
 295
 296         return ret;
 297 }
 298
 299 int board_init(void)
 300 {
 301         printf("EL Level:\tEL%d\n", current_el());
 302
 303 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 304     !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
 305     defined(CONFIG_SPL_BUILD))
 306         if (current_el() != 3) {
 307                 zynqmppl.name = zynqmp_get_silicon_idcode_name();
 308                 printf("Chip ID:\t%s\n", zynqmppl.name);
 309                 fpga_init();
 310                 fpga_add(fpga_xilinx, &zynqmppl);
 311         }
 312 #endif
 313
 314 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
 315         if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
 316                 puts("Watchdog: Not found!\n");
 317         } else {
 318                 wdt_start(watchdog_dev, 0, 0);
 319                 puts("Watchdog: Started\n");
 320         }
 321 #endif
 322
 323         return 0;
 324 }
 325
 326 #ifdef CONFIG_WATCHDOG
 327 /* Called by macro WATCHDOG_RESET */
 328 void watchdog_reset(void)
 329 {
 330 # if !defined(CONFIG_SPL_BUILD)
 331         static ulong next_reset;
 332         ulong now;
 333
 334         if (!watchdog_dev)
 335                 return;
 336
 337         now = timer_get_us();
 338
 339         /* Do not reset the watchdog too often */
 340         if (now > next_reset) {
 341                 wdt_reset(watchdog_dev);
 342                 next_reset = now + 1000;
 343         }
 344 # endif
 345 }
 346 #endif
 347
 348 int board_early_init_r(void)
 349 {
 350         u32 val;
 351
 352         if (current_el() != 3)
 353                 return 0;
 354
 355         val = readl(&crlapb_base->timestamp_ref_ctrl);
 356         val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 357
 358         if (!val) {
 359                 val = readl(&crlapb_base->timestamp_ref_ctrl);
 360                 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 361                 writel(val, &crlapb_base->timestamp_ref_ctrl);
 362
 363                 /* Program freq register in System counter */
 364                 writel(zynqmp_get_system_timer_freq(),
 365                        &iou_scntr_secure->base_frequency_id_register);
 366                 /* And enable system counter */
 367                 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
 368                        &iou_scntr_secure->counter_control_register);
 369         }
 370         return 0;
 371 }
 372
 373 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 374 {
 375 #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
 376     defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
 377     defined(CONFIG_ZYNQ_EEPROM_BUS)
 378         i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS);
 379
 380         if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
 381                         CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
 382                         ethaddr, 6))
 383                 printf("I2C EEPROM MAC address read failed\n");
 384 #endif
 385
 386         return 0;
 387 }
 388
 389 unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
 390                          char * const argv[])
 391 {
 392         int ret = 0;
 393
 394         if (current_el() > 1) {
 395                 smp_kick_all_cpus();
 396                 dcache_disable();
 397                 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
 398                                     ES_TO_AARCH64);
 399         } else {
 400                 printf("FAIL: current EL is not above EL1\n");
 401                 ret = EINVAL;
 402         }
 403         return ret;
 404 }
 405
 406 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
 407 int dram_init_banksize(void)
 408 {
 409         int ret;
 410
 411         ret = fdtdec_setup_memory_banksize();
 412         if (ret)
 413                 return ret;
 414
 415         mem_map_fill();
 416
 417         return 0;
 418 }
 419
 420 int dram_init(void)
 421 {
 422         if (fdtdec_setup_memory_size() != 0)
 423                 return -EINVAL;
 424
 425         return 0;
 426 }
 427 #else
 428 int dram_init_banksize(void)
 429 {
 430 #if defined(CONFIG_NR_DRAM_BANKS)
 431         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 432         gd->bd->bi_dram[0].size = get_effective_memsize();
 433 #endif
 434
 435         mem_map_fill();
 436
 437         return 0;
 438 }
 439
 440 int dram_init(void)
 441 {
 442         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 443                                     CONFIG_SYS_SDRAM_SIZE);
 444
 445         return 0;
 446 }
 447 #endif
 448
 449 void reset_cpu(ulong addr)
 450 {
 451 }
 452
 453 static const struct {
 454         u32 bit;
 455         const char *name;
 456 } reset_reasons[] = {
 457         { RESET_REASON_DEBUG_SYS, "DEBUG" },
 458         { RESET_REASON_SOFT, "SOFT" },
 459         { RESET_REASON_SRST, "SRST" },
 460         { RESET_REASON_PSONLY, "PS-ONLY" },
 461         { RESET_REASON_PMU, "PMU" },
 462         { RESET_REASON_INTERNAL, "INTERNAL" },
 463         { RESET_REASON_EXTERNAL, "EXTERNAL" },
 464         {}
 465 };
 466
 467 static u32 reset_reason(void)
 468 {
 469         u32 ret;
 470         int i;
 471         const char *reason = NULL;
 472
 473         ret = readl(&crlapb_base->reset_reason);
 474
 475         puts("Reset reason:\t");
 476
 477         for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
 478                 if (ret & reset_reasons[i].bit) {
 479                         reason = reset_reasons[i].name;
 480                         printf("%s ", reset_reasons[i].name);
 481                         break;
 482                 }
 483         }
 484
 485         puts("\n");
 486
 487         env_set("reset_reason", reason);
 488
 489         writel(~0, &crlapb_base->reset_reason);
 490
 491         return ret;
 492 }
 493
 494 int board_late_init(void)
 495 {
 496         u32 reg = 0;
 497         u8 bootmode;
 498         struct udevice *dev;
 499         int bootseq = -1;
 500         int bootseq_len = 0;
 501         int env_targets_len = 0;
 502         const char *mode;
 503         char *new_targets;
 504         char *env_targets;
 505         int ret;
 506
 507         if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
 508                 debug("Saved variables - Skipping\n");
 509                 return 0;
 510         }
 511
 512         ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
 513         if (ret)
 514                 return -EINVAL;
 515
 516         if (reg >> BOOT_MODE_ALT_SHIFT)
 517                 reg >>= BOOT_MODE_ALT_SHIFT;
 518
 519         bootmode = reg & BOOT_MODES_MASK;
 520
 521         puts("Bootmode: ");
 522         switch (bootmode) {
 523         case USB_MODE:
 524                 puts("USB_MODE\n");
 525                 mode = "usb";
 526                 env_set("modeboot", "usb_dfu_spl");
 527                 break;
 528         case JTAG_MODE:
 529                 puts("JTAG_MODE\n");
 530                 mode = "pxe dhcp";
 531                 env_set("modeboot", "jtagboot");
 532                 break;
 533         case QSPI_MODE_24BIT:
 534         case QSPI_MODE_32BIT:
 535                 mode = "qspi0";
 536                 puts("QSPI_MODE\n");
 537                 env_set("modeboot", "qspiboot");
 538                 break;
 539         case EMMC_MODE:
 540                 puts("EMMC_MODE\n");
 541                 mode = "mmc0";
 542                 env_set("modeboot", "emmcboot");
 543                 break;
 544         case SD_MODE:
 545                 puts("SD_MODE\n");
 546                 if (uclass_get_device_by_name(UCLASS_MMC,
 547                                               "sdhci@ff160000", &dev)) {
 548                         puts("Boot from SD0 but without SD0 enabled!\n");
 549                         return -1;
 550                 }
 551                 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
 552
 553                 mode = "mmc";
 554                 bootseq = dev->seq;
 555                 env_set("modeboot", "sdboot");
 556                 break;
 557         case SD1_LSHFT_MODE:
 558                 puts("LVL_SHFT_");
 559                 /* fall through */
 560         case SD_MODE1:
 561                 puts("SD_MODE1\n");
 562                 if (uclass_get_device_by_name(UCLASS_MMC,
 563                                               "sdhci@ff170000", &dev)) {
 564                         puts("Boot from SD1 but without SD1 enabled!\n");
 565                         return -1;
 566                 }
 567                 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
 568
 569                 mode = "mmc";
 570                 bootseq = dev->seq;
 571                 env_set("modeboot", "sdboot");
 572                 break;
 573         case NAND_MODE:
 574                 puts("NAND_MODE\n");
 575                 mode = "nand0";
 576                 env_set("modeboot", "nandboot");
 577                 break;
 578         default:
 579                 mode = "";
 580                 printf("Invalid Boot Mode:0x%x\n", bootmode);
 581                 break;
 582         }
 583
 584         if (bootseq >= 0) {
 585                 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
 586                 debug("Bootseq len: %x\n", bootseq_len);
 587         }
 588
 589         /*
 590          * One terminating char + one byte for space between mode
 591          * and default boot_targets
 592          */
 593         env_targets = env_get("boot_targets");
 594         if (env_targets)
 595                 env_targets_len = strlen(env_targets);
 596
 597         new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
 598                              bootseq_len);
 599
 600         if (bootseq >= 0)
 601                 sprintf(new_targets, "%s%x %s", mode, bootseq,
 602                         env_targets ? env_targets : "");
 603         else
 604                 sprintf(new_targets, "%s %s", mode,
 605                         env_targets ? env_targets : "");
 606
 607         env_set("boot_targets", new_targets);
 608
 609         reset_reason();
 610
 611         return 0;
 612 }
 613
 614 int checkboard(void)
 615 {
 616         puts("Board: Xilinx ZynqMP\n");
 617         return 0;
 618 }