board/xilinx/zynqmp/zynqmp.c

   1 /*
   2  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   3  * Michal Simek <michal.simek@xilinx.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <sata.h>
  10 #include <ahci.h>
  11 #include <scsi.h>
  12 #include <malloc.h>
  13 #include <asm/arch/clk.h>
  14 #include <asm/arch/hardware.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/io.h>
  17 #include <usb.h>
  18 #include <dwc3-uboot.h>
  19 #include <zynqmppl.h>
  20 #include <i2c.h>
  21 #include <g_dnl.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
  26     !defined(CONFIG_SPL_BUILD)
  27 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
  28
  29 static const struct {
  30         u32 id;
  31         u32 ver;
  32         char *name;
  33 } zynqmp_devices[] = {
  34         {
  35                 .id = 0x10,
  36                 .name = "3eg",
  37         },
  38         {
  39                 .id = 0x10,
  40                 .ver = 0x2c,
  41                 .name = "3cg",
  42         },
  43         {
  44                 .id = 0x11,
  45                 .name = "2eg",
  46         },
  47         {
  48                 .id = 0x11,
  49                 .ver = 0x2c,
  50                 .name = "2cg",
  51         },
  52         {
  53                 .id = 0x20,
  54                 .name = "5ev",
  55         },
  56         {
  57                 .id = 0x20,
  58                 .ver = 0x100,
  59                 .name = "5eg",
  60         },
  61         {
  62                 .id = 0x20,
  63                 .ver = 0x12c,
  64                 .name = "5cg",
  65         },
  66         {
  67                 .id = 0x21,
  68                 .name = "4ev",
  69         },
  70         {
  71                 .id = 0x21,
  72                 .ver = 0x100,
  73                 .name = "4eg",
  74         },
  75         {
  76                 .id = 0x21,
  77                 .ver = 0x12c,
  78                 .name = "4cg",
  79         },
  80         {
  81                 .id = 0x30,
  82                 .name = "7ev",
  83         },
  84         {
  85                 .id = 0x30,
  86                 .ver = 0x100,
  87                 .name = "7eg",
  88         },
  89         {
  90                 .id = 0x30,
  91                 .ver = 0x12c,
  92                 .name = "7cg",
  93         },
  94         {
  95                 .id = 0x38,
  96                 .name = "9eg",
  97         },
  98         {
  99                 .id = 0x38,
 100                 .ver = 0x2c,
 101                 .name = "9cg",
 102         },
 103         {
 104                 .id = 0x39,
 105                 .name = "6eg",
 106         },
 107         {
 108                 .id = 0x39,
 109                 .ver = 0x2c,
 110                 .name = "6cg",
 111         },
 112         {
 113                 .id = 0x40,
 114                 .name = "11eg",
 115         },
 116         { /* For testing purpose only */
 117                 .id = 0x50,
 118                 .ver = 0x2c,
 119                 .name = "15cg",
 120         },
 121         {
 122                 .id = 0x50,
 123                 .name = "15eg",
 124         },
 125         {
 126                 .id = 0x58,
 127                 .name = "19eg",
 128         },
 129         {
 130                 .id = 0x59,
 131                 .name = "17eg",
 132         },
 133         {
 134                 .id = 0x61,
 135                 .name = "21dr",
 136         },
 137         {
 138                 .id = 0x63,
 139                 .name = "23dr",
 140         },
 141         {
 142                 .id = 0x65,
 143                 .name = "25dr",
 144         },
 145         {
 146                 .id = 0x64,
 147                 .name = "27dr",
 148         },
 149         {
 150                 .id = 0x60,
 151                 .name = "28dr",
 152         },
 153         {
 154                 .id = 0x62,
 155                 .name = "29dr",
 156         },
 157 };
 158 #endif
 159
 160 int chip_id(unsigned char id)
 161 {
 162         struct pt_regs regs;
 163         int val = -EINVAL;
 164
 165         if (current_el() != 3) {
 166                 regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
 167                 regs.regs[1] = 0;
 168                 regs.regs[2] = 0;
 169                 regs.regs[3] = 0;
 170
 171                 smc_call(&regs);
 172
 173                 /*
 174                  * SMC returns:
 175                  * regs[0][31:0]  = status of the operation
 176                  * regs[0][63:32] = CSU.IDCODE register
 177                  * regs[1][31:0]  = CSU.version register
 178                  * regs[1][63:32] = CSU.IDCODE2 register
 179                  */
 180                 switch (id) {
 181                 case IDCODE:
 182                         regs.regs[0] = upper_32_bits(regs.regs[0]);
 183                         regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
 184                                         ZYNQMP_CSU_IDCODE_SVD_MASK;
 185                         regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 186                         val = regs.regs[0];
 187                         break;
 188                 case VERSION:
 189                         regs.regs[1] = lower_32_bits(regs.regs[1]);
 190                         regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
 191                         val = regs.regs[1];
 192                         break;
 193                 case IDCODE2:
 194                         regs.regs[1] = lower_32_bits(regs.regs[1]);
 195                         regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
 196                         val = regs.regs[1];
 197                         break;
 198                 default:
 199                         printf("%s, Invalid Req:0x%x\n", __func__, id);
 200                 }
 201         } else {
 202                 switch (id) {
 203                 case IDCODE:
 204                         val = readl(ZYNQMP_CSU_IDCODE_ADDR);
 205                         val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
 206                                ZYNQMP_CSU_IDCODE_SVD_MASK;
 207                         val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 208                         break;
 209                 case VERSION:
 210                         val = readl(ZYNQMP_CSU_VER_ADDR);
 211                         val &= ZYNQMP_CSU_SILICON_VER_MASK;
 212                         break;
 213                 default:
 214                         printf("%s, Invalid Req:0x%x\n", __func__, id);
 215                 }
 216         }
 217
 218         return val;
 219 }
 220
 221 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 222         !defined(CONFIG_SPL_BUILD)
 223 static char *zynqmp_get_silicon_idcode_name(void)
 224 {
 225         u32 i, id, ver;
 226
 227         id = chip_id(IDCODE);
 228         ver = chip_id(IDCODE2);
 229
 230         for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
 231                 if (zynqmp_devices[i].id == id && zynqmp_devices[i].ver == ver)
 232                         return zynqmp_devices[i].name;
 233         }
 234         return "unknown";
 235 }
 236 #endif
 237
 238 int board_early_init_f(void)
 239 {
 240         int ret = 0;
 241 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
 242         zynqmp_pmufw_version();
 243 #endif
 244
 245 #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
 246         ret = psu_init();
 247 #endif
 248
 249         return ret;
 250 }
 251
 252 #define ZYNQMP_VERSION_SIZE     9
 253
 254 int board_init(void)
 255 {
 256         printf("EL Level:\tEL%d\n", current_el());
 257
 258 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 259     !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
 260     defined(CONFIG_SPL_BUILD))
 261         if (current_el() != 3) {
 262                 static char version[ZYNQMP_VERSION_SIZE];
 263
 264                 strncat(version, "zu", 2);
 265                 zynqmppl.name = strncat(version,
 266                                         zynqmp_get_silicon_idcode_name(),
 267                                         ZYNQMP_VERSION_SIZE - 3);
 268                 printf("Chip ID:\t%s\n", zynqmppl.name);
 269                 fpga_init();
 270                 fpga_add(fpga_xilinx, &zynqmppl);
 271         }
 272 #endif
 273
 274         return 0;
 275 }
 276
 277 int board_early_init_r(void)
 278 {
 279         u32 val;
 280
 281         if (current_el() != 3)
 282                 return 0;
 283
 284         val = readl(&crlapb_base->timestamp_ref_ctrl);
 285         val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 286
 287         if (!val) {
 288                 val = readl(&crlapb_base->timestamp_ref_ctrl);
 289                 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 290                 writel(val, &crlapb_base->timestamp_ref_ctrl);
 291
 292                 /* Program freq register in System counter */
 293                 writel(zynqmp_get_system_timer_freq(),
 294                        &iou_scntr_secure->base_frequency_id_register);
 295                 /* And enable system counter */
 296                 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
 297                        &iou_scntr_secure->counter_control_register);
 298         }
 299         return 0;
 300 }
 301
 302 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 303 {
 304 #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
 305     defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
 306     defined(CONFIG_ZYNQ_EEPROM_BUS)
 307         i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS);
 308
 309         if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
 310                         CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
 311                         ethaddr, 6))
 312                 printf("I2C EEPROM MAC address read failed\n");
 313 #endif
 314
 315         return 0;
 316 }
 317
 318 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
 319 int dram_init_banksize(void)
 320 {
 321         return fdtdec_setup_memory_banksize();
 322 }
 323
 324 int dram_init(void)
 325 {
 326         if (fdtdec_setup_memory_size() != 0)
 327                 return -EINVAL;
 328
 329         return 0;
 330 }
 331 #else
 332 int dram_init(void)
 333 {
 334         gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 335
 336         return 0;
 337 }
 338 #endif
 339
 340 void reset_cpu(ulong addr)
 341 {
 342 }
 343
 344 int board_late_init(void)
 345 {
 346         u32 reg = 0;
 347         u8 bootmode;
 348         const char *mode;
 349         char *new_targets;
 350         char *env_targets;
 351         int ret;
 352
 353         if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
 354                 debug("Saved variables - Skipping\n");
 355                 return 0;
 356         }
 357
 358         ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
 359         if (ret)
 360                 return -EINVAL;
 361
 362         if (reg >> BOOT_MODE_ALT_SHIFT)
 363                 reg >>= BOOT_MODE_ALT_SHIFT;
 364
 365         bootmode = reg & BOOT_MODES_MASK;
 366
 367         puts("Bootmode: ");
 368         switch (bootmode) {
 369         case USB_MODE:
 370                 puts("USB_MODE\n");
 371                 mode = "usb";
 372                 env_set("modeboot", "usb_dfu_spl");
 373                 break;
 374         case JTAG_MODE:
 375                 puts("JTAG_MODE\n");
 376                 mode = "pxe dhcp";
 377                 env_set("modeboot", "jtagboot");
 378                 break;
 379         case QSPI_MODE_24BIT:
 380         case QSPI_MODE_32BIT:
 381                 mode = "qspi0";
 382                 puts("QSPI_MODE\n");
 383                 env_set("modeboot", "qspiboot");
 384                 break;
 385         case EMMC_MODE:
 386                 puts("EMMC_MODE\n");
 387                 mode = "mmc0";
 388                 env_set("modeboot", "emmcboot");
 389                 break;
 390         case SD_MODE:
 391                 puts("SD_MODE\n");
 392                 mode = "mmc0";
 393                 env_set("modeboot", "sdboot");
 394                 break;
 395         case SD1_LSHFT_MODE:
 396                 puts("LVL_SHFT_");
 397                 /* fall through */
 398         case SD_MODE1:
 399                 puts("SD_MODE1\n");
 400 #if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
 401                 mode = "mmc1";
 402                 env_set("sdbootdev", "1");
 403 #else
 404                 mode = "mmc0";
 405 #endif
 406                 env_set("modeboot", "sdboot");
 407                 break;
 408         case NAND_MODE:
 409                 puts("NAND_MODE\n");
 410                 mode = "nand0";
 411                 env_set("modeboot", "nandboot");
 412                 break;
 413         default:
 414                 mode = "";
 415                 printf("Invalid Boot Mode:0x%x\n", bootmode);
 416                 break;
 417         }
 418
 419         /*
 420          * One terminating char + one byte for space between mode
 421          * and default boot_targets
 422          */
 423         env_targets = env_get("boot_targets");
 424         if (env_targets) {
 425                 new_targets = calloc(1, strlen(mode) +
 426                                      strlen(env_targets) + 2);
 427                 sprintf(new_targets, "%s %s", mode, env_targets);
 428         } else {
 429                 new_targets = calloc(1, strlen(mode) + 2);
 430                 sprintf(new_targets, "%s", mode);
 431         }
 432
 433         env_set("boot_targets", new_targets);
 434
 435         return 0;
 436 }
 437
 438 int checkboard(void)
 439 {
 440         puts("Board: Xilinx ZynqMP\n");
 441         return 0;
 442 }
 443
 444 #ifdef CONFIG_USB_DWC3
 445 static struct dwc3_device dwc3_device_data0 = {
 446         .maximum_speed = USB_SPEED_HIGH,
 447         .base = ZYNQMP_USB0_XHCI_BASEADDR,
 448         .dr_mode = USB_DR_MODE_PERIPHERAL,
 449         .index = 0,
 450 };
 451
 452 static struct dwc3_device dwc3_device_data1 = {
 453         .maximum_speed = USB_SPEED_HIGH,
 454         .base = ZYNQMP_USB1_XHCI_BASEADDR,
 455         .dr_mode = USB_DR_MODE_PERIPHERAL,
 456         .index = 1,
 457 };
 458
 459 int usb_gadget_handle_interrupts(int index)
 460 {
 461         dwc3_uboot_handle_interrupt(index);
 462         return 0;
 463 }
 464
 465 int board_usb_init(int index, enum usb_init_type init)
 466 {
 467         debug("%s: index %x\n", __func__, index);
 468
 469 #if defined(CONFIG_USB_GADGET_DOWNLOAD)
 470         g_dnl_set_serialnumber(CONFIG_SYS_CONFIG_NAME);
 471 #endif
 472
 473         switch (index) {
 474         case 0:
 475                 return dwc3_uboot_init(&dwc3_device_data0);
 476         case 1:
 477                 return dwc3_uboot_init(&dwc3_device_data1);
 478         };
 479
 480         return -1;
 481 }
 482
 483 int board_usb_cleanup(int index, enum usb_init_type init)
 484 {
 485         dwc3_uboot_exit(index);
 486         return 0;
 487 }
 488 #endif