configs/T1042D4RDB_SPIFLASH_defconfig

   1 CONFIG_PPC=y
   2 CONFIG_SYS_TEXT_BASE=0x30001000
   3 CONFIG_SPL_LIBCOMMON_SUPPORT=y
   4 CONFIG_SPL_LIBGENERIC_SUPPORT=y
   5 CONFIG_ENV_SIZE=0x2000
   6 CONFIG_ENV_OFFSET=0x100000
   7 CONFIG_ENV_SECT_SIZE=0x10000
   8 CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb"
   9 CONFIG_SPL_TEXT_BASE=0xFFFD8000
  10 CONFIG_SPL_SERIAL=y
  11 CONFIG_SPL_DRIVERS_MISC=y
  12 CONFIG_SPL=y
  13 CONFIG_SPL_SPI_FLASH_SUPPORT=y
  14 CONFIG_SPL_SPI=y
  15 CONFIG_MPC85xx=y
  16 CONFIG_TARGET_T1042D4RDB=y
  17 CONFIG_MP=y
  18 CONFIG_FIT=y
  19 CONFIG_FIT_VERBOSE=y
  20 CONFIG_OF_BOARD_SETUP=y
  21 CONFIG_OF_STDOUT_VIA_ALIAS=y
  22 CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
  23 CONFIG_RAMBOOT_PBL=y
  24 CONFIG_SYS_FSL_PBL_PBI="$(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg"
  25 CONFIG_SYS_FSL_PBL_RCW="$(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg"
  26 CONFIG_BOOTDELAY=10
  27 CONFIG_USE_BOOTCOMMAND=y
  28 CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
  29 CONFIG_SILENT_CONSOLE=y
  30 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
  31 CONFIG_BOARD_EARLY_INIT_F=y
  32 CONFIG_BOARD_EARLY_INIT_R=y
  33 # CONFIG_SPL_FRAMEWORK is not set
  34 CONFIG_SPL_SPI_BOOT=y
  35 CONFIG_SPL_FSL_PBL=y
  36 CONFIG_SPL_ENV_SUPPORT=y
  37 CONFIG_SPL_I2C=y
  38 CONFIG_SPL_MPC8XXX_INIT_DDR=y
  39 CONFIG_HUSH_PARSER=y
  40 CONFIG_CMD_IMLS=y
  41 CONFIG_CMD_GREPENV=y
  42 CONFIG_CMD_DM=y
  43 CONFIG_CMD_I2C=y
  44 CONFIG_CMD_MMC=y
  45 CONFIG_CMD_USB=y
  46 CONFIG_CMD_DHCP=y
  47 CONFIG_CMD_MII=y
  48 CONFIG_CMD_PING=y
  49 CONFIG_CMD_EXT2=y
  50 CONFIG_CMD_FAT=y
  51 CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
  52 CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
  53 CONFIG_OF_CONTROL=y
  54 CONFIG_ENV_OVERWRITE=y
  55 CONFIG_ENV_IS_IN_SPI_FLASH=y
  56 CONFIG_USE_BOOTFILE=y
  57 CONFIG_BOOTFILE="uImage"
  58 CONFIG_USE_ETHPRIME=y
  59 CONFIG_ETHPRIME="FM1@DTSEC4"
  60 CONFIG_DM=y
  61 CONFIG_FSL_CAAM=y
  62 CONFIG_DDR_CLK_FREQ=66666666
  63 CONFIG_CHIP_SELECTS_PER_CTRL=2
  64 CONFIG_DDR_ECC=y
  65 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
  66 CONFIG_DM_I2C=y
  67 CONFIG_SPL_SYS_I2C_LEGACY=y
  68 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
  69 CONFIG_SYS_I2C_FSL=y
  70 CONFIG_SYS_FSL_I2C_OFFSET=0x118000
  71 CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
  72 CONFIG_SYS_FSL_I2C2_OFFSET=0x118100
  73 CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y
  74 CONFIG_SYS_FSL_I2C3_OFFSET=0x119000
  75 CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y
  76 CONFIG_SYS_FSL_I2C4_OFFSET=0x119100
  77 CONFIG_FSL_ESDHC=y
  78 CONFIG_MTD=y
  79 CONFIG_MTD_NOR_FLASH=y
  80 CONFIG_FLASH_CFI_DRIVER=y
  81 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
  82 CONFIG_FLASH_CFI_MTD=y
  83 CONFIG_SYS_FLASH_CFI=y
  84 CONFIG_SYS_MAX_FLASH_BANKS=2
  85 CONFIG_DM_SPI_FLASH=y
  86 CONFIG_SF_DEFAULT_SPEED=10000000
  87 CONFIG_SPI_FLASH_STMICRO=y
  88 CONFIG_PHYLIB=y
  89 CONFIG_PHY_REALTEK=y
  90 CONFIG_PHY_VITESSE=y
  91 CONFIG_DM_ETH=y
  92 CONFIG_DM_MDIO=y
  93 CONFIG_PHY_GIGE=y
  94 CONFIG_E1000=y
  95 CONFIG_FMAN_ENET=y
  96 CONFIG_SYS_FMAN_FW_ADDR=0x110000
  97 CONFIG_MII=y
  98 CONFIG_PCIE_FSL=y
  99 CONFIG_U_QE=y
 100 CONFIG_SYS_QE_FW_ADDR=0x130000
 101 CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
 102 CONFIG_DM_RTC=y
 103 CONFIG_SYS_NS16550=y
 104 CONFIG_SPI=y
 105 CONFIG_DM_SPI=y
 106 CONFIG_FSL_ESPI=y
 107 CONFIG_USB=y
 108 CONFIG_USB_EHCI_FSL=y
 109 CONFIG_USB_STORAGE=y
 110 CONFIG_ADDR_MAP=y
 111 CONFIG_SYS_NUM_ADDR_MAP=64