]> git.ipfire.org Git - thirdparty/u-boot.git/blob - configs/T2080QDS_SPIFLASH_defconfig
Merge patch series "pxe: Allow extlinux booting without CMDLINE enabled"
[thirdparty/u-boot.git] / configs / T2080QDS_SPIFLASH_defconfig
1 CONFIG_PPC=y
2 CONFIG_TEXT_BASE=0x00200000
3 CONFIG_SPL_LIBCOMMON_SUPPORT=y
4 CONFIG_SPL_LIBGENERIC_SUPPORT=y
5 CONFIG_SF_DEFAULT_SPEED=10000000
6 CONFIG_ENV_SIZE=0x2000
7 CONFIG_ENV_OFFSET=0x100000
8 CONFIG_ENV_SECT_SIZE=0x10000
9 CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
10 CONFIG_SPL_TEXT_BASE=0xFFFD8000
11 CONFIG_SYS_MONITOR_LEN=786432
12 CONFIG_SPL_SERIAL=y
13 CONFIG_SPL_DRIVERS_MISC=y
14 CONFIG_SPL=y
15 CONFIG_SPL_SPI_FLASH_SUPPORT=y
16 CONFIG_SPL_SPI=y
17 CONFIG_MPC85xx=y
18 CONFIG_SYS_INIT_RAM_LOCK=y
19 CONFIG_SYS_SRIO=y
20 CONFIG_SRIO1=y
21 CONFIG_SRIO2=y
22 CONFIG_SRIO_PCIE_BOOT_MASTER=y
23 CONFIG_TARGET_T2080QDS=y
24 CONFIG_ENABLE_36BIT_PHYS=y
25 CONFIG_SYS_BOOK3E_HV=y
26 CONFIG_SYS_CACHE_STASHING=y
27 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
28 CONFIG_USE_UBOOTPATH=y
29 CONFIG_PCIE1=y
30 CONFIG_PCIE2=y
31 CONFIG_PCIE3=y
32 CONFIG_PCIE4=y
33 CONFIG_FSL_USE_PCA9547_MUX=y
34 CONFIG_VID=y
35 CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
36 CONFIG_VOL_MONITOR_IR36021_READ=y
37 CONFIG_VOL_MONITOR_IR36021_SET=y
38 CONFIG_SYS_FSL_NUM_CC_PLLS=2
39 CONFIG_FSL_QIXIS=y
40 # CONFIG_QIXIS_I2C_ACCESS is not set
41 CONFIG_MP=y
42 CONFIG_DYNAMIC_SYS_CLK_FREQ=y
43 CONFIG_FIT=y
44 CONFIG_FIT_VERBOSE=y
45 CONFIG_RAMBOOT_PBL=y
46 CONFIG_SPIFLASH=y
47 CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xqds/t208x_pbi.cfg"
48 CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xqds/t2080_spi_rcw.cfg"
49 CONFIG_BOOTDELAY=10
50 CONFIG_OF_BOARD_SETUP=y
51 CONFIG_OF_STDOUT_VIA_ALIAS=y
52 CONFIG_USE_BOOTCOMMAND=y
53 CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
54 CONFIG_SYS_PBSIZE=276
55 CONFIG_ARCH_MISC_INIT=y
56 CONFIG_BOARD_EARLY_INIT_R=y
57 # CONFIG_SPL_FRAMEWORK is not set
58 CONFIG_SPL_MAX_SIZE=0x28000
59 CONFIG_SPL_PAD_TO=0x40000
60 CONFIG_SPL_SPI_BOOT=y
61 CONFIG_SPL_FSL_PBL=y
62 CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
63 CONFIG_SPL_FLUSH_IMAGE=y
64 CONFIG_SPL_SKIP_RELOCATE=y
65 CONFIG_SPL_GD_ADDR=0xfffc8000
66 CONFIG_SPL_RELOC_STACK=0xfffd8000
67 CONFIG_SPL_RELOC_MALLOC=y
68 CONFIG_SPL_RELOC_MALLOC_ADDR=0xfffcb000
69 CONFIG_SPL_RELOC_MALLOC_SIZE=0xc800
70 CONFIG_SPL_ENV_SUPPORT=y
71 CONFIG_SPL_I2C=y
72 CONFIG_SPL_MPC8XXX_INIT_DDR=y
73 CONFIG_HUSH_PARSER=y
74 CONFIG_CMD_IMLS=y
75 CONFIG_CMD_GREPENV=y
76 CONFIG_CMD_I2C=y
77 CONFIG_LOADS_ECHO=y
78 CONFIG_SYS_LOADS_BAUD_CHANGE=y
79 CONFIG_CMD_MMC=y
80 CONFIG_CMD_USB=y
81 CONFIG_CMD_DHCP=y
82 CONFIG_CMD_MII=y
83 CONFIG_CMD_PING=y
84 CONFIG_CMD_EXT2=y
85 CONFIG_CMD_FAT=y
86 CONFIG_CMD_MTDPARTS=y
87 CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
88 CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
89 CONFIG_OF_CONTROL=y
90 CONFIG_ENV_OVERWRITE=y
91 CONFIG_ENV_IS_IN_SPI_FLASH=y
92 CONFIG_USE_BOOTFILE=y
93 CONFIG_BOOTFILE="uImage"
94 CONFIG_USE_ETHPRIME=y
95 CONFIG_ETHPRIME="FM1@DTSEC3"
96 CONFIG_USE_ROOTPATH=y
97 CONFIG_FSL_SATA_V2=y
98 CONFIG_SYS_SATA_MAX_DEVICE=2
99 CONFIG_FSL_CAAM=y
100 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
101 CONFIG_DIMM_SLOTS_PER_CTLR=2
102 CONFIG_DDR_ECC=y
103 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
104 CONFIG_DM_I2C=y
105 CONFIG_SPL_SYS_I2C_LEGACY=y
106 CONFIG_SYS_I2C_FSL=y
107 CONFIG_SYS_FSL_I2C_OFFSET=0x118000
108 CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
109 CONFIG_SYS_FSL_I2C2_OFFSET=0x118100
110 CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y
111 CONFIG_SYS_FSL_I2C3_OFFSET=0x119000
112 CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y
113 CONFIG_SYS_FSL_I2C4_OFFSET=0x119100
114 CONFIG_SYS_I2C_EEPROM_ADDR=0x57
115 CONFIG_FSL_ESDHC=y
116 CONFIG_MTD=y
117 CONFIG_MTD_NOR_FLASH=y
118 CONFIG_FLASH_CFI_DRIVER=y
119 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
120 CONFIG_SYS_FLASH_EMPTY_INFO=y
121 CONFIG_FLASH_CFI_MTD=y
122 CONFIG_SYS_FLASH_CFI=y
123 CONFIG_SYS_FLASH_QUIET_TEST=y
124 CONFIG_SYS_MAX_FLASH_SECT=1024
125 CONFIG_SYS_MAX_FLASH_BANKS=2
126 CONFIG_DM_SPI_FLASH=y
127 CONFIG_SPI_FLASH_EON=y
128 CONFIG_SPI_FLASH_STMICRO=y
129 CONFIG_SPI_FLASH_SST=y
130 CONFIG_PHYLIB=y
131 CONFIG_PHY_AQUANTIA=y
132 CONFIG_PHY_REALTEK=y
133 CONFIG_PHY_TERANETICS=y
134 CONFIG_PHY_VITESSE=y
135 CONFIG_E1000=y
136 CONFIG_FMAN_ENET=y
137 CONFIG_SYS_FMAN_FW_ADDR=0x110000
138 CONFIG_MII=y
139 CONFIG_DM_PCI_COMPAT=y
140 CONFIG_PCIE_FSL=y
141 CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
142 CONFIG_SYS_NS16550_SERIAL=y
143 CONFIG_SPI=y
144 CONFIG_DM_SPI=y
145 CONFIG_FSL_ESPI=y
146 CONFIG_USB=y
147 CONFIG_USB_EHCI_FSL=y
148 CONFIG_USB_MAX_CONTROLLER_COUNT=2
149 CONFIG_USB_STORAGE=y
150 CONFIG_ADDR_MAP=y
151 CONFIG_SYS_NUM_ADDR_MAP=64