drivers/clk/renesas/clk-rcar-gen3.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Renesas RCar Gen3 CPG MSSR driver
   4  *
   5  * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
   6  *
   7  * Based on the following driver from Linux kernel:
   8  * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
   9  *
  10  * Copyright (C) 2016 Glider bvba
  11  */
  12
  13 #include <common.h>
  14 #include <clk-uclass.h>
  15 #include <dm.h>
  16 #include <dm/device-internal.h>
  17 #include <dm/lists.h>
  18 #include <errno.h>
  19 #include <log.h>
  20 #include <wait_bit.h>
  21 #include <asm/global_data.h>
  22 #include <asm/io.h>
  23 #include <linux/bitfield.h>
  24 #include <linux/bitops.h>
  25 #include <linux/clk-provider.h>
  26 #include <reset-uclass.h>
  27
  28 #include <dt-bindings/clock/renesas-cpg-mssr.h>
  29
  30 #include "renesas-cpg-mssr.h"
  31 #include "rcar-gen3-cpg.h"
  32 #include "rcar-cpg-lib.h"
  33
  34 #define CPG_PLL0CR              0x00d8
  35 #define CPG_PLL2CR              0x002c
  36 #define CPG_PLL4CR              0x01f4
  37
  38 static const struct clk_div_table cpg_rpcsrc_div_table[] = {
  39         { 2, 5 }, { 3, 6 }, { 0, 0 },
  40 };
  41
  42 static const struct clk_div_table r8a77970_cpg_sd0h_div_table[] = {
  43         {  0,  2 }, {  1,  3 }, {  2,  4 }, {  3,  6 },
  44         {  4,  8 }, {  5, 12 }, {  6, 16 }, {  7, 18 },
  45         {  8, 24 }, { 10, 36 }, { 11, 48 }, {  0,  0 },
  46 };
  47
  48 static const struct clk_div_table r8a77970_cpg_sd0_div_table[] = {
  49         {  4,  8 }, {  5, 12 }, {  6, 16 }, {  7, 18 },
  50         {  8, 24 }, { 10, 36 }, { 11, 48 }, { 12, 10 },
  51         {  0,  0 },
  52 };
  53
  54 static int gen3_clk_get_parent(struct gen3_clk_priv *priv, struct clk *clk,
  55                                struct cpg_mssr_info *info, struct clk *parent)
  56 {
  57         const struct cpg_core_clk *core;
  58         u8 shift;
  59         int ret;
  60
  61         if (!renesas_clk_is_mod(clk)) {
  62                 ret = renesas_clk_get_core(clk, info, &core);
  63                 if (ret)
  64                         return ret;
  65
  66                 if (core->type == CLK_TYPE_GEN3_MDSEL) {
  67                         shift = priv->cpg_mode & BIT(core->offset) ? 16 : 0;
  68                         parent->dev = clk->dev;
  69                         parent->id = core->parent >> shift;
  70                         parent->id &= 0xffff;
  71                         return 0;
  72                 }
  73         }
  74
  75         return renesas_clk_get_parent(clk, info, parent);
  76 }
  77
  78 static int gen3_clk_enable(struct clk *clk)
  79 {
  80         struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
  81
  82         return renesas_clk_endisable(clk, priv->base, priv->info, true);
  83 }
  84
  85 static int gen3_clk_disable(struct clk *clk)
  86 {
  87         struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
  88
  89         return renesas_clk_endisable(clk, priv->base, priv->info, false);
  90 }
  91
  92 static u64 gen3_clk_get_rate64(struct clk *clk);
  93
  94 static int gen3_clk_setup_sdif_div(struct clk *clk, ulong rate)
  95 {
  96         struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
  97         struct cpg_mssr_info *info = priv->info;
  98         const struct cpg_core_clk *core;
  99         struct clk parent, grandparent;
 100         int ret;
 101
 102         /*
 103          * The clk may be either CPG_MOD or core clock, in case this is MOD
 104          * clock, use core clock one level up, otherwise use the clock as-is.
 105          * Note that parent clock here always represents core clock. Also note
 106          * that grandparent clock are the parent clock of the core clock here.
 107          */
 108         if (renesas_clk_is_mod(clk)) {
 109                 ret = gen3_clk_get_parent(priv, clk, info, &parent);
 110                 if (ret) {
 111                         printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
 112                         return ret;
 113                 }
 114         } else {
 115                 parent = *clk;
 116         }
 117
 118         if (renesas_clk_is_mod(&parent))
 119                 return 0;
 120
 121         ret = renesas_clk_get_core(&parent, info, &core);
 122         if (ret)
 123                 return ret;
 124
 125         ret = renesas_clk_get_parent(&parent, info, &grandparent);
 126         if (ret) {
 127                 printf("%s[%i] grandparent fail, ret=%i\n", __func__, __LINE__, ret);
 128                 return ret;
 129         }
 130
 131         switch (core->type) {
 132         case CLK_TYPE_GEN3_SDH:
 133                 fallthrough;
 134         case CLK_TYPE_GEN4_SDH:
 135                 return rcar_clk_set_rate64_sdh(core->parent,
 136                                                gen3_clk_get_rate64(&grandparent),
 137                                                rate, priv->base + core->offset);
 138
 139         case CLK_TYPE_GEN3_SD:
 140                 fallthrough;
 141         case CLK_TYPE_GEN4_SD:
 142                 return rcar_clk_set_rate64_sd(core->parent,
 143                                               gen3_clk_get_rate64(&grandparent),
 144                                               rate, priv->base + core->offset);
 145
 146         case CLK_TYPE_R8A77970_SD0:
 147                 return rcar_clk_set_rate64_div_table(core->parent,
 148                                                      gen3_clk_get_rate64(&grandparent),
 149                                                      rate, priv->base + core->offset,
 150                                                      CPG_SDCKCR_SD0FC_MASK,
 151                                                      r8a77970_cpg_sd0_div_table, "SD");
 152         }
 153
 154         return 0;
 155 }
 156
 157 static u64 gen3_clk_get_rate64_pll_mul_reg(struct gen3_clk_priv *priv,
 158                                            struct clk *parent,
 159                                            u32 mul_reg, u32 mult, u32 div,
 160                                            char *name)
 161 {
 162         u32 value;
 163         u64 rate;
 164
 165         if (mul_reg) {
 166                 value = readl(priv->base + mul_reg);
 167                 mult = (((value >> 24) & 0x7f) + 1) * 2;
 168                 div = 1;
 169         }
 170
 171         rate = (gen3_clk_get_rate64(parent) * mult) / div;
 172
 173         debug("%s[%i] %s clk: mult=%u div=%u => rate=%llu\n",
 174               __func__, __LINE__, name, mult, div, rate);
 175         return rate;
 176 }
 177
 178 static u64 gen3_clk_get_rate64(struct clk *clk)
 179 {
 180         struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
 181         struct cpg_mssr_info *info = priv->info;
 182         struct clk parent;
 183         const struct cpg_core_clk *core;
 184         const struct rcar_gen3_cpg_pll_config *pll_config =
 185                                         priv->cpg_pll_config;
 186         u32 value, div;
 187         u64 rate = 0;
 188         u8 shift;
 189         int ret;
 190
 191         debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id);
 192
 193         ret = gen3_clk_get_parent(priv, clk, info, &parent);
 194         if (ret) {
 195                 printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
 196                 return ret;
 197         }
 198
 199         if (renesas_clk_is_mod(clk)) {
 200                 rate = gen3_clk_get_rate64(&parent);
 201                 debug("%s[%i] MOD clk: parent=%lu => rate=%llu\n",
 202                       __func__, __LINE__, parent.id, rate);
 203                 return rate;
 204         }
 205
 206         ret = renesas_clk_get_core(clk, info, &core);
 207         if (ret)
 208                 return ret;
 209
 210         switch (core->type) {
 211         case CLK_TYPE_IN:
 212                 if (core->id == info->clk_extal_id) {
 213                         rate = clk_get_rate(&priv->clk_extal);
 214                         debug("%s[%i] EXTAL clk: rate=%llu\n",
 215                               __func__, __LINE__, rate);
 216                         return rate;
 217                 }
 218
 219                 if (core->id == info->clk_extalr_id) {
 220                         rate = clk_get_rate(&priv->clk_extalr);
 221                         debug("%s[%i] EXTALR clk: rate=%llu\n",
 222                               __func__, __LINE__, rate);
 223                         return rate;
 224                 }
 225
 226                 return -EINVAL;
 227
 228         case CLK_TYPE_GEN3_MAIN:
 229                 return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
 230                                                 0, 1, pll_config->extal_div,
 231                                                 "MAIN");
 232
 233         case CLK_TYPE_GEN3_PLL0:
 234                 return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
 235                                                 CPG_PLL0CR, 0, 0, "PLL0");
 236
 237         case CLK_TYPE_GEN3_PLL1:
 238                 return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
 239                                                 0, pll_config->pll1_mult,
 240                                                 pll_config->pll1_div, "PLL1");
 241
 242         case CLK_TYPE_GEN3_PLL2:
 243                 return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
 244                                                 CPG_PLL2CR, 0, 0, "PLL2");
 245
 246         case CLK_TYPE_GEN3_PLL3:
 247                 return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
 248                                                 0, pll_config->pll3_mult,
 249                                                 pll_config->pll3_div, "PLL3");
 250
 251         case CLK_TYPE_GEN3_PLL4:
 252                 return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
 253                                                 CPG_PLL4CR, 0, 0, "PLL4");
 254
 255         case CLK_TYPE_GEN4_MAIN:
 256                 return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
 257                                                 0, 1, pll_config->extal_div,
 258                                                 "V3U_MAIN");
 259
 260         case CLK_TYPE_GEN4_PLL1:
 261                 return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
 262                                                 0, pll_config->pll1_mult,
 263                                                 pll_config->pll1_div,
 264                                                 "V3U_PLL1");
 265
 266         case CLK_TYPE_GEN4_PLL2X_3X:
 267                 return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
 268                                                 core->offset, 0, 0,
 269                                                 "V3U_PLL2X_3X");
 270
 271         case CLK_TYPE_GEN4_PLL5:
 272                 return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
 273                                                 0, pll_config->pll5_mult,
 274                                                 pll_config->pll5_div,
 275                                                 "V3U_PLL5");
 276
 277         case CLK_TYPE_FF:
 278                 return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
 279                                                 0, core->mult, core->div,
 280                                                 "FIXED");
 281
 282         case CLK_TYPE_GEN3_MDSEL:
 283                 shift = priv->cpg_mode & BIT(core->offset) ? 16 : 0;
 284                 div = (core->div >> shift) & 0xffff;
 285                 rate = gen3_clk_get_rate64(&parent) / div;
 286                 debug("%s[%i] PE clk: parent=%i div=%u => rate=%llu\n",
 287                       __func__, __LINE__, (core->parent >> shift) & 0xffff,
 288                       div, rate);
 289                 return rate;
 290
 291         case CLK_TYPE_GEN3_SDH: /* Fixed factor 1:1 */
 292                 fallthrough;
 293         case CLK_TYPE_GEN4_SDH: /* Fixed factor 1:1 */
 294                 return rcar_clk_get_rate64_sdh(core->parent,
 295                                                gen3_clk_get_rate64(&parent),
 296                                                priv->base + core->offset);
 297
 298         case CLK_TYPE_R8A77970_SD0H:
 299                 return rcar_clk_get_rate64_div_table(core->parent,
 300                                                      gen3_clk_get_rate64(&parent),
 301                                                      priv->base + core->offset,
 302                                                      CPG_SDCKCR_SDHFC_MASK,
 303                                                      r8a77970_cpg_sd0h_div_table, "SDH");
 304
 305         case CLK_TYPE_GEN3_SD:
 306                 fallthrough;
 307         case CLK_TYPE_GEN4_SD:
 308                 return rcar_clk_get_rate64_sd(core->parent,
 309                                               gen3_clk_get_rate64(&parent),
 310                                               priv->base + core->offset);
 311
 312         case CLK_TYPE_R8A77970_SD0:
 313                 return rcar_clk_get_rate64_div_table(core->parent,
 314                                                      gen3_clk_get_rate64(&parent),
 315                                                      priv->base + core->offset,
 316                                                      CPG_SDCKCR_SD0FC_MASK,
 317                                                      r8a77970_cpg_sd0_div_table, "SD");
 318
 319         case CLK_TYPE_GEN3_RPCSRC:
 320                 return rcar_clk_get_rate64_div_table(core->parent,
 321                                                      gen3_clk_get_rate64(&parent),
 322                                                      priv->base + CPG_RPCCKCR,
 323                                                      CPG_RPCCKCR_DIV_POST_MASK,
 324                                                      cpg_rpcsrc_div_table, "RPCSRC");
 325
 326         case CLK_TYPE_GEN3_D3_RPCSRC:
 327         case CLK_TYPE_GEN3_E3_RPCSRC:
 328                 /*
 329                  * Register RPCSRC as fixed factor clock based on the
 330                  * MD[4:1] pins and CPG_RPCCKCR[4:3] register value for
 331                  * which has been set prior to booting the kernel.
 332                  */
 333                 value = (readl(priv->base + CPG_RPCCKCR) & GENMASK(4, 3)) >> 3;
 334
 335                 switch (value) {
 336                 case 0:
 337                         div = 5;
 338                         break;
 339                 case 1:
 340                         div = 3;
 341                         break;
 342                 case 2:
 343                         div = core->div;
 344                         break;
 345                 case 3:
 346                 default:
 347                         div = 2;
 348                         break;
 349                 }
 350
 351                 rate = gen3_clk_get_rate64(&parent) / div;
 352                 debug("%s[%i] E3/D3 RPCSRC clk: parent=%i div=%u => rate=%llu\n",
 353                       __func__, __LINE__, (core->parent >> 16) & 0xffff, div, rate);
 354
 355                 return rate;
 356
 357         case CLK_TYPE_GEN3_RPC:
 358         case CLK_TYPE_GEN4_RPC:
 359                 return rcar_clk_get_rate64_rpc(core->parent,
 360                                                gen3_clk_get_rate64(&parent),
 361                                                priv->base + CPG_RPCCKCR);
 362
 363         case CLK_TYPE_GEN3_RPCD2:
 364         case CLK_TYPE_GEN4_RPCD2:
 365                 return rcar_clk_get_rate64_rpcd2(core->parent,
 366                                                  gen3_clk_get_rate64(&parent));
 367
 368         }
 369
 370         printf("%s[%i] unknown fail\n", __func__, __LINE__);
 371
 372         return -ENOENT;
 373 }
 374
 375 static ulong gen3_clk_get_rate(struct clk *clk)
 376 {
 377         return gen3_clk_get_rate64(clk);
 378 }
 379
 380 static ulong gen3_clk_set_rate(struct clk *clk, ulong rate)
 381 {
 382         /* Force correct SD-IF divider configuration if applicable */
 383         gen3_clk_setup_sdif_div(clk, rate);
 384         return gen3_clk_get_rate64(clk);
 385 }
 386
 387 static int gen3_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
 388 {
 389         if (args->args_count != 2) {
 390                 debug("Invalid args_count: %d\n", args->args_count);
 391                 return -EINVAL;
 392         }
 393
 394         clk->id = (args->args[0] << 16) | args->args[1];
 395
 396         return 0;
 397 }
 398
 399 const struct clk_ops gen3_clk_ops = {
 400         .enable         = gen3_clk_enable,
 401         .disable        = gen3_clk_disable,
 402         .get_rate       = gen3_clk_get_rate,
 403         .set_rate       = gen3_clk_set_rate,
 404         .of_xlate       = gen3_clk_of_xlate,
 405 };
 406
 407 static int gen3_clk_probe(struct udevice *dev)
 408 {
 409         struct gen3_clk_priv *priv = dev_get_priv(dev);
 410         struct cpg_mssr_info *info =
 411                 (struct cpg_mssr_info *)dev_get_driver_data(dev);
 412         fdt_addr_t rst_base;
 413         int ret;
 414
 415         priv->base = dev_read_addr_ptr(dev);
 416         if (!priv->base)
 417                 return -EINVAL;
 418
 419         priv->info = info;
 420         ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, info->reset_node);
 421         if (ret < 0)
 422                 return ret;
 423
 424         rst_base = fdtdec_get_addr(gd->fdt_blob, ret, "reg");
 425         if (rst_base == FDT_ADDR_T_NONE)
 426                 return -EINVAL;
 427
 428         priv->cpg_mode = readl(rst_base + info->reset_modemr_offset);
 429
 430         priv->cpg_pll_config =
 431                 (struct rcar_gen3_cpg_pll_config *)info->get_pll_config(priv->cpg_mode);
 432         if (!priv->cpg_pll_config->extal_div)
 433                 return -EINVAL;
 434
 435         if (info->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) {
 436                 priv->info->status_regs = mstpsr;
 437                 priv->info->control_regs = smstpcr;
 438                 priv->info->reset_regs = srcr;
 439                 priv->info->reset_clear_regs = srstclr;
 440         } else if (info->reg_layout == CLK_REG_LAYOUT_RCAR_V3U) {
 441                 priv->info->status_regs = mstpsr_for_v3u;
 442                 priv->info->control_regs = mstpcr_for_v3u;
 443                 priv->info->reset_regs = srcr_for_v3u;
 444                 priv->info->reset_clear_regs = srstclr_for_v3u;
 445         } else {
 446                 return -EINVAL;
 447         }
 448
 449         ret = clk_get_by_name(dev, "extal", &priv->clk_extal);
 450         if (ret < 0)
 451                 return ret;
 452
 453         if (info->extalr_node) {
 454                 ret = clk_get_by_name(dev, info->extalr_node, &priv->clk_extalr);
 455                 if (ret < 0)
 456                         return ret;
 457         }
 458
 459         return 0;
 460 }
 461
 462 static int gen3_clk_remove(struct udevice *dev)
 463 {
 464         struct gen3_clk_priv *priv = dev_get_priv(dev);
 465
 466         return renesas_clk_remove(priv->base, priv->info);
 467 }
 468
 469 U_BOOT_DRIVER(clk_gen3) = {
 470         .name           = "clk_gen3",
 471         .id             = UCLASS_CLK,
 472         .priv_auto      = sizeof(struct gen3_clk_priv),
 473         .ops            = &gen3_clk_ops,
 474         .probe          = gen3_clk_probe,
 475         .remove         = gen3_clk_remove,
 476 };
 477
 478 static int gen3_reset_assert(struct reset_ctl *reset_ctl)
 479 {
 480         struct udevice *cdev = (struct udevice *)dev_get_driver_data(reset_ctl->dev);
 481         struct gen3_clk_priv *priv = dev_get_priv(cdev);
 482         unsigned int packed_id = MOD_CLK_PACK(reset_ctl->id);
 483         unsigned int reg = packed_id / 32;
 484         unsigned int bit = packed_id % 32;
 485         u32 bitmask = BIT(bit);
 486
 487         writel(bitmask, priv->base + priv->info->reset_regs[reg]);
 488
 489         return 0;
 490 }
 491
 492 static int gen3_reset_deassert(struct reset_ctl *reset_ctl)
 493 {
 494         struct udevice *cdev = (struct udevice *)dev_get_driver_data(reset_ctl->dev);
 495         struct gen3_clk_priv *priv = dev_get_priv(cdev);
 496         unsigned int packed_id = MOD_CLK_PACK(reset_ctl->id);
 497         unsigned int reg = packed_id / 32;
 498         unsigned int bit = packed_id % 32;
 499         u32 bitmask = BIT(bit);
 500
 501         writel(bitmask, priv->base + priv->info->reset_clear_regs[reg]);
 502
 503         return 0;
 504 }
 505
 506 static const struct reset_ops rst_gen3_ops = {
 507         .rst_assert = gen3_reset_assert,
 508         .rst_deassert = gen3_reset_deassert,
 509 };
 510
 511 U_BOOT_DRIVER(rst_gen3) = {
 512         .name = "rst_gen3",
 513         .id = UCLASS_RESET,
 514         .ops = &rst_gen3_ops,
 515 };
 516
 517 int gen3_cpg_bind(struct udevice *parent)
 518 {
 519         struct cpg_mssr_info *info =
 520                 (struct cpg_mssr_info *)dev_get_driver_data(parent);
 521         struct udevice *cdev, *rdev;
 522         struct driver *drv;
 523         int ret;
 524
 525         drv = lists_driver_lookup_name("clk_gen3");
 526         if (!drv)
 527                 return -ENOENT;
 528
 529         ret = device_bind_with_driver_data(parent, drv, "clk_gen3", (ulong)info,
 530                                            dev_ofnode(parent), &cdev);
 531         if (ret)
 532                 return ret;
 533
 534         drv = lists_driver_lookup_name("rst_gen3");
 535         if (!drv)
 536                 return -ENOENT;
 537
 538         ret = device_bind_with_driver_data(parent, drv, "rst_gen3", (ulong)cdev,
 539                                            dev_ofnode(parent), &rdev);
 540         if (ret)
 541                 device_unbind(cdev);
 542
 543         return ret;
 544 }