drivers/crypto/ace_sha.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Advanced Crypto Engine - SHA Firmware
   4  * Copyright (c) 2012  Samsung Electronics
   5  */
   6 #include <common.h>
   7 #include "ace_sha.h"
   8
   9 #ifdef CONFIG_SHA_HW_ACCEL
  10 #include <u-boot/sha256.h>
  11 #include <u-boot/sha1.h>
  12 #include <linux/errno.h>
  13
  14 /* SHA1 value for the message of zero length */
  15 static const unsigned char sha1_digest_emptymsg[SHA1_SUM_LEN] = {
  16         0xDA, 0x39, 0xA3, 0xEE, 0x5E, 0x6B, 0x4B, 0x0D,
  17         0x32, 0x55, 0xBF, 0xFF, 0x95, 0x60, 0x18, 0x90,
  18         0xAF, 0xD8, 0x07, 0x09};
  19
  20 /* SHA256 value for the message of zero length */
  21 static const unsigned char sha256_digest_emptymsg[SHA256_SUM_LEN] = {
  22         0xE3, 0xB0, 0xC4, 0x42, 0x98, 0xFC, 0x1C, 0x14,
  23         0x9A, 0xFB, 0xF4, 0xC8, 0x99, 0x6F, 0xB9, 0x24,
  24         0x27, 0xAE, 0x41, 0xE4, 0x64, 0x9B, 0x93, 0x4C,
  25         0xA4, 0x95, 0x99, 0x1B, 0x78, 0x52, 0xB8, 0x55};
  26
  27 int ace_sha_hash_digest(const unsigned char *pbuf, unsigned int buf_len,
  28                         unsigned char *pout, unsigned int hash_type)
  29 {
  30         unsigned int i, reg, len;
  31         unsigned int *pdigest;
  32         struct exynos_ace_sfr *ace_sha_reg =
  33                 (struct exynos_ace_sfr *)samsung_get_base_ace_sfr();
  34
  35         if (buf_len == 0) {
  36                 /* ACE H/W cannot compute hash value for empty string */
  37                 if (hash_type == ACE_SHA_TYPE_SHA1)
  38                         memcpy(pout, sha1_digest_emptymsg, SHA1_SUM_LEN);
  39                 else
  40                         memcpy(pout, sha256_digest_emptymsg, SHA256_SUM_LEN);
  41                 return 0;
  42         }
  43
  44         /* Flush HRDMA */
  45         writel(ACE_FC_HRDMACFLUSH_ON, &ace_sha_reg->fc_hrdmac);
  46         writel(ACE_FC_HRDMACFLUSH_OFF, &ace_sha_reg->fc_hrdmac);
  47
  48         /* Set byte swap of data in */
  49         writel(ACE_HASH_SWAPDI_ON | ACE_HASH_SWAPDO_ON | ACE_HASH_SWAPIV_ON,
  50                &ace_sha_reg->hash_byteswap);
  51
  52         /* Select Hash input mux as external source */
  53         reg = readl(&ace_sha_reg->fc_fifoctrl);
  54         reg = (reg & ~ACE_FC_SELHASH_MASK) | ACE_FC_SELHASH_EXOUT;
  55         writel(reg, &ace_sha_reg->fc_fifoctrl);
  56
  57         /* Set Hash as SHA1 or SHA256 and start Hash engine */
  58         reg = (hash_type == ACE_SHA_TYPE_SHA1) ?
  59                 ACE_HASH_ENGSEL_SHA1HASH : ACE_HASH_ENGSEL_SHA256HASH;
  60         reg |= ACE_HASH_STARTBIT_ON;
  61         writel(reg, &ace_sha_reg->hash_control);
  62
  63         /* Enable FIFO mode */
  64         writel(ACE_HASH_FIFO_ON, &ace_sha_reg->hash_fifo_mode);
  65
  66         /* Set message length */
  67         writel(buf_len, &ace_sha_reg->hash_msgsize_low);
  68         writel(0, &ace_sha_reg->hash_msgsize_high);
  69
  70         /* Set HRDMA */
  71         writel((unsigned int)pbuf, &ace_sha_reg->fc_hrdmas);
  72         writel(buf_len, &ace_sha_reg->fc_hrdmal);
  73
  74         while ((readl(&ace_sha_reg->hash_status) & ACE_HASH_MSGDONE_MASK) ==
  75                 ACE_HASH_MSGDONE_OFF) {
  76                 /*
  77                  * PRNG error bit goes HIGH if a PRNG request occurs without
  78                  * a complete seed setup. We are using this bit to check h/w
  79                  * fault because proper setup is not expected in that case.
  80                  */
  81                 if ((readl(&ace_sha_reg->hash_status)
  82                         & ACE_HASH_PRNGERROR_MASK) == ACE_HASH_PRNGERROR_ON)
  83                         return -EBUSY;
  84         }
  85
  86         /* Clear MSG_DONE bit */
  87         writel(ACE_HASH_MSGDONE_ON, &ace_sha_reg->hash_status);
  88
  89         /* Read hash result */
  90         pdigest = (unsigned int *)pout;
  91         len = (hash_type == ACE_SHA_TYPE_SHA1) ? SHA1_SUM_LEN : SHA256_SUM_LEN;
  92
  93         for (i = 0; i < len / 4; i++)
  94                 pdigest[i] = readl(&ace_sha_reg->hash_result[i]);
  95
  96         /* Clear HRDMA pending bit */
  97         writel(ACE_FC_HRDMA, &ace_sha_reg->fc_intpend);
  98
  99         return 0;
 100 }
 101
 102 void hw_sha256(const unsigned char *pbuf, unsigned int buf_len,
 103                         unsigned char *pout, unsigned int chunk_size)
 104 {
 105         if (ace_sha_hash_digest(pbuf, buf_len, pout, ACE_SHA_TYPE_SHA256))
 106                 debug("ACE was not setup properly or it is faulty\n");
 107 }
 108
 109 void hw_sha1(const unsigned char *pbuf, unsigned int buf_len,
 110                         unsigned char *pout, unsigned int chunk_size)
 111 {
 112         if (ace_sha_hash_digest(pbuf, buf_len, pout, ACE_SHA_TYPE_SHA1))
 113                 debug("ACE was not setup properly or it is faulty\n");
 114 }
 115 #endif /* CONFIG_SHA_HW_ACCEL */
 116
 117 #ifdef CONFIG_LIB_HW_RAND
 118 static unsigned int seed_done;
 119
 120 void srand(unsigned int seed)
 121 {
 122         struct exynos_ace_sfr *reg =
 123                 (struct exynos_ace_sfr *)samsung_get_base_ace_sfr();
 124         int i, status;
 125
 126         /* Seed data */
 127         for (i = 0; i < ACE_HASH_PRNG_REG_NUM; i++)
 128                 writel(seed << i, &reg->hash_seed[i]);
 129
 130         /* Wait for seed setup done */
 131         while (1) {
 132                 status = readl(&reg->hash_status);
 133                 if ((status & ACE_HASH_SEEDSETTING_MASK) ||
 134                     (status & ACE_HASH_PRNGERROR_MASK))
 135                         break;
 136         }
 137
 138         seed_done = 1;
 139 }
 140
 141 unsigned int rand(void)
 142 {
 143         struct exynos_ace_sfr *reg =
 144                 (struct exynos_ace_sfr *)samsung_get_base_ace_sfr();
 145         int i, status;
 146         unsigned int seed = (unsigned int)&status;
 147         unsigned int ret = 0;
 148
 149         if (!seed_done)
 150                 srand(seed);
 151
 152         /* Start PRNG */
 153         writel(ACE_HASH_ENGSEL_PRNG | ACE_HASH_STARTBIT_ON, &reg->hash_control);
 154
 155         /* Wait for PRNG done */
 156         while (1) {
 157                 status = readl(&reg->hash_status);
 158                 if (status & ACE_HASH_PRNGDONE_MASK)
 159                         break;
 160                 if (status & ACE_HASH_PRNGERROR_MASK) {
 161                         seed_done = 0;
 162                         return 0;
 163                 }
 164         }
 165
 166         /* Clear Done IRQ */
 167         writel(ACE_HASH_PRNGDONE_MASK, &reg->hash_status);
 168
 169         /* Read a PRNG result */
 170         for (i = 0; i < ACE_HASH_PRNG_REG_NUM; i++)
 171                 ret += readl(&reg->hash_prng[i]);
 172
 173         seed_done = 0;
 174         return ret;
 175 }
 176
 177 unsigned int rand_r(unsigned int *seedp)
 178 {
 179         srand(*seedp);
 180
 181         return rand();
 182 }
 183 #endif /* CONFIG_LIB_HW_RAND */