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boards: lx2160a: Add support of I2C driver model
[thirdparty/u-boot.git] / drivers / ddr / fsl / main.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2008-2014 Freescale Semiconductor, Inc.
4 */
5
6 /*
7 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
8 * Based on code from spd_sdram.c
9 * Author: James Yang [at freescale.com]
10 */
11
12 #include <common.h>
13 #include <i2c.h>
14 #include <fsl_ddr_sdram.h>
15 #include <fsl_ddr.h>
16
17 /*
18 * CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view
19 * of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for
20 * all Power SoCs. But it could be different for ARM SoCs. For example,
21 * fsl_lsch3 has a mapping mechanism to map DDR memory to ranges (in order) of
22 * 0x00_8000_0000 ~ 0x00_ffff_ffff
23 * 0x80_8000_0000 ~ 0xff_ffff_ffff
24 */
25 #ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
26 #ifdef CONFIG_MPC83xx
27 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_SDRAM_BASE
28 #else
29 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE
30 #endif
31 #endif
32
33 #ifdef CONFIG_PPC
34 #include <asm/fsl_law.h>
35
36 void fsl_ddr_set_lawbar(
37 const common_timing_params_t *memctl_common_params,
38 unsigned int memctl_interleaved,
39 unsigned int ctrl_num);
40 #endif
41
42 void fsl_ddr_set_intl3r(const unsigned int granule_size);
43 #if defined(SPD_EEPROM_ADDRESS) || \
44 defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
45 defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
46 #if (CONFIG_SYS_NUM_DDR_CTLRS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
47 u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
48 [0][0] = SPD_EEPROM_ADDRESS,
49 };
50 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
51 u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
52 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
53 [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
54 };
55 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
56 u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
57 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
58 [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */
59 };
60 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
61 u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
62 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
63 [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
64 [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */
65 [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */
66 };
67 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
68 u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
69 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
70 [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */
71 [2][0] = SPD_EEPROM_ADDRESS3, /* controller 3 */
72 };
73 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
74 u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
75 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
76 [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
77 [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */
78 [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */
79 [2][0] = SPD_EEPROM_ADDRESS5, /* controller 3 */
80 [2][1] = SPD_EEPROM_ADDRESS6, /* controller 3 */
81 };
82
83 #endif
84
85 #define SPD_SPA0_ADDRESS 0x36
86 #define SPD_SPA1_ADDRESS 0x37
87
88 static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
89 {
90 int ret;
91 #ifdef CONFIG_SYS_FSL_DDR4
92 uint8_t dummy = 0;
93 #endif
94
95 #ifndef CONFIG_DM_I2C
96 i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
97 #endif
98
99
100 #ifdef CONFIG_SYS_FSL_DDR4
101 /*
102 * DDR4 SPD has 384 to 512 bytes
103 * To access the lower 256 bytes, we need to set EE page address to 0
104 * To access the upper 256 bytes, we need to set EE page address to 1
105 * See Jedec standar No. 21-C for detail
106 */
107 #ifndef CONFIG_DM_I2C
108 i2c_write(SPD_SPA0_ADDRESS, 0, 1, &dummy, 1);
109 ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, 256);
110 if (!ret) {
111 i2c_write(SPD_SPA1_ADDRESS, 0, 1, &dummy, 1);
112 ret = i2c_read(i2c_address, 0, 1,
113 (uchar *)((ulong)spd + 256),
114 min(256,
115 (int)sizeof(generic_spd_eeprom_t) - 256));
116 }
117 #else
118 struct udevice *dev;
119 int read_len = min(256, (int)sizeof(generic_spd_eeprom_t) - 256);
120
121 ret = i2c_get_chip_for_busnum(0, SPD_SPA0_ADDRESS, 1, &dev);
122 if (!ret)
123 dm_i2c_write(dev, 0, &dummy, 1);
124 ret = i2c_get_chip_for_busnum(0, i2c_address, 1, &dev);
125 if (!ret) {
126 if (!dm_i2c_read(dev, 0, (uchar *)spd, 256)) {
127 if (!i2c_get_chip_for_busnum(0, SPD_SPA1_ADDRESS,
128 1, &dev))
129 dm_i2c_write(dev, 0, &dummy, 1);
130 if (!i2c_get_chip_for_busnum(0, i2c_address, 1, &dev))
131 ret = dm_i2c_read(dev, 0,
132 (uchar *)((ulong)spd + 256),
133 read_len);
134 }
135 }
136 #endif
137
138 #else
139
140 #ifndef CONFIG_DM_I2C
141 ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
142 sizeof(generic_spd_eeprom_t));
143 #else
144 ret = i2c_get_chip_for_busnum(0, i2c_address, 1, &dev);
145 if (!ret)
146 ret = dm_i2c_read(dev, 0, (uchar *)spd,
147 sizeof(generic_spd_eeprom_t));
148 #endif
149
150 #endif
151
152 if (ret) {
153 if (i2c_address ==
154 #ifdef SPD_EEPROM_ADDRESS
155 SPD_EEPROM_ADDRESS
156 #elif defined(SPD_EEPROM_ADDRESS1)
157 SPD_EEPROM_ADDRESS1
158 #endif
159 ) {
160 printf("DDR: failed to read SPD from address %u\n",
161 i2c_address);
162 } else {
163 debug("DDR: failed to read SPD from address %u\n",
164 i2c_address);
165 }
166 memset(spd, 0, sizeof(generic_spd_eeprom_t));
167 }
168 }
169
170 __attribute__((weak, alias("__get_spd")))
171 void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address);
172
173 /* This function allows boards to update SPD address */
174 __weak void update_spd_address(unsigned int ctrl_num,
175 unsigned int slot,
176 unsigned int *addr)
177 {
178 }
179
180 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
181 unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl)
182 {
183 unsigned int i;
184 unsigned int i2c_address = 0;
185
186 if (ctrl_num >= CONFIG_SYS_NUM_DDR_CTLRS) {
187 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
188 return;
189 }
190
191 for (i = 0; i < dimm_slots_per_ctrl; i++) {
192 i2c_address = spd_i2c_addr[ctrl_num][i];
193 update_spd_address(ctrl_num, i, &i2c_address);
194 get_spd(&(ctrl_dimms_spd[i]), i2c_address);
195 }
196 }
197 #else
198 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
199 unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl)
200 {
201 }
202 #endif /* SPD_EEPROM_ADDRESSx */
203
204 /*
205 * ASSUMPTIONS:
206 * - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller
207 * - Same memory data bus width on all controllers
208 *
209 * NOTES:
210 *
211 * The memory controller and associated documentation use confusing
212 * terminology when referring to the orgranization of DRAM.
213 *
214 * Here is a terminology translation table:
215 *
216 * memory controller/documention |industry |this code |signals
217 * -------------------------------|-----------|-----------|-----------------
218 * physical bank/bank |rank |rank |chip select (CS)
219 * logical bank/sub-bank |bank |bank |bank address (BA)
220 * page/row |row |page |row address
221 * ??? |column |column |column address
222 *
223 * The naming confusion is further exacerbated by the descriptions of the
224 * memory controller interleaving feature, where accesses are interleaved
225 * _BETWEEN_ two seperate memory controllers. This is configured only in
226 * CS0_CONFIG[INTLV_CTL] of each memory controller.
227 *
228 * memory controller documentation | number of chip selects
229 * | per memory controller supported
230 * --------------------------------|-----------------------------------------
231 * cache line interleaving | 1 (CS0 only)
232 * page interleaving | 1 (CS0 only)
233 * bank interleaving | 1 (CS0 only)
234 * superbank interleraving | depends on bank (chip select)
235 * | interleraving [rank interleaving]
236 * | mode used on every memory controller
237 *
238 * Even further confusing is the existence of the interleaving feature
239 * _WITHIN_ each memory controller. The feature is referred to in
240 * documentation as chip select interleaving or bank interleaving,
241 * although it is configured in the DDR_SDRAM_CFG field.
242 *
243 * Name of field | documentation name | this code
244 * -----------------------------|-----------------------|------------------
245 * DDR_SDRAM_CFG[BA_INTLV_CTL] | Bank (chip select) | rank interleaving
246 * | interleaving
247 */
248
249 const char *step_string_tbl[] = {
250 "STEP_GET_SPD",
251 "STEP_COMPUTE_DIMM_PARMS",
252 "STEP_COMPUTE_COMMON_PARMS",
253 "STEP_GATHER_OPTS",
254 "STEP_ASSIGN_ADDRESSES",
255 "STEP_COMPUTE_REGS",
256 "STEP_PROGRAM_REGS",
257 "STEP_ALL"
258 };
259
260 const char * step_to_string(unsigned int step) {
261
262 unsigned int s = __ilog2(step);
263
264 if ((1 << s) != step)
265 return step_string_tbl[7];
266
267 if (s >= ARRAY_SIZE(step_string_tbl)) {
268 printf("Error for the step in %s\n", __func__);
269 s = 0;
270 }
271
272 return step_string_tbl[s];
273 }
274
275 static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo,
276 unsigned int dbw_cap_adj[])
277 {
278 unsigned int i, j;
279 unsigned long long total_mem, current_mem_base, total_ctlr_mem;
280 unsigned long long rank_density, ctlr_density = 0;
281 unsigned int first_ctrl = pinfo->first_ctrl;
282 unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
283
284 /*
285 * If a reduced data width is requested, but the SPD
286 * specifies a physically wider device, adjust the
287 * computed dimm capacities accordingly before
288 * assigning addresses.
289 */
290 for (i = first_ctrl; i <= last_ctrl; i++) {
291 unsigned int found = 0;
292
293 switch (pinfo->memctl_opts[i].data_bus_width) {
294 case 2:
295 /* 16-bit */
296 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
297 unsigned int dw;
298 if (!pinfo->dimm_params[i][j].n_ranks)
299 continue;
300 dw = pinfo->dimm_params[i][j].primary_sdram_width;
301 if ((dw == 72 || dw == 64)) {
302 dbw_cap_adj[i] = 2;
303 break;
304 } else if ((dw == 40 || dw == 32)) {
305 dbw_cap_adj[i] = 1;
306 break;
307 }
308 }
309 break;
310
311 case 1:
312 /* 32-bit */
313 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
314 unsigned int dw;
315 dw = pinfo->dimm_params[i][j].data_width;
316 if (pinfo->dimm_params[i][j].n_ranks
317 && (dw == 72 || dw == 64)) {
318 /*
319 * FIXME: can't really do it
320 * like this because this just
321 * further reduces the memory
322 */
323 found = 1;
324 break;
325 }
326 }
327 if (found) {
328 dbw_cap_adj[i] = 1;
329 }
330 break;
331
332 case 0:
333 /* 64-bit */
334 break;
335
336 default:
337 printf("unexpected data bus width "
338 "specified controller %u\n", i);
339 return 1;
340 }
341 debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]);
342 }
343
344 current_mem_base = pinfo->mem_base;
345 total_mem = 0;
346 if (pinfo->memctl_opts[first_ctrl].memctl_interleaving) {
347 rank_density = pinfo->dimm_params[first_ctrl][0].rank_density >>
348 dbw_cap_adj[first_ctrl];
349 switch (pinfo->memctl_opts[first_ctrl].ba_intlv_ctl &
350 FSL_DDR_CS0_CS1_CS2_CS3) {
351 case FSL_DDR_CS0_CS1_CS2_CS3:
352 ctlr_density = 4 * rank_density;
353 break;
354 case FSL_DDR_CS0_CS1:
355 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
356 ctlr_density = 2 * rank_density;
357 break;
358 case FSL_DDR_CS2_CS3:
359 default:
360 ctlr_density = rank_density;
361 break;
362 }
363 debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
364 rank_density, ctlr_density);
365 for (i = first_ctrl; i <= last_ctrl; i++) {
366 if (pinfo->memctl_opts[i].memctl_interleaving) {
367 switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
368 case FSL_DDR_256B_INTERLEAVING:
369 case FSL_DDR_CACHE_LINE_INTERLEAVING:
370 case FSL_DDR_PAGE_INTERLEAVING:
371 case FSL_DDR_BANK_INTERLEAVING:
372 case FSL_DDR_SUPERBANK_INTERLEAVING:
373 total_ctlr_mem = 2 * ctlr_density;
374 break;
375 case FSL_DDR_3WAY_1KB_INTERLEAVING:
376 case FSL_DDR_3WAY_4KB_INTERLEAVING:
377 case FSL_DDR_3WAY_8KB_INTERLEAVING:
378 total_ctlr_mem = 3 * ctlr_density;
379 break;
380 case FSL_DDR_4WAY_1KB_INTERLEAVING:
381 case FSL_DDR_4WAY_4KB_INTERLEAVING:
382 case FSL_DDR_4WAY_8KB_INTERLEAVING:
383 total_ctlr_mem = 4 * ctlr_density;
384 break;
385 default:
386 panic("Unknown interleaving mode");
387 }
388 pinfo->common_timing_params[i].base_address =
389 current_mem_base;
390 pinfo->common_timing_params[i].total_mem =
391 total_ctlr_mem;
392 total_mem = current_mem_base + total_ctlr_mem;
393 debug("ctrl %d base 0x%llx\n", i, current_mem_base);
394 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
395 } else {
396 /* when 3rd controller not interleaved */
397 current_mem_base = total_mem;
398 total_ctlr_mem = 0;
399 pinfo->common_timing_params[i].base_address =
400 current_mem_base;
401 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
402 unsigned long long cap =
403 pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
404 pinfo->dimm_params[i][j].base_address =
405 current_mem_base;
406 debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
407 current_mem_base += cap;
408 total_ctlr_mem += cap;
409 }
410 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
411 pinfo->common_timing_params[i].total_mem =
412 total_ctlr_mem;
413 total_mem += total_ctlr_mem;
414 }
415 }
416 } else {
417 /*
418 * Simple linear assignment if memory
419 * controllers are not interleaved.
420 */
421 for (i = first_ctrl; i <= last_ctrl; i++) {
422 total_ctlr_mem = 0;
423 pinfo->common_timing_params[i].base_address =
424 current_mem_base;
425 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
426 /* Compute DIMM base addresses. */
427 unsigned long long cap =
428 pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
429 pinfo->dimm_params[i][j].base_address =
430 current_mem_base;
431 debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
432 current_mem_base += cap;
433 total_ctlr_mem += cap;
434 }
435 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
436 pinfo->common_timing_params[i].total_mem =
437 total_ctlr_mem;
438 total_mem += total_ctlr_mem;
439 }
440 }
441 debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
442
443 return total_mem;
444 }
445
446 /* Use weak function to allow board file to override the address assignment */
447 __attribute__((weak, alias("__step_assign_addresses")))
448 unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
449 unsigned int dbw_cap_adj[]);
450
451 unsigned long long
452 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
453 unsigned int size_only)
454 {
455 unsigned int i, j;
456 unsigned long long total_mem = 0;
457 int assert_reset = 0;
458 unsigned int first_ctrl = pinfo->first_ctrl;
459 unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
460 __maybe_unused int retval;
461 __maybe_unused bool goodspd = false;
462 __maybe_unused int dimm_slots_per_ctrl = pinfo->dimm_slots_per_ctrl;
463
464 fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;
465 common_timing_params_t *timing_params = pinfo->common_timing_params;
466 if (pinfo->board_need_mem_reset)
467 assert_reset = pinfo->board_need_mem_reset();
468
469 /* data bus width capacity adjust shift amount */
470 unsigned int dbw_capacity_adjust[CONFIG_SYS_NUM_DDR_CTLRS];
471
472 for (i = first_ctrl; i <= last_ctrl; i++)
473 dbw_capacity_adjust[i] = 0;
474
475 debug("starting at step %u (%s)\n",
476 start_step, step_to_string(start_step));
477
478 switch (start_step) {
479 case STEP_GET_SPD:
480 #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
481 /* STEP 1: Gather all DIMM SPD data */
482 for (i = first_ctrl; i <= last_ctrl; i++) {
483 fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i,
484 dimm_slots_per_ctrl);
485 }
486
487 case STEP_COMPUTE_DIMM_PARMS:
488 /* STEP 2: Compute DIMM parameters from SPD data */
489
490 for (i = first_ctrl; i <= last_ctrl; i++) {
491 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
492 generic_spd_eeprom_t *spd =
493 &(pinfo->spd_installed_dimms[i][j]);
494 dimm_params_t *pdimm =
495 &(pinfo->dimm_params[i][j]);
496 retval = compute_dimm_parameters(
497 i, spd, pdimm, j);
498 #ifdef CONFIG_SYS_DDR_RAW_TIMING
499 if (!j && retval) {
500 printf("SPD error on controller %d! "
501 "Trying fallback to raw timing "
502 "calculation\n", i);
503 retval = fsl_ddr_get_dimm_params(pdimm,
504 i, j);
505 }
506 #else
507 if (retval == 2) {
508 printf("Error: compute_dimm_parameters"
509 " non-zero returned FATAL value "
510 "for memctl=%u dimm=%u\n", i, j);
511 return 0;
512 }
513 #endif
514 if (retval) {
515 debug("Warning: compute_dimm_parameters"
516 " non-zero return value for memctl=%u "
517 "dimm=%u\n", i, j);
518 } else {
519 goodspd = true;
520 }
521 }
522 }
523 if (!goodspd) {
524 /*
525 * No valid SPD found
526 * Throw an error if this is for main memory, i.e.
527 * first_ctrl == 0. Otherwise, siliently return 0
528 * as the memory size.
529 */
530 if (first_ctrl == 0)
531 printf("Error: No valid SPD detected.\n");
532
533 return 0;
534 }
535 #elif defined(CONFIG_SYS_DDR_RAW_TIMING)
536 case STEP_COMPUTE_DIMM_PARMS:
537 for (i = first_ctrl; i <= last_ctrl; i++) {
538 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
539 dimm_params_t *pdimm =
540 &(pinfo->dimm_params[i][j]);
541 fsl_ddr_get_dimm_params(pdimm, i, j);
542 }
543 }
544 debug("Filling dimm parameters from board specific file\n");
545 #endif
546 case STEP_COMPUTE_COMMON_PARMS:
547 /*
548 * STEP 3: Compute a common set of timing parameters
549 * suitable for all of the DIMMs on each memory controller
550 */
551 for (i = first_ctrl; i <= last_ctrl; i++) {
552 debug("Computing lowest common DIMM"
553 " parameters for memctl=%u\n", i);
554 compute_lowest_common_dimm_parameters
555 (i,
556 pinfo->dimm_params[i],
557 &timing_params[i],
558 CONFIG_DIMM_SLOTS_PER_CTLR);
559 }
560
561 case STEP_GATHER_OPTS:
562 /* STEP 4: Gather configuration requirements from user */
563 for (i = first_ctrl; i <= last_ctrl; i++) {
564 debug("Reloading memory controller "
565 "configuration options for memctl=%u\n", i);
566 /*
567 * This "reloads" the memory controller options
568 * to defaults. If the user "edits" an option,
569 * next_step points to the step after this,
570 * which is currently STEP_ASSIGN_ADDRESSES.
571 */
572 populate_memctl_options(
573 &timing_params[i],
574 &pinfo->memctl_opts[i],
575 pinfo->dimm_params[i], i);
576 /*
577 * For RDIMMs, JEDEC spec requires clocks to be stable
578 * before reset signal is deasserted. For the boards
579 * using fixed parameters, this function should be
580 * be called from board init file.
581 */
582 if (timing_params[i].all_dimms_registered)
583 assert_reset = 1;
584 }
585 if (assert_reset && !size_only) {
586 if (pinfo->board_mem_reset) {
587 debug("Asserting mem reset\n");
588 pinfo->board_mem_reset();
589 } else {
590 debug("Asserting mem reset missing\n");
591 }
592 }
593
594 case STEP_ASSIGN_ADDRESSES:
595 /* STEP 5: Assign addresses to chip selects */
596 check_interleaving_options(pinfo);
597 total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust);
598 debug("Total mem %llu assigned\n", total_mem);
599
600 case STEP_COMPUTE_REGS:
601 /* STEP 6: compute controller register values */
602 debug("FSL Memory ctrl register computation\n");
603 for (i = first_ctrl; i <= last_ctrl; i++) {
604 if (timing_params[i].ndimms_present == 0) {
605 memset(&ddr_reg[i], 0,
606 sizeof(fsl_ddr_cfg_regs_t));
607 continue;
608 }
609
610 compute_fsl_memctl_config_regs
611 (i,
612 &pinfo->memctl_opts[i],
613 &ddr_reg[i], &timing_params[i],
614 pinfo->dimm_params[i],
615 dbw_capacity_adjust[i],
616 size_only);
617 }
618
619 default:
620 break;
621 }
622
623 {
624 /*
625 * Compute the amount of memory available just by
626 * looking for the highest valid CSn_BNDS value.
627 * This allows us to also experiment with using
628 * only CS0 when using dual-rank DIMMs.
629 */
630 unsigned int max_end = 0;
631
632 for (i = first_ctrl; i <= last_ctrl; i++) {
633 for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) {
634 fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
635 if (reg->cs[j].config & 0x80000000) {
636 unsigned int end;
637 /*
638 * 0xfffffff is a special value we put
639 * for unused bnds
640 */
641 if (reg->cs[j].bnds == 0xffffffff)
642 continue;
643 end = reg->cs[j].bnds & 0xffff;
644 if (end > max_end) {
645 max_end = end;
646 }
647 }
648 }
649 }
650
651 total_mem = 1 + (((unsigned long long)max_end << 24ULL) |
652 0xFFFFFFULL) - pinfo->mem_base;
653 }
654
655 return total_mem;
656 }
657
658 phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)
659 {
660 unsigned int i, first_ctrl, last_ctrl;
661 #ifdef CONFIG_PPC
662 unsigned int law_memctl = LAW_TRGT_IF_DDR_1;
663 #endif
664 unsigned long long total_memory;
665 int deassert_reset = 0;
666
667 first_ctrl = pinfo->first_ctrl;
668 last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
669
670 /* Compute it once normally. */
671 #ifdef CONFIG_FSL_DDR_INTERACTIVE
672 if (tstc() && (getc() == 'd')) { /* we got a key press of 'd' */
673 total_memory = fsl_ddr_interactive(pinfo, 0);
674 } else if (fsl_ddr_interactive_env_var_exists()) {
675 total_memory = fsl_ddr_interactive(pinfo, 1);
676 } else
677 #endif
678 total_memory = fsl_ddr_compute(pinfo, STEP_GET_SPD, 0);
679
680 /* setup 3-way interleaving before enabling DDRC */
681 switch (pinfo->memctl_opts[first_ctrl].memctl_interleaving_mode) {
682 case FSL_DDR_3WAY_1KB_INTERLEAVING:
683 case FSL_DDR_3WAY_4KB_INTERLEAVING:
684 case FSL_DDR_3WAY_8KB_INTERLEAVING:
685 fsl_ddr_set_intl3r(
686 pinfo->memctl_opts[first_ctrl].
687 memctl_interleaving_mode);
688 break;
689 default:
690 break;
691 }
692
693 /*
694 * Program configuration registers.
695 * JEDEC specs requires clocks to be stable before deasserting reset
696 * for RDIMMs. Clocks start after chip select is enabled and clock
697 * control register is set. During step 1, all controllers have their
698 * registers set but not enabled. Step 2 proceeds after deasserting
699 * reset through board FPGA or GPIO.
700 * For non-registered DIMMs, initialization can go through but it is
701 * also OK to follow the same flow.
702 */
703 if (pinfo->board_need_mem_reset)
704 deassert_reset = pinfo->board_need_mem_reset();
705 for (i = first_ctrl; i <= last_ctrl; i++) {
706 if (pinfo->common_timing_params[i].all_dimms_registered)
707 deassert_reset = 1;
708 }
709 for (i = first_ctrl; i <= last_ctrl; i++) {
710 debug("Programming controller %u\n", i);
711 if (pinfo->common_timing_params[i].ndimms_present == 0) {
712 debug("No dimms present on controller %u; "
713 "skipping programming\n", i);
714 continue;
715 }
716 /*
717 * The following call with step = 1 returns before enabling
718 * the controller. It has to finish with step = 2 later.
719 */
720 fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]), i,
721 deassert_reset ? 1 : 0);
722 }
723 if (deassert_reset) {
724 /* Use board FPGA or GPIO to deassert reset signal */
725 if (pinfo->board_mem_de_reset) {
726 debug("Deasserting mem reset\n");
727 pinfo->board_mem_de_reset();
728 } else {
729 debug("Deasserting mem reset missing\n");
730 }
731 for (i = first_ctrl; i <= last_ctrl; i++) {
732 /* Call with step = 2 to continue initialization */
733 fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]),
734 i, 2);
735 }
736 }
737
738 #ifdef CONFIG_FSL_DDR_SYNC_REFRESH
739 fsl_ddr_sync_memctl_refresh(first_ctrl, last_ctrl);
740 #endif
741
742 #ifdef CONFIG_PPC
743 /* program LAWs */
744 for (i = first_ctrl; i <= last_ctrl; i++) {
745 if (pinfo->memctl_opts[i].memctl_interleaving) {
746 switch (pinfo->memctl_opts[i].
747 memctl_interleaving_mode) {
748 case FSL_DDR_CACHE_LINE_INTERLEAVING:
749 case FSL_DDR_PAGE_INTERLEAVING:
750 case FSL_DDR_BANK_INTERLEAVING:
751 case FSL_DDR_SUPERBANK_INTERLEAVING:
752 if (i % 2)
753 break;
754 if (i == 0) {
755 law_memctl = LAW_TRGT_IF_DDR_INTRLV;
756 fsl_ddr_set_lawbar(
757 &pinfo->common_timing_params[i],
758 law_memctl, i);
759 }
760 #if CONFIG_SYS_NUM_DDR_CTLRS > 3
761 else if (i == 2) {
762 law_memctl = LAW_TRGT_IF_DDR_INTLV_34;
763 fsl_ddr_set_lawbar(
764 &pinfo->common_timing_params[i],
765 law_memctl, i);
766 }
767 #endif
768 break;
769 case FSL_DDR_3WAY_1KB_INTERLEAVING:
770 case FSL_DDR_3WAY_4KB_INTERLEAVING:
771 case FSL_DDR_3WAY_8KB_INTERLEAVING:
772 law_memctl = LAW_TRGT_IF_DDR_INTLV_123;
773 if (i == 0) {
774 fsl_ddr_set_lawbar(
775 &pinfo->common_timing_params[i],
776 law_memctl, i);
777 }
778 break;
779 case FSL_DDR_4WAY_1KB_INTERLEAVING:
780 case FSL_DDR_4WAY_4KB_INTERLEAVING:
781 case FSL_DDR_4WAY_8KB_INTERLEAVING:
782 law_memctl = LAW_TRGT_IF_DDR_INTLV_1234;
783 if (i == 0)
784 fsl_ddr_set_lawbar(
785 &pinfo->common_timing_params[i],
786 law_memctl, i);
787 /* place holder for future 4-way interleaving */
788 break;
789 default:
790 break;
791 }
792 } else {
793 switch (i) {
794 case 0:
795 law_memctl = LAW_TRGT_IF_DDR_1;
796 break;
797 case 1:
798 law_memctl = LAW_TRGT_IF_DDR_2;
799 break;
800 case 2:
801 law_memctl = LAW_TRGT_IF_DDR_3;
802 break;
803 case 3:
804 law_memctl = LAW_TRGT_IF_DDR_4;
805 break;
806 default:
807 break;
808 }
809 fsl_ddr_set_lawbar(&pinfo->common_timing_params[i],
810 law_memctl, i);
811 }
812 }
813 #endif
814
815 debug("total_memory by %s = %llu\n", __func__, total_memory);
816
817 #if !defined(CONFIG_PHYS_64BIT)
818 /* Check for 4G or more. Bad. */
819 if ((first_ctrl == 0) && (total_memory >= (1ull << 32))) {
820 puts("Detected ");
821 print_size(total_memory, " of memory\n");
822 printf(" This U-Boot only supports < 4G of DDR\n");
823 printf(" You could rebuild it with CONFIG_PHYS_64BIT\n");
824 printf(" "); /* re-align to match init_dram print */
825 total_memory = CONFIG_MAX_MEM_MAPPED;
826 }
827 #endif
828
829 return total_memory;
830 }
831
832 /*
833 * fsl_ddr_sdram(void) -- this is the main function to be
834 * called by dram_init() in the board file.
835 *
836 * It returns amount of memory configured in bytes.
837 */
838 phys_size_t fsl_ddr_sdram(void)
839 {
840 fsl_ddr_info_t info;
841
842 /* Reset info structure. */
843 memset(&info, 0, sizeof(fsl_ddr_info_t));
844 info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
845 info.first_ctrl = 0;
846 info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS;
847 info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR;
848 info.board_need_mem_reset = board_need_mem_reset;
849 info.board_mem_reset = board_assert_mem_reset;
850 info.board_mem_de_reset = board_deassert_mem_reset;
851 remove_unused_controllers(&info);
852
853 return __fsl_ddr_sdram(&info);
854 }
855
856 #ifdef CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
857 phys_size_t fsl_other_ddr_sdram(unsigned long long base,
858 unsigned int first_ctrl,
859 unsigned int num_ctrls,
860 unsigned int dimm_slots_per_ctrl,
861 int (*board_need_reset)(void),
862 void (*board_reset)(void),
863 void (*board_de_reset)(void))
864 {
865 fsl_ddr_info_t info;
866
867 /* Reset info structure. */
868 memset(&info, 0, sizeof(fsl_ddr_info_t));
869 info.mem_base = base;
870 info.first_ctrl = first_ctrl;
871 info.num_ctrls = num_ctrls;
872 info.dimm_slots_per_ctrl = dimm_slots_per_ctrl;
873 info.board_need_mem_reset = board_need_reset;
874 info.board_mem_reset = board_reset;
875 info.board_mem_de_reset = board_de_reset;
876
877 return __fsl_ddr_sdram(&info);
878 }
879 #endif
880
881 /*
882 * fsl_ddr_sdram_size(first_ctrl, last_intlv) - This function only returns the
883 * size of the total memory without setting ddr control registers.
884 */
885 phys_size_t
886 fsl_ddr_sdram_size(void)
887 {
888 fsl_ddr_info_t info;
889 unsigned long long total_memory = 0;
890
891 memset(&info, 0 , sizeof(fsl_ddr_info_t));
892 info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
893 info.first_ctrl = 0;
894 info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS;
895 info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR;
896 info.board_need_mem_reset = NULL;
897 remove_unused_controllers(&info);
898
899 /* Compute it once normally. */
900 total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1);
901
902 return total_memory;
903 }
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