drivers/ddr/marvell/a38x/ddr_ml_wrapper.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (C) Marvell International Ltd. and its affiliates
   4  */
   5
   6 #ifndef _DDR_ML_WRAPPER_H
   7 #define _DDR_ML_WRAPPER_H
   8
   9 #include <i2c.h>
  10 #include <spl.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/cpu.h>
  13 #include <asm/arch/soc.h>
  14
  15 #define INTER_REGS_BASE SOC_REGS_PHY_BASE
  16
  17 /*
  18  * MV_DEBUG_INIT need to be defines, otherwise the output of the
  19  * DDR2 training code is not complete and misleading
  20  */
  21 #define MV_DEBUG_INIT
  22
  23 #ifdef MV_DEBUG_INIT
  24 #define DEBUG_INIT_S(s)                 puts(s)
  25 #define DEBUG_INIT_D(d, l)              printf("%x", d)
  26 #define DEBUG_INIT_D_10(d, l)           printf("%d", d)
  27 #else
  28 #define DEBUG_INIT_S(s)
  29 #define DEBUG_INIT_D(d, l)
  30 #define DEBUG_INIT_D_10(d, l)
  31 #endif
  32
  33 #ifdef MV_DEBUG_INIT_FULL
  34 #define DEBUG_INIT_FULL_S(s)            puts(s)
  35 #define DEBUG_INIT_FULL_D(d, l)         printf("%x", d)
  36 #define DEBUG_INIT_FULL_D_10(d, l)      printf("%d", d)
  37 #define DEBUG_WR_REG(reg, val) \
  38         { DEBUG_INIT_S("Write Reg: 0x"); DEBUG_INIT_D((reg), 8); \
  39           DEBUG_INIT_S("= "); DEBUG_INIT_D((val), 8); DEBUG_INIT_S("\n"); }
  40 #define DEBUG_RD_REG(reg, val) \
  41         { DEBUG_INIT_S("Read  Reg: 0x"); DEBUG_INIT_D((reg), 8); \
  42           DEBUG_INIT_S("= "); DEBUG_INIT_D((val), 8); DEBUG_INIT_S("\n"); }
  43 #else
  44 #define DEBUG_INIT_FULL_S(s)
  45 #define DEBUG_INIT_FULL_D(d, l)
  46 #define DEBUG_INIT_FULL_D_10(d, l)
  47 #define DEBUG_WR_REG(reg, val)
  48 #define DEBUG_RD_REG(reg, val)
  49 #endif
  50
  51 #define DEBUG_INIT_FULL_C(s, d, l)                      \
  52         { DEBUG_INIT_FULL_S(s);                         \
  53           DEBUG_INIT_FULL_D(d, l);                      \
  54           DEBUG_INIT_FULL_S("\n"); }
  55 #define DEBUG_INIT_C(s, d, l) \
  56         { DEBUG_INIT_S(s); DEBUG_INIT_D(d, l); DEBUG_INIT_S("\n"); }
  57
  58 /*
  59  * Debug (Enable/Disable modules) and Error report
  60  */
  61
  62 #ifdef BASIC_DEBUG
  63 #define MV_DEBUG_WL
  64 #define MV_DEBUG_RL
  65 #define MV_DEBUG_DQS_RESULTS
  66 #endif
  67
  68 #ifdef FULL_DEBUG
  69 #define MV_DEBUG_WL
  70 #define MV_DEBUG_RL
  71 #define MV_DEBUG_DQS
  72
  73 #define MV_DEBUG_PBS
  74 #define MV_DEBUG_DFS
  75 #define MV_DEBUG_MAIN_FULL
  76 #define MV_DEBUG_DFS_FULL
  77 #define MV_DEBUG_DQS_FULL
  78 #define MV_DEBUG_RL_FULL
  79 #define MV_DEBUG_WL_FULL
  80 #endif
  81
  82
  83 /* The following is a list of Marvell status */
  84 #define MV_ERROR        (-1)
  85 #define MV_OK           (0x00)  /* Operation succeeded                   */
  86 #define MV_FAIL         (0x01)  /* Operation failed                      */
  87 #define MV_BAD_VALUE    (0x02)  /* Illegal value (general)               */
  88 #define MV_OUT_OF_RANGE (0x03)  /* The value is out of range             */
  89 #define MV_BAD_PARAM    (0x04)  /* Illegal parameter in function called  */
  90 #define MV_BAD_PTR      (0x05)  /* Illegal pointer value                 */
  91 #define MV_BAD_SIZE     (0x06)  /* Illegal size                          */
  92 #define MV_BAD_STATE    (0x07)  /* Illegal state of state machine        */
  93 #define MV_SET_ERROR    (0x08)  /* Set operation failed                  */
  94 #define MV_GET_ERROR    (0x09)  /* Get operation failed                  */
  95 #define MV_CREATE_ERROR (0x0a)  /* Fail while creating an item           */
  96 #define MV_NOT_FOUND    (0x0b)  /* Item not found                        */
  97 #define MV_NO_MORE      (0x0c)  /* No more items found                   */
  98 #define MV_NO_SUCH      (0x0d)  /* No such item                          */
  99 #define MV_TIMEOUT      (0x0e)  /* Time Out                              */
 100 #define MV_NO_CHANGE    (0x0f)  /* Parameter(s) is already in this value */
 101 #define MV_NOT_SUPPORTED (0x10) /* This request is not support           */
 102 #define MV_NOT_IMPLEMENTED (0x11) /* Request supported but not implemented*/
 103 #define MV_NOT_INITIALIZED (0x12) /* The item is not initialized          */
 104 #define MV_NO_RESOURCE  (0x13)  /* Resource not available (memory ...)   */
 105 #define MV_FULL         (0x14)  /* Item is full (Queue or table etc...)  */
 106 #define MV_EMPTY        (0x15)  /* Item is empty (Queue or table etc...) */
 107 #define MV_INIT_ERROR   (0x16)  /* Error occurred while INIT process     */
 108 #define MV_HW_ERROR     (0x17)  /* Hardware error                        */
 109 #define MV_TX_ERROR     (0x18)  /* Transmit operation not succeeded      */
 110 #define MV_RX_ERROR     (0x19)  /* Recieve operation not succeeded       */
 111 #define MV_NOT_READY    (0x1a)  /* The other side is not ready yet       */
 112 #define MV_ALREADY_EXIST (0x1b) /* Tried to create existing item         */
 113 #define MV_OUT_OF_CPU_MEM   (0x1c) /* Cpu memory allocation failed.      */
 114 #define MV_NOT_STARTED  (0x1d)  /* Not started yet                       */
 115 #define MV_BUSY         (0x1e)  /* Item is busy.                         */
 116 #define MV_TERMINATE    (0x1f)  /* Item terminates it's work.            */
 117 #define MV_NOT_ALIGNED  (0x20)  /* Wrong alignment                       */
 118 #define MV_NOT_ALLOWED  (0x21)  /* Operation NOT allowed                 */
 119 #define MV_WRITE_PROTECT (0x22) /* Write protected                       */
 120 #define MV_INVALID      (int)(-1)
 121
 122 /*
 123  * Accessor functions for the registers
 124  */
 125 static inline void reg_write(u32 addr, u32 val)
 126 {
 127         writel(val, INTER_REGS_BASE + addr);
 128 }
 129
 130 static inline u32 reg_read(u32 addr)
 131 {
 132         return readl(INTER_REGS_BASE + addr);
 133 }
 134
 135 static inline void reg_bit_set(u32 addr, u32 mask)
 136 {
 137         setbits_le32(INTER_REGS_BASE + addr, mask);
 138 }
 139
 140 static inline void reg_bit_clr(u32 addr, u32 mask)
 141 {
 142         clrbits_le32(INTER_REGS_BASE + addr, mask);
 143 }
 144
 145 #endif /* _DDR_ML_WRAPPER_H */