1 // SPDX-License-Identifier: GPL-2.0
3 * core.c - DesignWare USB3 DRD Controller Core file
5 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
10 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.c) and ported
13 * commit cd72f890d2 : usb: dwc3: core: enable phy suspend quirk on non-FPGA
19 #include <dwc3-uboot.h>
20 #include <dm/device_compat.h>
21 #include <dm/devres.h>
22 #include <linux/bug.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/err.h>
26 #include <linux/ioport.h>
28 #include <generic-phy.h>
29 #include <linux/usb/ch9.h>
30 #include <linux/usb/gadget.h>
36 #include "linux-compat.h"
38 static LIST_HEAD(dwc3_list
);
39 /* -------------------------------------------------------------------------- */
41 static void dwc3_set_mode(struct dwc3
*dwc
, u32 mode
)
45 reg
= dwc3_readl(dwc
->regs
, DWC3_GCTL
);
46 reg
&= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG
));
47 reg
|= DWC3_GCTL_PRTCAPDIR(mode
);
48 dwc3_writel(dwc
->regs
, DWC3_GCTL
, reg
);
52 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
53 * @dwc: pointer to our context structure
55 static int dwc3_core_soft_reset(struct dwc3
*dwc
)
59 /* Before Resetting PHY, put Core in Reset */
60 reg
= dwc3_readl(dwc
->regs
, DWC3_GCTL
);
61 reg
|= DWC3_GCTL_CORESOFTRESET
;
62 dwc3_writel(dwc
->regs
, DWC3_GCTL
, reg
);
64 /* Assert USB3 PHY reset */
65 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB3PIPECTL(0));
66 reg
|= DWC3_GUSB3PIPECTL_PHYSOFTRST
;
67 dwc3_writel(dwc
->regs
, DWC3_GUSB3PIPECTL(0), reg
);
69 /* Assert USB2 PHY reset */
70 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB2PHYCFG(0));
71 reg
|= DWC3_GUSB2PHYCFG_PHYSOFTRST
;
72 dwc3_writel(dwc
->regs
, DWC3_GUSB2PHYCFG(0), reg
);
76 /* Clear USB3 PHY reset */
77 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB3PIPECTL(0));
78 reg
&= ~DWC3_GUSB3PIPECTL_PHYSOFTRST
;
79 dwc3_writel(dwc
->regs
, DWC3_GUSB3PIPECTL(0), reg
);
81 /* Clear USB2 PHY reset */
82 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB2PHYCFG(0));
83 reg
&= ~DWC3_GUSB2PHYCFG_PHYSOFTRST
;
84 dwc3_writel(dwc
->regs
, DWC3_GUSB2PHYCFG(0), reg
);
88 /* After PHYs are stable we can take Core out of reset state */
89 reg
= dwc3_readl(dwc
->regs
, DWC3_GCTL
);
90 reg
&= ~DWC3_GCTL_CORESOFTRESET
;
91 dwc3_writel(dwc
->regs
, DWC3_GCTL
, reg
);
97 * dwc3_free_one_event_buffer - Frees one event buffer
98 * @dwc: Pointer to our controller context structure
99 * @evt: Pointer to event buffer to be freed
101 static void dwc3_free_one_event_buffer(struct dwc3
*dwc
,
102 struct dwc3_event_buffer
*evt
)
104 dma_free_coherent(evt
->buf
);
108 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
109 * @dwc: Pointer to our controller context structure
110 * @length: size of the event buffer
112 * Returns a pointer to the allocated event buffer structure on success
113 * otherwise ERR_PTR(errno).
115 static struct dwc3_event_buffer
*dwc3_alloc_one_event_buffer(struct dwc3
*dwc
,
118 struct dwc3_event_buffer
*evt
;
120 evt
= devm_kzalloc((struct udevice
*)dwc
->dev
, sizeof(*evt
),
123 return ERR_PTR(-ENOMEM
);
126 evt
->length
= length
;
127 evt
->buf
= dma_alloc_coherent(length
,
128 (unsigned long *)&evt
->dma
);
130 return ERR_PTR(-ENOMEM
);
132 dwc3_flush_cache((uintptr_t)evt
->buf
, evt
->length
);
138 * dwc3_free_event_buffers - frees all allocated event buffers
139 * @dwc: Pointer to our controller context structure
141 static void dwc3_free_event_buffers(struct dwc3
*dwc
)
143 struct dwc3_event_buffer
*evt
;
146 for (i
= 0; i
< dwc
->num_event_buffers
; i
++) {
147 evt
= dwc
->ev_buffs
[i
];
149 dwc3_free_one_event_buffer(dwc
, evt
);
154 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
155 * @dwc: pointer to our controller context structure
156 * @length: size of event buffer
158 * Returns 0 on success otherwise negative errno. In the error case, dwc
159 * may contain some buffers allocated but not all which were requested.
161 static int dwc3_alloc_event_buffers(struct dwc3
*dwc
, unsigned length
)
166 num
= DWC3_NUM_INT(dwc
->hwparams
.hwparams1
);
167 dwc
->num_event_buffers
= num
;
169 dwc
->ev_buffs
= memalign(CONFIG_SYS_CACHELINE_SIZE
,
170 sizeof(*dwc
->ev_buffs
) * num
);
174 for (i
= 0; i
< num
; i
++) {
175 struct dwc3_event_buffer
*evt
;
177 evt
= dwc3_alloc_one_event_buffer(dwc
, length
);
179 dev_err(dwc
->dev
, "can't allocate event buffer\n");
182 dwc
->ev_buffs
[i
] = evt
;
189 * dwc3_event_buffers_setup - setup our allocated event buffers
190 * @dwc: pointer to our controller context structure
192 * Returns 0 on success otherwise negative errno.
194 static int dwc3_event_buffers_setup(struct dwc3
*dwc
)
196 struct dwc3_event_buffer
*evt
;
199 for (n
= 0; n
< dwc
->num_event_buffers
; n
++) {
200 evt
= dwc
->ev_buffs
[n
];
201 dev_dbg(dwc
->dev
, "Event buf %p dma %08llx length %d\n",
202 evt
->buf
, (unsigned long long) evt
->dma
,
207 dwc3_writel(dwc
->regs
, DWC3_GEVNTADRLO(n
),
208 lower_32_bits(evt
->dma
));
209 dwc3_writel(dwc
->regs
, DWC3_GEVNTADRHI(n
),
210 upper_32_bits(evt
->dma
));
211 dwc3_writel(dwc
->regs
, DWC3_GEVNTSIZ(n
),
212 DWC3_GEVNTSIZ_SIZE(evt
->length
));
213 dwc3_writel(dwc
->regs
, DWC3_GEVNTCOUNT(n
), 0);
219 static void dwc3_event_buffers_cleanup(struct dwc3
*dwc
)
221 struct dwc3_event_buffer
*evt
;
224 for (n
= 0; n
< dwc
->num_event_buffers
; n
++) {
225 evt
= dwc
->ev_buffs
[n
];
229 dwc3_writel(dwc
->regs
, DWC3_GEVNTADRLO(n
), 0);
230 dwc3_writel(dwc
->regs
, DWC3_GEVNTADRHI(n
), 0);
231 dwc3_writel(dwc
->regs
, DWC3_GEVNTSIZ(n
), DWC3_GEVNTSIZ_INTMASK
232 | DWC3_GEVNTSIZ_SIZE(0));
233 dwc3_writel(dwc
->regs
, DWC3_GEVNTCOUNT(n
), 0);
237 static int dwc3_alloc_scratch_buffers(struct dwc3
*dwc
)
239 if (!dwc
->has_hibernation
)
242 if (!dwc
->nr_scratch
)
245 dwc
->scratchbuf
= kmalloc_array(dwc
->nr_scratch
,
246 DWC3_SCRATCHBUF_SIZE
, GFP_KERNEL
);
247 if (!dwc
->scratchbuf
)
253 static int dwc3_setup_scratch_buffers(struct dwc3
*dwc
)
255 dma_addr_t scratch_addr
;
259 if (!dwc
->has_hibernation
)
262 if (!dwc
->nr_scratch
)
265 scratch_addr
= dma_map_single(dwc
->scratchbuf
,
266 dwc
->nr_scratch
* DWC3_SCRATCHBUF_SIZE
,
268 if (dma_mapping_error(dwc
->dev
, scratch_addr
)) {
269 dev_err(dwc
->dev
, "failed to map scratch buffer\n");
274 dwc
->scratch_addr
= scratch_addr
;
276 param
= lower_32_bits(scratch_addr
);
278 ret
= dwc3_send_gadget_generic_command(dwc
,
279 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO
, param
);
283 param
= upper_32_bits(scratch_addr
);
285 ret
= dwc3_send_gadget_generic_command(dwc
,
286 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI
, param
);
293 dma_unmap_single(scratch_addr
, dwc
->nr_scratch
* DWC3_SCRATCHBUF_SIZE
,
300 static void dwc3_free_scratch_buffers(struct dwc3
*dwc
)
302 if (!dwc
->has_hibernation
)
305 if (!dwc
->nr_scratch
)
308 dma_unmap_single(dwc
->scratch_addr
, dwc
->nr_scratch
*
309 DWC3_SCRATCHBUF_SIZE
, DMA_BIDIRECTIONAL
);
310 kfree(dwc
->scratchbuf
);
313 static void dwc3_core_num_eps(struct dwc3
*dwc
)
315 struct dwc3_hwparams
*parms
= &dwc
->hwparams
;
317 dwc
->num_in_eps
= DWC3_NUM_IN_EPS(parms
);
318 dwc
->num_out_eps
= DWC3_NUM_EPS(parms
) - dwc
->num_in_eps
;
320 dev_vdbg(dwc
->dev
, "found %d IN and %d OUT endpoints\n",
321 dwc
->num_in_eps
, dwc
->num_out_eps
);
324 static void dwc3_cache_hwparams(struct dwc3
*dwc
)
326 struct dwc3_hwparams
*parms
= &dwc
->hwparams
;
328 parms
->hwparams0
= dwc3_readl(dwc
->regs
, DWC3_GHWPARAMS0
);
329 parms
->hwparams1
= dwc3_readl(dwc
->regs
, DWC3_GHWPARAMS1
);
330 parms
->hwparams2
= dwc3_readl(dwc
->regs
, DWC3_GHWPARAMS2
);
331 parms
->hwparams3
= dwc3_readl(dwc
->regs
, DWC3_GHWPARAMS3
);
332 parms
->hwparams4
= dwc3_readl(dwc
->regs
, DWC3_GHWPARAMS4
);
333 parms
->hwparams5
= dwc3_readl(dwc
->regs
, DWC3_GHWPARAMS5
);
334 parms
->hwparams6
= dwc3_readl(dwc
->regs
, DWC3_GHWPARAMS6
);
335 parms
->hwparams7
= dwc3_readl(dwc
->regs
, DWC3_GHWPARAMS7
);
336 parms
->hwparams8
= dwc3_readl(dwc
->regs
, DWC3_GHWPARAMS8
);
340 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
341 * @dwc: Pointer to our controller context structure
343 static void dwc3_phy_setup(struct dwc3
*dwc
)
347 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB3PIPECTL(0));
350 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
351 * to '0' during coreConsultant configuration. So default value
352 * will be '0' when the core is reset. Application needs to set it
353 * to '1' after the core initialization is completed.
355 if (dwc
->revision
> DWC3_REVISION_194A
)
356 reg
|= DWC3_GUSB3PIPECTL_SUSPHY
;
358 if (dwc
->u2ss_inp3_quirk
)
359 reg
|= DWC3_GUSB3PIPECTL_U2SSINP3OK
;
361 if (dwc
->req_p1p2p3_quirk
)
362 reg
|= DWC3_GUSB3PIPECTL_REQP1P2P3
;
364 if (dwc
->del_p1p2p3_quirk
)
365 reg
|= DWC3_GUSB3PIPECTL_DEP1P2P3_EN
;
367 if (dwc
->del_phy_power_chg_quirk
)
368 reg
|= DWC3_GUSB3PIPECTL_DEPOCHANGE
;
370 if (dwc
->lfps_filter_quirk
)
371 reg
|= DWC3_GUSB3PIPECTL_LFPSFILT
;
373 if (dwc
->rx_detect_poll_quirk
)
374 reg
|= DWC3_GUSB3PIPECTL_RX_DETOPOLL
;
376 if (dwc
->tx_de_emphasis_quirk
)
377 reg
|= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc
->tx_de_emphasis
);
379 if (dwc
->dis_u3_susphy_quirk
)
380 reg
&= ~DWC3_GUSB3PIPECTL_SUSPHY
;
382 if (dwc
->dis_del_phy_power_chg_quirk
)
383 reg
&= ~DWC3_GUSB3PIPECTL_DEPOCHANGE
;
385 dwc3_writel(dwc
->regs
, DWC3_GUSB3PIPECTL(0), reg
);
389 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB2PHYCFG(0));
392 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
393 * '0' during coreConsultant configuration. So default value will
394 * be '0' when the core is reset. Application needs to set it to
395 * '1' after the core initialization is completed.
397 if (dwc
->revision
> DWC3_REVISION_194A
)
398 reg
|= DWC3_GUSB2PHYCFG_SUSPHY
;
400 if (dwc
->dis_u2_susphy_quirk
)
401 reg
&= ~DWC3_GUSB2PHYCFG_SUSPHY
;
403 if (dwc
->dis_enblslpm_quirk
)
404 reg
&= ~DWC3_GUSB2PHYCFG_ENBLSLPM
;
406 if (dwc
->dis_u2_freeclk_exists_quirk
)
407 reg
&= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS
;
409 dwc3_writel(dwc
->regs
, DWC3_GUSB2PHYCFG(0), reg
);
415 * dwc3_core_init - Low-level initialization of DWC3 Core
416 * @dwc: Pointer to our controller context structure
418 * Returns 0 on success otherwise negative errno.
420 static int dwc3_core_init(struct dwc3
*dwc
)
422 unsigned long timeout
;
423 u32 hwparams4
= dwc
->hwparams
.hwparams4
;
427 reg
= dwc3_readl(dwc
->regs
, DWC3_GSNPSID
);
428 /* This should read as U3 followed by revision number */
429 if ((reg
& DWC3_GSNPSID_MASK
) != 0x55330000) {
430 dev_err(dwc
->dev
, "this is not a DesignWare USB3 DRD Core\n");
436 /* Handle USB2.0-only core configuration */
437 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc
->hwparams
.hwparams3
) ==
438 DWC3_GHWPARAMS3_SSPHY_IFC_DIS
) {
439 if (dwc
->maximum_speed
== USB_SPEED_SUPER
)
440 dwc
->maximum_speed
= USB_SPEED_HIGH
;
443 /* issue device SoftReset too */
445 dwc3_writel(dwc
->regs
, DWC3_DCTL
, DWC3_DCTL_CSFTRST
);
447 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
448 if (!(reg
& DWC3_DCTL_CSFTRST
))
453 dev_err(dwc
->dev
, "Reset Timed Out\n");
460 ret
= dwc3_core_soft_reset(dwc
);
464 reg
= dwc3_readl(dwc
->regs
, DWC3_GCTL
);
465 reg
&= ~DWC3_GCTL_SCALEDOWN_MASK
;
467 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc
->hwparams
.hwparams1
)) {
468 case DWC3_GHWPARAMS1_EN_PWROPT_CLK
:
470 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
471 * issue which would cause xHCI compliance tests to fail.
473 * Because of that we cannot enable clock gating on such
478 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
481 if ((dwc
->dr_mode
== USB_DR_MODE_HOST
||
482 dwc
->dr_mode
== USB_DR_MODE_OTG
) &&
483 (dwc
->revision
>= DWC3_REVISION_210A
&&
484 dwc
->revision
<= DWC3_REVISION_250A
))
485 reg
|= DWC3_GCTL_DSBLCLKGTNG
| DWC3_GCTL_SOFITPSYNC
;
487 reg
&= ~DWC3_GCTL_DSBLCLKGTNG
;
489 case DWC3_GHWPARAMS1_EN_PWROPT_HIB
:
490 /* enable hibernation here */
491 dwc
->nr_scratch
= DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4
);
494 * REVISIT Enabling this bit so that host-mode hibernation
495 * will work. Device-mode hibernation is not yet implemented.
497 reg
|= DWC3_GCTL_GBLHIBERNATIONEN
;
500 dev_dbg(dwc
->dev
, "No power optimization available\n");
503 /* check if current dwc3 is on simulation board */
504 if (dwc
->hwparams
.hwparams6
& DWC3_GHWPARAMS6_EN_FPGA
) {
505 dev_dbg(dwc
->dev
, "it is on FPGA board\n");
509 if(dwc
->disable_scramble_quirk
&& !dwc
->is_fpga
)
511 "disable_scramble cannot be used on non-FPGA builds\n");
513 if (dwc
->disable_scramble_quirk
&& dwc
->is_fpga
)
514 reg
|= DWC3_GCTL_DISSCRAMBLE
;
516 reg
&= ~DWC3_GCTL_DISSCRAMBLE
;
518 if (dwc
->u2exit_lfps_quirk
)
519 reg
|= DWC3_GCTL_U2EXIT_LFPS
;
522 * WORKAROUND: DWC3 revisions <1.90a have a bug
523 * where the device can fail to connect at SuperSpeed
524 * and falls back to high-speed mode which causes
525 * the device to enter a Connect/Disconnect loop
527 if (dwc
->revision
< DWC3_REVISION_190A
)
528 reg
|= DWC3_GCTL_U2RSTECN
;
530 dwc3_core_num_eps(dwc
);
532 dwc3_writel(dwc
->regs
, DWC3_GCTL
, reg
);
534 ret
= dwc3_alloc_scratch_buffers(dwc
);
538 ret
= dwc3_setup_scratch_buffers(dwc
);
545 dwc3_free_scratch_buffers(dwc
);
551 static void dwc3_core_exit(struct dwc3
*dwc
)
553 dwc3_free_scratch_buffers(dwc
);
556 static int dwc3_core_init_mode(struct dwc3
*dwc
)
560 switch (dwc
->dr_mode
) {
561 case USB_DR_MODE_PERIPHERAL
:
562 dwc3_set_mode(dwc
, DWC3_GCTL_PRTCAP_DEVICE
);
563 ret
= dwc3_gadget_init(dwc
);
565 dev_err(dev
, "failed to initialize gadget\n");
569 case USB_DR_MODE_HOST
:
570 dwc3_set_mode(dwc
, DWC3_GCTL_PRTCAP_HOST
);
571 ret
= dwc3_host_init(dwc
);
573 dev_err(dev
, "failed to initialize host\n");
577 case USB_DR_MODE_OTG
:
578 dwc3_set_mode(dwc
, DWC3_GCTL_PRTCAP_OTG
);
579 ret
= dwc3_host_init(dwc
);
581 dev_err(dev
, "failed to initialize host\n");
585 ret
= dwc3_gadget_init(dwc
);
587 dev_err(dev
, "failed to initialize gadget\n");
592 dev_err(dev
, "Unsupported mode of operation %d\n", dwc
->dr_mode
);
599 static void dwc3_gadget_run(struct dwc3
*dwc
)
601 dwc3_writel(dwc
->regs
, DWC3_DCTL
, DWC3_DCTL_RUN_STOP
);
605 static void dwc3_core_exit_mode(struct dwc3
*dwc
)
607 switch (dwc
->dr_mode
) {
608 case USB_DR_MODE_PERIPHERAL
:
609 dwc3_gadget_exit(dwc
);
611 case USB_DR_MODE_HOST
:
614 case USB_DR_MODE_OTG
:
616 dwc3_gadget_exit(dwc
);
624 * switch back to peripheral mode
625 * This enables the phy to enter idle and then, if enabled, suspend.
627 dwc3_set_mode(dwc
, DWC3_GCTL_PRTCAP_DEVICE
);
628 dwc3_gadget_run(dwc
);
631 static void dwc3_uboot_hsphy_mode(struct dwc3_device
*dwc3_dev
,
634 enum usb_phy_interface hsphy_mode
= dwc3_dev
->hsphy_mode
;
637 /* Set dwc3 usb2 phy config */
638 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB2PHYCFG(0));
640 switch (hsphy_mode
) {
641 case USBPHY_INTERFACE_MODE_UTMI
:
642 reg
&= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK
|
643 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK
);
644 reg
|= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT
) |
645 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT
);
647 case USBPHY_INTERFACE_MODE_UTMIW
:
648 reg
&= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK
|
649 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK
);
650 reg
|= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT
) |
651 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT
);
657 dwc3_writel(dwc
->regs
, DWC3_GUSB2PHYCFG(0), reg
);
660 #define DWC3_ALIGN_MASK (16 - 1)
663 * dwc3_uboot_init - dwc3 core uboot initialization code
664 * @dwc3_dev: struct dwc3_device containing initialization data
666 * Entry point for dwc3 driver (equivalent to dwc3_probe in linux
667 * kernel driver). Pointer to dwc3_device should be passed containing
668 * base address and other initialization data. Returns '0' on success and
669 * a negative value on failure.
671 * Generally called from board_usb_init() implemented in board file.
673 int dwc3_uboot_init(struct dwc3_device
*dwc3_dev
)
676 struct device
*dev
= NULL
;
677 u8 lpm_nyet_threshold
;
685 mem
= devm_kzalloc((struct udevice
*)dev
,
686 sizeof(*dwc
) + DWC3_ALIGN_MASK
, GFP_KERNEL
);
690 dwc
= PTR_ALIGN(mem
, DWC3_ALIGN_MASK
+ 1);
693 dwc
->regs
= (void *)(uintptr_t)(dwc3_dev
->base
+
694 DWC3_GLOBALS_REGS_START
);
696 /* default to highest possible threshold */
697 lpm_nyet_threshold
= 0xff;
699 /* default to -3.5dB de-emphasis */
703 * default to assert utmi_sleep_n and use maximum allowed HIRD
704 * threshold value of 0b1100
708 dwc
->maximum_speed
= dwc3_dev
->maximum_speed
;
709 dwc
->has_lpm_erratum
= dwc3_dev
->has_lpm_erratum
;
710 if (dwc3_dev
->lpm_nyet_threshold
)
711 lpm_nyet_threshold
= dwc3_dev
->lpm_nyet_threshold
;
712 dwc
->is_utmi_l1_suspend
= dwc3_dev
->is_utmi_l1_suspend
;
713 if (dwc3_dev
->hird_threshold
)
714 hird_threshold
= dwc3_dev
->hird_threshold
;
716 dwc
->needs_fifo_resize
= dwc3_dev
->tx_fifo_resize
;
717 dwc
->dr_mode
= dwc3_dev
->dr_mode
;
719 dwc
->disable_scramble_quirk
= dwc3_dev
->disable_scramble_quirk
;
720 dwc
->u2exit_lfps_quirk
= dwc3_dev
->u2exit_lfps_quirk
;
721 dwc
->u2ss_inp3_quirk
= dwc3_dev
->u2ss_inp3_quirk
;
722 dwc
->req_p1p2p3_quirk
= dwc3_dev
->req_p1p2p3_quirk
;
723 dwc
->del_p1p2p3_quirk
= dwc3_dev
->del_p1p2p3_quirk
;
724 dwc
->del_phy_power_chg_quirk
= dwc3_dev
->del_phy_power_chg_quirk
;
725 dwc
->lfps_filter_quirk
= dwc3_dev
->lfps_filter_quirk
;
726 dwc
->rx_detect_poll_quirk
= dwc3_dev
->rx_detect_poll_quirk
;
727 dwc
->dis_u3_susphy_quirk
= dwc3_dev
->dis_u3_susphy_quirk
;
728 dwc
->dis_u2_susphy_quirk
= dwc3_dev
->dis_u2_susphy_quirk
;
729 dwc
->dis_del_phy_power_chg_quirk
= dwc3_dev
->dis_del_phy_power_chg_quirk
;
730 dwc
->dis_enblslpm_quirk
= dwc3_dev
->dis_enblslpm_quirk
;
731 dwc
->dis_u2_freeclk_exists_quirk
= dwc3_dev
->dis_u2_freeclk_exists_quirk
;
733 dwc
->tx_de_emphasis_quirk
= dwc3_dev
->tx_de_emphasis_quirk
;
734 if (dwc3_dev
->tx_de_emphasis
)
735 tx_de_emphasis
= dwc3_dev
->tx_de_emphasis
;
737 /* default to superspeed if no maximum_speed passed */
738 if (dwc
->maximum_speed
== USB_SPEED_UNKNOWN
)
739 dwc
->maximum_speed
= USB_SPEED_SUPER
;
741 dwc
->lpm_nyet_threshold
= lpm_nyet_threshold
;
742 dwc
->tx_de_emphasis
= tx_de_emphasis
;
744 dwc
->hird_threshold
= hird_threshold
745 | (dwc
->is_utmi_l1_suspend
<< 4);
747 dwc
->index
= dwc3_dev
->index
;
749 dwc3_cache_hwparams(dwc
);
751 ret
= dwc3_alloc_event_buffers(dwc
, DWC3_EVENT_BUFFERS_SIZE
);
753 dev_err(dwc
->dev
, "failed to allocate event buffers\n");
757 if (!IS_ENABLED(CONFIG_USB_DWC3_GADGET
))
758 dwc
->dr_mode
= USB_DR_MODE_HOST
;
759 else if (!IS_ENABLED(CONFIG_USB_HOST
))
760 dwc
->dr_mode
= USB_DR_MODE_PERIPHERAL
;
762 if (dwc
->dr_mode
== USB_DR_MODE_UNKNOWN
)
763 dwc
->dr_mode
= USB_DR_MODE_OTG
;
765 ret
= dwc3_core_init(dwc
);
767 dev_err(dev
, "failed to initialize core\n");
771 dwc3_uboot_hsphy_mode(dwc3_dev
, dwc
);
773 ret
= dwc3_event_buffers_setup(dwc
);
775 dev_err(dwc
->dev
, "failed to setup event buffers\n");
779 ret
= dwc3_core_init_mode(dwc
);
783 list_add_tail(&dwc
->list
, &dwc3_list
);
788 dwc3_event_buffers_cleanup(dwc
);
794 dwc3_free_event_buffers(dwc
);
800 * dwc3_uboot_exit - dwc3 core uboot cleanup code
801 * @index: index of this controller
803 * Performs cleanup of memory allocated in dwc3_uboot_init and other misc
804 * cleanups (equivalent to dwc3_remove in linux). index of _this_ controller
805 * should be passed and should match with the index passed in
806 * dwc3_device during init.
808 * Generally called from board file.
810 void dwc3_uboot_exit(int index
)
814 list_for_each_entry(dwc
, &dwc3_list
, list
) {
815 if (dwc
->index
!= index
)
818 dwc3_core_exit_mode(dwc
);
819 dwc3_event_buffers_cleanup(dwc
);
820 dwc3_free_event_buffers(dwc
);
822 list_del(&dwc
->list
);
829 * dwc3_uboot_handle_interrupt - handle dwc3 core interrupt
830 * @index: index of this controller
832 * Invokes dwc3 gadget interrupts.
834 * Generally called from board file.
836 void dwc3_uboot_handle_interrupt(int index
)
838 struct dwc3
*dwc
= NULL
;
840 list_for_each_entry(dwc
, &dwc3_list
, list
) {
841 if (dwc
->index
!= index
)
844 dwc3_gadget_uboot_handle_interrupt(dwc
);
849 MODULE_ALIAS("platform:dwc3");
850 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
851 MODULE_LICENSE("GPL v2");
852 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
854 #if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB)
855 int dwc3_setup_phy(struct udevice
*dev
, struct phy_bulk
*phys
)
859 ret
= generic_phy_get_bulk(dev
, phys
);
863 ret
= generic_phy_init_bulk(phys
);
867 ret
= generic_phy_power_on_bulk(phys
);
869 generic_phy_exit_bulk(phys
);
874 int dwc3_shutdown_phy(struct udevice
*dev
, struct phy_bulk
*phys
)
878 ret
= generic_phy_power_off_bulk(phys
);
879 ret
|= generic_phy_exit_bulk(phys
);
884 #if CONFIG_IS_ENABLED(DM_USB)
885 void dwc3_of_parse(struct dwc3
*dwc
)
888 struct udevice
*dev
= dwc
->dev
;
889 u8 lpm_nyet_threshold
;
893 /* default to highest possible threshold */
894 lpm_nyet_threshold
= 0xff;
896 /* default to -3.5dB de-emphasis */
900 * default to assert utmi_sleep_n and use maximum allowed HIRD
901 * threshold value of 0b1100
905 dwc
->has_lpm_erratum
= dev_read_bool(dev
,
906 "snps,has-lpm-erratum");
907 tmp
= dev_read_u8_array_ptr(dev
, "snps,lpm-nyet-threshold", 1);
909 lpm_nyet_threshold
= *tmp
;
911 dwc
->is_utmi_l1_suspend
= dev_read_bool(dev
,
912 "snps,is-utmi-l1-suspend");
913 tmp
= dev_read_u8_array_ptr(dev
, "snps,hird-threshold", 1);
915 hird_threshold
= *tmp
;
917 dwc
->disable_scramble_quirk
= dev_read_bool(dev
,
918 "snps,disable_scramble_quirk");
919 dwc
->u2exit_lfps_quirk
= dev_read_bool(dev
,
920 "snps,u2exit_lfps_quirk");
921 dwc
->u2ss_inp3_quirk
= dev_read_bool(dev
,
922 "snps,u2ss_inp3_quirk");
923 dwc
->req_p1p2p3_quirk
= dev_read_bool(dev
,
924 "snps,req_p1p2p3_quirk");
925 dwc
->del_p1p2p3_quirk
= dev_read_bool(dev
,
926 "snps,del_p1p2p3_quirk");
927 dwc
->del_phy_power_chg_quirk
= dev_read_bool(dev
,
928 "snps,del_phy_power_chg_quirk");
929 dwc
->lfps_filter_quirk
= dev_read_bool(dev
,
930 "snps,lfps_filter_quirk");
931 dwc
->rx_detect_poll_quirk
= dev_read_bool(dev
,
932 "snps,rx_detect_poll_quirk");
933 dwc
->dis_u3_susphy_quirk
= dev_read_bool(dev
,
934 "snps,dis_u3_susphy_quirk");
935 dwc
->dis_u2_susphy_quirk
= dev_read_bool(dev
,
936 "snps,dis_u2_susphy_quirk");
937 dwc
->dis_del_phy_power_chg_quirk
= dev_read_bool(dev
,
938 "snps,dis-del-phy-power-chg-quirk");
939 dwc
->dis_enblslpm_quirk
= dev_read_bool(dev
,
940 "snps,dis_enblslpm_quirk");
941 dwc
->dis_u2_freeclk_exists_quirk
= dev_read_bool(dev
,
942 "snps,dis-u2-freeclk-exists-quirk");
943 dwc
->tx_de_emphasis_quirk
= dev_read_bool(dev
,
944 "snps,tx_de_emphasis_quirk");
945 tmp
= dev_read_u8_array_ptr(dev
, "snps,tx_de_emphasis", 1);
947 tx_de_emphasis
= *tmp
;
949 dwc
->lpm_nyet_threshold
= lpm_nyet_threshold
;
950 dwc
->tx_de_emphasis
= tx_de_emphasis
;
952 dwc
->hird_threshold
= hird_threshold
953 | (dwc
->is_utmi_l1_suspend
<< 4);
956 int dwc3_init(struct dwc3
*dwc
)
960 dwc3_cache_hwparams(dwc
);
962 ret
= dwc3_alloc_event_buffers(dwc
, DWC3_EVENT_BUFFERS_SIZE
);
964 dev_err(dwc
->dev
, "failed to allocate event buffers\n");
968 ret
= dwc3_core_init(dwc
);
970 dev_err(dev
, "failed to initialize core\n");
974 ret
= dwc3_event_buffers_setup(dwc
);
976 dev_err(dwc
->dev
, "failed to setup event buffers\n");
980 ret
= dwc3_core_init_mode(dwc
);
987 dwc3_event_buffers_cleanup(dwc
);
993 dwc3_free_event_buffers(dwc
);
998 void dwc3_remove(struct dwc3
*dwc
)
1000 dwc3_core_exit_mode(dwc
);
1001 dwc3_event_buffers_cleanup(dwc
);
1002 dwc3_free_event_buffers(dwc
);
1003 dwc3_core_exit(dwc
);