1 /* SPDX-License-Identifier: GPL-2.0 */
3 * core.h - DesignWare USB3 DRD Core Header
5 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
10 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.h) and ported
13 * commit 460d098cb6 : usb: dwc3: make HIRD threshold configurable
17 #ifndef __DRIVERS_USB_DWC3_CORE_H
18 #define __DRIVERS_USB_DWC3_CORE_H
20 #include <linux/bitops.h>
21 #include <linux/ioport.h>
23 #include <linux/usb/ch9.h>
24 #include <linux/usb/otg.h>
26 #define DWC3_MSG_MAX 500
28 /* Global constants */
29 #define DWC3_EP0_BOUNCE_SIZE 512
30 #define DWC3_ENDPOINTS_NUM 32
31 #define DWC3_XHCI_RESOURCES_NUM 2
33 #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */
34 #define DWC3_EVENT_SIZE 4 /* bytes */
35 #define DWC3_EVENT_MAX_NUM 64 /* 2 events/endpoint */
36 #define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM)
37 #define DWC3_EVENT_TYPE_MASK 0xfe
39 #define DWC3_EVENT_TYPE_DEV 0
40 #define DWC3_EVENT_TYPE_CARKIT 3
41 #define DWC3_EVENT_TYPE_I2C 4
43 #define DWC3_DEVICE_EVENT_DISCONNECT 0
44 #define DWC3_DEVICE_EVENT_RESET 1
45 #define DWC3_DEVICE_EVENT_CONNECT_DONE 2
46 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
47 #define DWC3_DEVICE_EVENT_WAKEUP 4
48 #define DWC3_DEVICE_EVENT_HIBER_REQ 5
49 #define DWC3_DEVICE_EVENT_EOPF 6
50 #define DWC3_DEVICE_EVENT_SOF 7
51 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
52 #define DWC3_DEVICE_EVENT_CMD_CMPL 10
53 #define DWC3_DEVICE_EVENT_OVERFLOW 11
55 #define DWC3_GEVNTCOUNT_MASK 0xfffc
56 #define DWC3_GSNPSID_MASK 0xffff0000
57 #define DWC3_GSNPSREV_MASK 0xffff
59 /* DWC3 registers memory space boundries */
60 #define DWC3_XHCI_REGS_START 0x0
61 #define DWC3_XHCI_REGS_END 0x7fff
62 #define DWC3_GLOBALS_REGS_START 0xc100
63 #define DWC3_GLOBALS_REGS_END 0xc6ff
64 #define DWC3_DEVICE_REGS_START 0xc700
65 #define DWC3_DEVICE_REGS_END 0xcbff
66 #define DWC3_OTG_REGS_START 0xcc00
67 #define DWC3_OTG_REGS_END 0xccff
69 /* Global Registers */
70 #define DWC3_GSBUSCFG0 0xc100
71 #define DWC3_GSBUSCFG1 0xc104
72 #define DWC3_GTXTHRCFG 0xc108
73 #define DWC3_GRXTHRCFG 0xc10c
74 #define DWC3_GCTL 0xc110
75 #define DWC3_GEVTEN 0xc114
76 #define DWC3_GSTS 0xc118
77 #define DWC3_GUCTL1 0xc11c
78 #define DWC3_GSNPSID 0xc120
79 #define DWC3_GGPIO 0xc124
80 #define DWC3_GUID 0xc128
81 #define DWC3_GUCTL 0xc12c
82 #define DWC3_GBUSERRADDR0 0xc130
83 #define DWC3_GBUSERRADDR1 0xc134
84 #define DWC3_GPRTBIMAP0 0xc138
85 #define DWC3_GPRTBIMAP1 0xc13c
86 #define DWC3_GHWPARAMS0 0xc140
87 #define DWC3_GHWPARAMS1 0xc144
88 #define DWC3_GHWPARAMS2 0xc148
89 #define DWC3_GHWPARAMS3 0xc14c
90 #define DWC3_GHWPARAMS4 0xc150
91 #define DWC3_GHWPARAMS5 0xc154
92 #define DWC3_GHWPARAMS6 0xc158
93 #define DWC3_GHWPARAMS7 0xc15c
94 #define DWC3_GDBGFIFOSPACE 0xc160
95 #define DWC3_GDBGLTSSM 0xc164
96 #define DWC3_GPRTBIMAP_HS0 0xc180
97 #define DWC3_GPRTBIMAP_HS1 0xc184
98 #define DWC3_GPRTBIMAP_FS0 0xc188
99 #define DWC3_GPRTBIMAP_FS1 0xc18c
101 #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04))
102 #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04))
104 #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04))
106 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04))
108 #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04))
109 #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04))
111 #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10))
112 #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10))
113 #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10))
114 #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10))
116 #define DWC3_GHWPARAMS8 0xc600
118 /* Device Registers */
119 #define DWC3_DCFG 0xc700
120 #define DWC3_DCTL 0xc704
121 #define DWC3_DEVTEN 0xc708
122 #define DWC3_DSTS 0xc70c
123 #define DWC3_DGCMDPAR 0xc710
124 #define DWC3_DGCMD 0xc714
125 #define DWC3_DALEPENA 0xc720
126 #define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10))
127 #define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10))
128 #define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10))
129 #define DWC3_DEPCMD(n) (0xc80c + (n * 0x10))
132 #define DWC3_OCFG 0xcc00
133 #define DWC3_OCTL 0xcc04
134 #define DWC3_OEVT 0xcc08
135 #define DWC3_OEVTEN 0xcc0C
136 #define DWC3_OSTS 0xcc10
140 /* Global Configuration Register */
141 #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
142 #define DWC3_GCTL_U2RSTECN (1 << 16)
143 #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
144 #define DWC3_GCTL_CLK_BUS (0)
145 #define DWC3_GCTL_CLK_PIPE (1)
146 #define DWC3_GCTL_CLK_PIPEHALF (2)
147 #define DWC3_GCTL_CLK_MASK (3)
149 #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
150 #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
151 #define DWC3_GCTL_PRTCAP_HOST 1
152 #define DWC3_GCTL_PRTCAP_DEVICE 2
153 #define DWC3_GCTL_PRTCAP_OTG 3
155 #define DWC3_GCTL_CORESOFTRESET (1 << 11)
156 #define DWC3_GCTL_SOFITPSYNC (1 << 10)
157 #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
158 #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
159 #define DWC3_GCTL_DISSCRAMBLE (1 << 3)
160 #define DWC3_GCTL_U2EXIT_LFPS (1 << 2)
161 #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1)
162 #define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
164 /* Global User Control 1 Register */
165 #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28)
166 #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24)
168 /* Global USB2 PHY Configuration Register */
169 #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
170 #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS (1 << 30)
171 #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
172 #define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8)
173 #define DWC3_GUSB2PHYCFG_PHYIF(n) ((n) << 3)
174 #define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1)
175 #define DWC3_GUSB2PHYCFG_USBTRDTIM(n) ((n) << 10)
176 #define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)
177 #define USBTRDTIM_UTMI_8_BIT 9
178 #define USBTRDTIM_UTMI_16_BIT 5
179 #define UTMI_PHYIF_16_BIT 1
180 #define UTMI_PHYIF_8_BIT 0
182 /* Global USB3 PIPE Control Register */
183 #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
184 #define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29)
185 #define DWC3_GUSB3PIPECTL_REQP1P2P3 (1 << 24)
186 #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19)
187 #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7)
188 #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1)
189 #define DWC3_GUSB3PIPECTL_DEPOCHANGE (1 << 18)
190 #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
191 #define DWC3_GUSB3PIPECTL_LFPSFILT (1 << 9)
192 #define DWC3_GUSB3PIPECTL_RX_DETOPOLL (1 << 8)
193 #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3)
194 #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1)
196 /* Global TX Fifo Size Register */
197 #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
198 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
200 /* Global Event Size Registers */
201 #define DWC3_GEVNTSIZ_INTMASK (1 << 31)
202 #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff)
204 /* Global HWPARAMS1 Register */
205 #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
206 #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
207 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
208 #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2
209 #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24)
210 #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3)
212 /* Global HWPARAMS3 Register */
213 #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3)
214 #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0
215 #define DWC3_GHWPARAMS3_SSPHY_IFC_ENA 1
216 #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2)
217 #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0
218 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1
219 #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2
220 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3
221 #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4)
222 #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0
223 #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1
225 /* Global HWPARAMS4 Register */
226 #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
227 #define DWC3_MAX_HIBER_SCRATCHBUFS 15
229 /* Global HWPARAMS6 Register */
230 #define DWC3_GHWPARAMS6_EN_FPGA (1 << 7)
232 /* Device Configuration Register */
233 #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
234 #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
236 #define DWC3_DCFG_SPEED_MASK (7 << 0)
237 #define DWC3_DCFG_SUPERSPEED (4 << 0)
238 #define DWC3_DCFG_HIGHSPEED (0 << 0)
239 #define DWC3_DCFG_FULLSPEED2 (1 << 0)
240 #define DWC3_DCFG_LOWSPEED (2 << 0)
241 #define DWC3_DCFG_FULLSPEED1 (3 << 0)
243 #define DWC3_DCFG_LPM_CAP (1 << 22)
245 /* Device Control Register */
246 #define DWC3_DCTL_RUN_STOP (1 << 31)
247 #define DWC3_DCTL_CSFTRST (1 << 30)
248 #define DWC3_DCTL_LSFTRST (1 << 29)
250 #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
251 #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24)
253 #define DWC3_DCTL_APPL1RES (1 << 23)
255 /* These apply for core versions 1.87a and earlier */
256 #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
257 #define DWC3_DCTL_TRGTULST(n) ((n) << 17)
258 #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))
259 #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))
260 #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))
261 #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))
262 #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
264 /* These apply for core versions 1.94a and later */
265 #define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf)
266 #define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20)
268 #define DWC3_DCTL_KEEP_CONNECT (1 << 19)
269 #define DWC3_DCTL_L1_HIBER_EN (1 << 18)
270 #define DWC3_DCTL_CRS (1 << 17)
271 #define DWC3_DCTL_CSS (1 << 16)
273 #define DWC3_DCTL_INITU2ENA (1 << 12)
274 #define DWC3_DCTL_ACCEPTU2ENA (1 << 11)
275 #define DWC3_DCTL_INITU1ENA (1 << 10)
276 #define DWC3_DCTL_ACCEPTU1ENA (1 << 9)
277 #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
279 #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
280 #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
282 #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
283 #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))
284 #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))
285 #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))
286 #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))
287 #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
288 #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
290 /* Device Event Enable Register */
291 #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12)
292 #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11)
293 #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10)
294 #define DWC3_DEVTEN_ERRTICERREN (1 << 9)
295 #define DWC3_DEVTEN_SOFEN (1 << 7)
296 #define DWC3_DEVTEN_EOPFEN (1 << 6)
297 #define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5)
298 #define DWC3_DEVTEN_WKUPEVTEN (1 << 4)
299 #define DWC3_DEVTEN_ULSTCNGEN (1 << 3)
300 #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2)
301 #define DWC3_DEVTEN_USBRSTEN (1 << 1)
302 #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0)
304 /* Device Status Register */
305 #define DWC3_DSTS_DCNRD (1 << 29)
307 /* This applies for core versions 1.87a and earlier */
308 #define DWC3_DSTS_PWRUPREQ (1 << 24)
310 /* These apply for core versions 1.94a and later */
311 #define DWC3_DSTS_RSS (1 << 25)
312 #define DWC3_DSTS_SSS (1 << 24)
314 #define DWC3_DSTS_COREIDLE (1 << 23)
315 #define DWC3_DSTS_DEVCTRLHLT (1 << 22)
317 #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
318 #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
320 #define DWC3_DSTS_RXFIFOEMPTY (1 << 17)
322 #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
323 #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
325 #define DWC3_DSTS_CONNECTSPD (7 << 0)
327 #define DWC3_DSTS_SUPERSPEED (4 << 0)
328 #define DWC3_DSTS_HIGHSPEED (0 << 0)
329 #define DWC3_DSTS_FULLSPEED2 (1 << 0)
330 #define DWC3_DSTS_LOWSPEED (2 << 0)
331 #define DWC3_DSTS_FULLSPEED1 (3 << 0)
333 /* Device Generic Command Register */
334 #define DWC3_DGCMD_SET_LMP 0x01
335 #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
336 #define DWC3_DGCMD_XMIT_FUNCTION 0x03
338 /* These apply for core versions 1.94a and later */
339 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
340 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
342 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
343 #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
344 #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
345 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
347 #define DWC3_DGCMD_STATUS(n) (((n) >> 15) & 1)
348 #define DWC3_DGCMD_CMDACT (1 << 10)
349 #define DWC3_DGCMD_CMDIOC (1 << 8)
351 /* Device Generic Command Parameter Register */
352 #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0)
353 #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
354 #define DWC3_DGCMDPAR_RX_FIFO (0 << 5)
355 #define DWC3_DGCMDPAR_TX_FIFO (1 << 5)
356 #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)
357 #define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0)
359 /* Device Endpoint Command Register */
360 #define DWC3_DEPCMD_PARAM_SHIFT 16
361 #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT)
362 #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
363 #define DWC3_DEPCMD_STATUS(x) (((x) >> 15) & 1)
364 #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11)
365 #define DWC3_DEPCMD_CMDACT (1 << 10)
366 #define DWC3_DEPCMD_CMDIOC (1 << 8)
368 #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
369 #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
370 #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
371 #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
372 #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
373 #define DWC3_DEPCMD_SETSTALL (0x04 << 0)
374 /* This applies for core versions 1.90a and earlier */
375 #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
376 /* This applies for core versions 1.94a and later */
377 #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0)
378 #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
379 #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
381 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
382 #define DWC3_DALEPENA_EP(n) (1 << n)
384 #define DWC3_DEPCMD_TYPE_CONTROL 0
385 #define DWC3_DEPCMD_TYPE_ISOC 1
386 #define DWC3_DEPCMD_TYPE_BULK 2
387 #define DWC3_DEPCMD_TYPE_INTR 3
394 * struct dwc3_event_buffer - Software event buffer representation
396 * @length: size of this buffer
397 * @lpos: event offset
398 * @count: cache of last read event count register
399 * @flags: flags related to this event buffer
401 * @dwc: pointer to DWC controller
403 struct dwc3_event_buffer
{
410 #define DWC3_EVENT_PENDING (1UL << 0)
417 #define DWC3_EP_FLAG_STALLED (1 << 0)
418 #define DWC3_EP_FLAG_WEDGED (1 << 1)
420 #define DWC3_EP_DIRECTION_TX true
421 #define DWC3_EP_DIRECTION_RX false
423 #define DWC3_TRB_NUM 32
424 #define DWC3_TRB_MASK (DWC3_TRB_NUM - 1)
427 * struct dwc3_ep - device side endpoint representation
428 * @endpoint: usb endpoint
429 * @request_list: list of requests for this endpoint
430 * @req_queued: list of requests on this ep which have TRBs setup
431 * @trb_pool: array of transaction buffers
432 * @trb_pool_dma: dma address of @trb_pool
433 * @free_slot: next slot which is going to be used
434 * @busy_slot: first slot which is owned by HW
435 * @desc: usb_endpoint_descriptor pointer
436 * @dwc: pointer to DWC controller
437 * @saved_state: ep state saved during hibernation
438 * @flags: endpoint flags (wedged, stalled, ...)
439 * @current_trb: index of current used trb
440 * @number: endpoint number (1 - 15)
441 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
442 * @resource_index: Resource transfer index
443 * @interval: the interval on which the ISOC transfer is started
444 * @name: a human readable name e.g. ep1out-bulk
445 * @direction: true for TX, false for RX
446 * @stream_capable: true when streams are enabled
449 struct usb_ep endpoint
;
450 struct list_head request_list
;
451 struct list_head req_queued
;
453 struct dwc3_trb
*trb_pool
;
454 dma_addr_t trb_pool_dma
;
457 const struct usb_ss_ep_comp_descriptor
*comp_desc
;
462 #define DWC3_EP_ENABLED (1 << 0)
463 #define DWC3_EP_STALL (1 << 1)
464 #define DWC3_EP_WEDGE (1 << 2)
465 #define DWC3_EP_BUSY (1 << 4)
466 #define DWC3_EP_PENDING_REQUEST (1 << 5)
467 #define DWC3_EP_MISSED_ISOC (1 << 6)
469 /* This last one is specific to EP0 */
470 #define DWC3_EP0_DIR_IN (1 << 31)
472 unsigned current_trb
;
481 unsigned direction
:1;
482 unsigned stream_capable
:1;
486 DWC3_PHY_UNKNOWN
= 0,
492 DWC3_EP0_UNKNOWN
= 0,
495 DWC3_EP0_NRDY_STATUS
,
498 enum dwc3_ep0_state
{
505 enum dwc3_link_state
{
507 DWC3_LINK_STATE_U0
= 0x00, /* in HS, means ON */
508 DWC3_LINK_STATE_U1
= 0x01,
509 DWC3_LINK_STATE_U2
= 0x02, /* in HS, means SLEEP */
510 DWC3_LINK_STATE_U3
= 0x03, /* in HS, means SUSPEND */
511 DWC3_LINK_STATE_SS_DIS
= 0x04,
512 DWC3_LINK_STATE_RX_DET
= 0x05, /* in HS, means Early Suspend */
513 DWC3_LINK_STATE_SS_INACT
= 0x06,
514 DWC3_LINK_STATE_POLL
= 0x07,
515 DWC3_LINK_STATE_RECOV
= 0x08,
516 DWC3_LINK_STATE_HRESET
= 0x09,
517 DWC3_LINK_STATE_CMPLY
= 0x0a,
518 DWC3_LINK_STATE_LPBK
= 0x0b,
519 DWC3_LINK_STATE_RESET
= 0x0e,
520 DWC3_LINK_STATE_RESUME
= 0x0f,
521 DWC3_LINK_STATE_MASK
= 0x0f,
524 /* TRB Length, PCM and Status */
525 #define DWC3_TRB_SIZE_MASK (0x00ffffff)
526 #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
527 #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
528 #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
530 #define DWC3_TRBSTS_OK 0
531 #define DWC3_TRBSTS_MISSED_ISOC 1
532 #define DWC3_TRBSTS_SETUP_PENDING 2
533 #define DWC3_TRB_STS_XFER_IN_PROG 4
536 #define DWC3_TRB_CTRL_HWO (1 << 0)
537 #define DWC3_TRB_CTRL_LST (1 << 1)
538 #define DWC3_TRB_CTRL_CHN (1 << 2)
539 #define DWC3_TRB_CTRL_CSP (1 << 3)
540 #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
541 #define DWC3_TRB_CTRL_ISP_IMI (1 << 10)
542 #define DWC3_TRB_CTRL_IOC (1 << 11)
543 #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
545 #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1)
546 #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2)
547 #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3)
548 #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4)
549 #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5)
550 #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6)
551 #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7)
552 #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8)
555 * struct dwc3_trb - transfer request block (hw format)
569 * dwc3_hwparams - copy of HWPARAMS registers
570 * @hwparams0 - GHWPARAMS0
571 * @hwparams1 - GHWPARAMS1
572 * @hwparams2 - GHWPARAMS2
573 * @hwparams3 - GHWPARAMS3
574 * @hwparams4 - GHWPARAMS4
575 * @hwparams5 - GHWPARAMS5
576 * @hwparams6 - GHWPARAMS6
577 * @hwparams7 - GHWPARAMS7
578 * @hwparams8 - GHWPARAMS8
580 struct dwc3_hwparams
{
593 #define DWC3_MODE(n) ((n) & 0x7)
595 #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8)
598 #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
601 #define DWC3_NUM_IN_EPS_MASK (0x1f << 18)
602 #define DWC3_NUM_EPS_MASK (0x3f << 12)
603 #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \
604 (DWC3_NUM_EPS_MASK)) >> 12)
605 #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \
606 (DWC3_NUM_IN_EPS_MASK)) >> 18)
609 #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)
611 struct dwc3_request
{
612 struct usb_request request
;
613 struct list_head list
;
618 struct dwc3_trb
*trb
;
621 unsigned direction
:1;
627 * struct dwc3_scratchpad_array - hibernation scratchpad array
628 * (format defined by hw)
630 struct dwc3_scratchpad_array
{
631 __le64 dma_adr
[DWC3_MAX_HIBER_SCRATCHBUFS
];
635 * struct dwc3 - representation of our controller
636 * @ctrl_req: usb control request which is used for ep0
637 * @ep0_trb: trb which is used for the ctrl_req
638 * @ep0_bounce: bounce buffer for ep0
639 * @setup_buf: used while precessing STD USB requests
640 * @ctrl_req_addr: dma address of ctrl_req
641 * @ep0_trb: dma address of ep0_trb
642 * @ep0_usb_req: dummy req used while handling STD USB requests
643 * @ep0_bounce_addr: dma address of ep0_bounce
644 * @scratch_addr: dma address of scratchbuf
645 * @lock: for synchronizing
646 * @dev: pointer to our struct device
647 * @xhci: pointer to our xHCI child
648 * @event_buffer_list: a list of event buffers
649 * @gadget: device side representation of the peripheral controller
650 * @gadget_driver: pointer to the gadget driver
651 * @regs: base address for our registers
652 * @regs_size: address space size
653 * @nr_scratch: number of scratch buffers
654 * @num_event_buffers: calculated number of event buffers
655 * @u1u2: only used on revisions <1.83a for workaround
656 * @maximum_speed: maximum speed requested (mainly for testing purposes)
657 * @revision: revision register contents
658 * @dr_mode: requested mode of operation
659 * @dcfg: saved contents of DCFG register
660 * @gctl: saved contents of GCTL register
661 * @isoch_delay: wValue from Set Isochronous Delay request;
662 * @u2sel: parameter from Set SEL request.
663 * @u2pel: parameter from Set SEL request.
664 * @u1sel: parameter from Set SEL request.
665 * @u1pel: parameter from Set SEL request.
666 * @num_out_eps: number of out endpoints
667 * @num_in_eps: number of in endpoints
668 * @ep0_next_event: hold the next expected event
669 * @ep0state: state of endpoint zero
670 * @link_state: link state
671 * @speed: device speed (super, high, full, low)
672 * @mem: points to start of memory which is used for this struct.
673 * @hwparams: copy of hwparams registers
674 * @root: debugfs root folder pointer
675 * @regset: debugfs pointer to regdump file
676 * @test_mode: true when we're entering a USB test mode
677 * @test_mode_nr: test feature selector
678 * @lpm_nyet_threshold: LPM NYET response threshold
679 * @hird_threshold: HIRD threshold
680 * @delayed_status: true when gadget driver asks for delayed status
681 * @ep0_bounced: true when we used bounce buffer
682 * @ep0_expect_in: true when we expect a DATA IN transfer
683 * @has_hibernation: true when dwc3 was configured with Hibernation
684 * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that
685 * there's now way for software to detect this in runtime.
686 * @is_utmi_l1_suspend: the core asserts output signal
688 * 1 - utmi_l1_suspend_n
689 * @is_selfpowered: true when we are selfpowered
690 * @is_fpga: true when we are using the FPGA board
691 * @needs_fifo_resize: not all users might want fifo resizing, flag it
692 * @pullups_connected: true when Run/Stop bit is set
693 * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes.
694 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
695 * @start_config_issued: true when StartConfig command has been issued
696 * @three_stage_setup: set if we perform a three phase setup
697 * @disable_scramble_quirk: set if we enable the disable scramble quirk
698 * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
699 * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
700 * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk
701 * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk
702 * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk
703 * @lfps_filter_quirk: set if we enable LFPS filter quirk
704 * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk
705 * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy
706 * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy
707 * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
708 * @tx_de_emphasis: Tx de-emphasis value
709 * 0 - -6dB de-emphasis
710 * 1 - -3.5dB de-emphasis
713 * @index: index of _this_ controller
714 * @list: to maintain the list of dwc3 controllers
717 struct usb_ctrlrequest
*ctrl_req
;
718 struct dwc3_trb
*ep0_trb
;
722 dma_addr_t ctrl_req_addr
;
723 dma_addr_t ep0_trb_addr
;
724 dma_addr_t ep0_bounce_addr
;
725 dma_addr_t scratch_addr
;
726 struct dwc3_request ep0_usb_req
;
731 #if defined(__UBOOT__) && CONFIG_IS_ENABLED(DM_USB)
737 struct platform_device
*xhci
;
738 struct resource xhci_resources
[DWC3_XHCI_RESOURCES_NUM
];
740 struct dwc3_event_buffer
**ev_buffs
;
741 struct dwc3_ep
*eps
[DWC3_ENDPOINTS_NUM
];
743 struct usb_gadget gadget
;
744 struct usb_gadget_driver
*gadget_driver
;
749 enum usb_dr_mode dr_mode
;
751 /* used for suspend/resume */
756 u32 num_event_buffers
;
761 #define DWC3_REVISION_173A 0x5533173a
762 #define DWC3_REVISION_175A 0x5533175a
763 #define DWC3_REVISION_180A 0x5533180a
764 #define DWC3_REVISION_183A 0x5533183a
765 #define DWC3_REVISION_185A 0x5533185a
766 #define DWC3_REVISION_187A 0x5533187a
767 #define DWC3_REVISION_188A 0x5533188a
768 #define DWC3_REVISION_190A 0x5533190a
769 #define DWC3_REVISION_194A 0x5533194a
770 #define DWC3_REVISION_200A 0x5533200a
771 #define DWC3_REVISION_202A 0x5533202a
772 #define DWC3_REVISION_210A 0x5533210a
773 #define DWC3_REVISION_220A 0x5533220a
774 #define DWC3_REVISION_230A 0x5533230a
775 #define DWC3_REVISION_240A 0x5533240a
776 #define DWC3_REVISION_250A 0x5533250a
777 #define DWC3_REVISION_260A 0x5533260a
778 #define DWC3_REVISION_270A 0x5533270a
779 #define DWC3_REVISION_280A 0x5533280a
780 #define DWC3_REVISION_290A 0x5533290a
782 enum dwc3_ep0_next ep0_next_event
;
783 enum dwc3_ep0_state ep0state
;
784 enum dwc3_link_state link_state
;
799 struct dwc3_hwparams hwparams
;
801 struct debugfs_regset32
*regset
;
805 u8 lpm_nyet_threshold
;
808 unsigned delayed_status
:1;
809 unsigned ep0_bounced
:1;
810 unsigned ep0_expect_in
:1;
811 unsigned has_hibernation
:1;
812 unsigned has_lpm_erratum
:1;
813 unsigned is_utmi_l1_suspend
:1;
814 unsigned is_selfpowered
:1;
816 unsigned needs_fifo_resize
:1;
817 unsigned pullups_connected
:1;
818 unsigned resize_fifos
:1;
819 unsigned setup_packet_pending
:1;
820 unsigned start_config_issued
:1;
821 unsigned three_stage_setup
:1;
823 unsigned disable_scramble_quirk
:1;
824 unsigned u2exit_lfps_quirk
:1;
825 unsigned u2ss_inp3_quirk
:1;
826 unsigned req_p1p2p3_quirk
:1;
827 unsigned del_p1p2p3_quirk
:1;
828 unsigned del_phy_power_chg_quirk
:1;
829 unsigned lfps_filter_quirk
:1;
830 unsigned rx_detect_poll_quirk
:1;
831 unsigned dis_u3_susphy_quirk
:1;
832 unsigned dis_u2_susphy_quirk
:1;
833 unsigned dis_del_phy_power_chg_quirk
:1;
834 unsigned dis_tx_ipgap_linecheck_quirk
:1;
835 unsigned dis_enblslpm_quirk
:1;
836 unsigned dis_u2_freeclk_exists_quirk
:1;
838 unsigned tx_de_emphasis_quirk
:1;
839 unsigned tx_de_emphasis
:2;
841 struct list_head list
;
844 /* -------------------------------------------------------------------------- */
846 /* -------------------------------------------------------------------------- */
848 struct dwc3_event_type
{
854 #define DWC3_DEPEVT_XFERCOMPLETE 0x01
855 #define DWC3_DEPEVT_XFERINPROGRESS 0x02
856 #define DWC3_DEPEVT_XFERNOTREADY 0x03
857 #define DWC3_DEPEVT_RXTXFIFOEVT 0x04
858 #define DWC3_DEPEVT_STREAMEVT 0x06
859 #define DWC3_DEPEVT_EPCMDCMPLT 0x07
862 * dwc3_ep_event_string - returns event name
863 * @event: then event code
865 static inline const char *dwc3_ep_event_string(u8 event
)
868 case DWC3_DEPEVT_XFERCOMPLETE
:
869 return "Transfer Complete";
870 case DWC3_DEPEVT_XFERINPROGRESS
:
871 return "Transfer In-Progress";
872 case DWC3_DEPEVT_XFERNOTREADY
:
873 return "Transfer Not Ready";
874 case DWC3_DEPEVT_RXTXFIFOEVT
:
876 case DWC3_DEPEVT_STREAMEVT
:
878 case DWC3_DEPEVT_EPCMDCMPLT
:
879 return "Endpoint Command Complete";
886 * struct dwc3_event_depvt - Device Endpoint Events
887 * @one_bit: indicates this is an endpoint event (not used)
888 * @endpoint_number: number of the endpoint
889 * @endpoint_event: The event we have:
891 * 0x01 - XferComplete
892 * 0x02 - XferInProgress
893 * 0x03 - XferNotReady
894 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
898 * @reserved11_10: Reserved, don't use.
899 * @status: Indicates the status of the event. Refer to databook for
901 * @parameters: Parameters of the current event. Refer to databook for
904 struct dwc3_event_depevt
{
906 u32 endpoint_number
:5;
907 u32 endpoint_event
:4;
911 /* Within XferNotReady */
912 #define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3)
914 /* Within XferComplete */
915 #define DEPEVT_STATUS_BUSERR (1 << 0)
916 #define DEPEVT_STATUS_SHORT (1 << 1)
917 #define DEPEVT_STATUS_IOC (1 << 2)
918 #define DEPEVT_STATUS_LST (1 << 3)
920 /* Stream event only */
921 #define DEPEVT_STREAMEVT_FOUND 1
922 #define DEPEVT_STREAMEVT_NOTFOUND 2
924 /* Control-only Status */
925 #define DEPEVT_STATUS_CONTROL_DATA 1
926 #define DEPEVT_STATUS_CONTROL_STATUS 2
932 * struct dwc3_event_devt - Device Events
933 * @one_bit: indicates this is a non-endpoint event (not used)
934 * @device_event: indicates it's a device event. Should read as 0x00
935 * @type: indicates the type of device event.
948 * 12 - VndrDevTstRcved
949 * @reserved15_12: Reserved, not used
950 * @event_info: Information about this event
951 * @reserved31_25: Reserved, not used
953 struct dwc3_event_devt
{
963 * struct dwc3_event_gevt - Other Core Events
964 * @one_bit: indicates this is a non-endpoint event (not used)
965 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
966 * @phy_port_number: self-explanatory
967 * @reserved31_12: Reserved, not used.
969 struct dwc3_event_gevt
{
972 u32 phy_port_number
:4;
973 u32 reserved31_12
:20;
977 * union dwc3_event - representation of Event Buffer contents
978 * @raw: raw 32-bit event
979 * @type: the type of the event
980 * @depevt: Device Endpoint Event
981 * @devt: Device Event
982 * @gevt: Global Event
986 struct dwc3_event_type type
;
987 struct dwc3_event_depevt depevt
;
988 struct dwc3_event_devt devt
;
989 struct dwc3_event_gevt gevt
;
993 * struct dwc3_gadget_ep_cmd_params - representation of endpoint command
995 * @param2: third parameter
996 * @param1: second parameter
997 * @param0: first parameter
999 struct dwc3_gadget_ep_cmd_params
{
1006 * DWC3 Features to be used as Driver Data
1009 #define DWC3_HAS_PERIPHERAL BIT(0)
1010 #define DWC3_HAS_XHCI BIT(1)
1011 #define DWC3_HAS_OTG BIT(3)
1014 int dwc3_gadget_resize_tx_fifos(struct dwc3
*dwc
);
1015 void dwc3_of_parse(struct dwc3
*dwc
);
1016 int dwc3_init(struct dwc3
*dwc
);
1017 void dwc3_remove(struct dwc3
*dwc
);
1019 static inline int dwc3_host_init(struct dwc3
*dwc
)
1021 static inline void dwc3_host_exit(struct dwc3
*dwc
)
1024 #ifdef CONFIG_USB_DWC3_GADGET
1025 int dwc3_gadget_init(struct dwc3
*dwc
);
1026 void dwc3_gadget_exit(struct dwc3
*dwc
);
1027 int dwc3_gadget_set_test_mode(struct dwc3
*dwc
, int mode
);
1028 int dwc3_gadget_get_link_state(struct dwc3
*dwc
);
1029 int dwc3_gadget_set_link_state(struct dwc3
*dwc
, enum dwc3_link_state state
);
1030 int dwc3_send_gadget_ep_cmd(struct dwc3
*dwc
, unsigned ep
,
1031 unsigned cmd
, struct dwc3_gadget_ep_cmd_params
*params
);
1032 int dwc3_send_gadget_generic_command(struct dwc3
*dwc
, unsigned cmd
, u32 param
);
1034 static inline int dwc3_gadget_init(struct dwc3
*dwc
)
1036 static inline void dwc3_gadget_exit(struct dwc3
*dwc
)
1038 static inline int dwc3_gadget_set_test_mode(struct dwc3
*dwc
, int mode
)
1040 static inline int dwc3_gadget_get_link_state(struct dwc3
*dwc
)
1042 static inline int dwc3_gadget_set_link_state(struct dwc3
*dwc
,
1043 enum dwc3_link_state state
)
1046 static inline int dwc3_send_gadget_ep_cmd(struct dwc3
*dwc
, unsigned ep
,
1047 unsigned cmd
, struct dwc3_gadget_ep_cmd_params
*params
)
1049 static inline int dwc3_send_gadget_generic_command(struct dwc3
*dwc
,
1054 #endif /* __DRIVERS_USB_DWC3_CORE_H */