include/power/stpmic1.h

   1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
   2 /*
   3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4  */
   5
   6 #ifndef __PMIC_STPMIC1_H_
   7 #define __PMIC_STPMIC1_H_
   8
   9 #define STPMIC1_MAIN_CR                 0x10
  10 #define STPMIC1_BUCKS_MRST_CR           0x18
  11 #define STPMIC1_LDOS_MRST_CR            0x1a
  12 #define STPMIC1_BUCKX_MAIN_CR(buck)     (0x20 + (buck))
  13 #define STPMIC1_REFDDR_MAIN_CR          0x24
  14 #define STPMIC1_LDOX_MAIN_CR(ldo)       (0x25 + (ldo))
  15 #define STPMIC1_BST_SW_CR               0x40
  16 #define STPMIC1_NVM_SR                  0xb8
  17 #define STPMIC1_NVM_CR                  0xb9
  18
  19 /* Main PMIC Control Register (MAIN_CR) */
  20 #define STPMIC1_SWOFF                   BIT(0)
  21 #define STPMIC1_RREQ_EN                 BIT(1)
  22
  23 /* BUCKS_MRST_CR */
  24 #define STPMIC1_MRST_BUCK(buck)         BIT(buck)
  25 #define STPMIC1_MRST_BUCK_ALL           GENMASK(3, 0)
  26
  27 /* LDOS_MRST_CR */
  28 #define STPMIC1_MRST_LDO(ldo)           BIT(ldo)
  29 #define STPMIC1_MRST_LDO_ALL            GENMASK(6, 0)
  30
  31 /* BUCKx_MAIN_CR (x=1...4) */
  32 #define STPMIC1_BUCK_ENA                BIT(0)
  33 #define STPMIC1_BUCK_PREG_MODE          BIT(1)
  34 #define STPMIC1_BUCK_VOUT_MASK          GENMASK(7, 2)
  35 #define STPMIC1_BUCK_VOUT_SHIFT         2
  36 #define STPMIC1_BUCK_VOUT(sel)          (sel << STPMIC1_BUCK_VOUT_SHIFT)
  37
  38 #define STPMIC1_BUCK2_1200000V          STPMIC1_BUCK_VOUT(24)
  39 #define STPMIC1_BUCK2_1350000V          STPMIC1_BUCK_VOUT(30)
  40
  41 #define STPMIC1_BUCK3_1800000V          STPMIC1_BUCK_VOUT(39)
  42
  43 /* REFDDR_MAIN_CR */
  44 #define STPMIC1_VREF_ENA                BIT(0)
  45
  46 /* LDOX_MAIN_CR */
  47 #define STPMIC1_LDO_ENA                 BIT(0)
  48 #define STPMIC1_LDO12356_VOUT_MASK      GENMASK(6, 2)
  49 #define STPMIC1_LDO12356_VOUT_SHIFT     2
  50 #define STPMIC1_LDO_VOUT(sel)           (sel << STPMIC1_LDO12356_VOUT_SHIFT)
  51
  52 #define STPMIC1_LDO3_MODE               BIT(7)
  53 #define STPMIC1_LDO3_DDR_SEL            31
  54 #define STPMIC1_LDO3_1800000            STPMIC1_LDO_VOUT(9)
  55
  56 #define STPMIC1_LDO4_UV                 3300000
  57
  58 /* BST_SW_CR */
  59 #define STPMIC1_BST_ON                  BIT(0)
  60 #define STPMIC1_VBUSOTG_ON              BIT(1)
  61 #define STPMIC1_SWOUT_ON                BIT(2)
  62 #define STPMIC1_PWR_SW_ON               (STPMIC1_VBUSOTG_ON | STPMIC1_SWOUT_ON)
  63
  64 /* NVM_SR */
  65 #define STPMIC1_NVM_BUSY                BIT(0)
  66
  67 /* NVM_CR */
  68 #define STPMIC1_NVM_CMD_PROGRAM         1
  69 #define STPMIC1_NVM_CMD_READ            2
  70
  71 /* Timeout */
  72 #define STPMIC1_DEFAULT_START_UP_DELAY_MS       1
  73 #define STPMIC1_DEFAULT_STOP_DELAY_MS           5
  74 #define STPMIC1_USB_BOOST_START_UP_DELAY_MS     10
  75
  76 enum {
  77         STPMIC1_BUCK1,
  78         STPMIC1_BUCK2,
  79         STPMIC1_BUCK3,
  80         STPMIC1_BUCK4,
  81         STPMIC1_MAX_BUCK,
  82 };
  83
  84 enum {
  85         STPMIC1_PREG_MODE_HP,
  86         STPMIC1_PREG_MODE_LP,
  87 };
  88
  89 enum {
  90         STPMIC1_LDO1,
  91         STPMIC1_LDO2,
  92         STPMIC1_LDO3,
  93         STPMIC1_LDO4,
  94         STPMIC1_LDO5,
  95         STPMIC1_LDO6,
  96         STPMIC1_MAX_LDO,
  97 };
  98
  99 enum {
 100         STPMIC1_LDO_MODE_NORMAL,
 101         STPMIC1_LDO_MODE_BYPASS,
 102         STPMIC1_LDO_MODE_SINK_SOURCE,
 103 };
 104
 105 enum {
 106         STPMIC1_PWR_SW1,
 107         STPMIC1_PWR_SW2,
 108         STPMIC1_MAX_PWR_SW,
 109 };
 110
 111 int stpmic1_shadow_read_byte(u8 addr, u8 *buf);
 112 int stpmic1_shadow_write_byte(u8 addr, u8 *buf);
 113 int stpmic1_nvm_read_byte(u8 addr, u8 *buf);
 114 int stpmic1_nvm_write_byte(u8 addr, u8 *buf);
 115 int stpmic1_nvm_read_all(u8 *buf, int buf_len);
 116 int stpmic1_nvm_write_all(u8 *buf, int buf_len);
 117 #endif